| Stephen Warren | c80efba | 2012-04-20 16:57:38 -0600 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | /include/ "tegra20.dtsi" |
| 4 | |
| 5 | / { |
| 6 | model = "NVIDIA Tegra2 Whistler evaluation board"; |
| 7 | compatible = "nvidia,whistler", "nvidia,tegra20"; |
| 8 | |
| 9 | memory { |
| 10 | reg = <0x00000000 0x20000000>; |
| 11 | }; |
| 12 | |
| 13 | pinmux { |
| 14 | pinctrl-names = "default"; |
| 15 | pinctrl-0 = <&state_default>; |
| 16 | |
| 17 | state_default: pinmux { |
| 18 | ata { |
| 19 | nvidia,pins = "ata", "atb", "ate", "gma", "gmb", |
| 20 | "gmc", "gmd", "gpu"; |
| 21 | nvidia,function = "gmi"; |
| 22 | }; |
| 23 | atc { |
| 24 | nvidia,pins = "atc", "atd"; |
| 25 | nvidia,function = "sdio4"; |
| 26 | }; |
| 27 | cdev1 { |
| 28 | nvidia,pins = "cdev1"; |
| 29 | nvidia,function = "plla_out"; |
| 30 | }; |
| 31 | cdev2 { |
| 32 | nvidia,pins = "cdev2"; |
| 33 | nvidia,function = "osc"; |
| 34 | }; |
| 35 | crtp { |
| 36 | nvidia,pins = "crtp"; |
| 37 | nvidia,function = "crt"; |
| 38 | }; |
| 39 | csus { |
| 40 | nvidia,pins = "csus"; |
| 41 | nvidia,function = "vi_sensor_clk"; |
| 42 | }; |
| 43 | dap1 { |
| 44 | nvidia,pins = "dap1"; |
| 45 | nvidia,function = "dap1"; |
| 46 | }; |
| 47 | dap2 { |
| 48 | nvidia,pins = "dap2"; |
| 49 | nvidia,function = "dap2"; |
| 50 | }; |
| 51 | dap3 { |
| 52 | nvidia,pins = "dap3"; |
| 53 | nvidia,function = "dap3"; |
| 54 | }; |
| 55 | dap4 { |
| 56 | nvidia,pins = "dap4"; |
| 57 | nvidia,function = "dap4"; |
| 58 | }; |
| 59 | ddc { |
| 60 | nvidia,pins = "ddc"; |
| 61 | nvidia,function = "i2c2"; |
| 62 | }; |
| 63 | dta { |
| 64 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; |
| 65 | nvidia,function = "vi"; |
| 66 | }; |
| 67 | dte { |
| 68 | nvidia,pins = "dte"; |
| 69 | nvidia,function = "rsvd1"; |
| 70 | }; |
| 71 | dtf { |
| 72 | nvidia,pins = "dtf"; |
| 73 | nvidia,function = "i2c3"; |
| 74 | }; |
| 75 | gme { |
| 76 | nvidia,pins = "gme"; |
| 77 | nvidia,function = "dap5"; |
| 78 | }; |
| 79 | gpu7 { |
| 80 | nvidia,pins = "gpu7"; |
| 81 | nvidia,function = "rtck"; |
| 82 | }; |
| 83 | gpv { |
| 84 | nvidia,pins = "gpv"; |
| 85 | nvidia,function = "pcie"; |
| 86 | }; |
| 87 | hdint { |
| 88 | nvidia,pins = "hdint", "pta"; |
| 89 | nvidia,function = "hdmi"; |
| 90 | }; |
| 91 | i2cp { |
| 92 | nvidia,pins = "i2cp"; |
| 93 | nvidia,function = "i2cp"; |
| 94 | }; |
| 95 | irrx { |
| 96 | nvidia,pins = "irrx", "irtx"; |
| 97 | nvidia,function = "uartb"; |
| 98 | }; |
| 99 | kbca { |
| 100 | nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; |
| 101 | nvidia,function = "kbc"; |
| 102 | }; |
| 103 | kbcb { |
| 104 | nvidia,pins = "kbcb", "kbcd"; |
| 105 | nvidia,function = "sdio2"; |
| 106 | }; |
| 107 | lcsn { |
| 108 | nvidia,pins = "lcsn", "lsck", "lsda", "lsdi", |
| 109 | "spia", "spib", "spic"; |
| 110 | nvidia,function = "spi3"; |
| 111 | }; |
| 112 | ld0 { |
| 113 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 114 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 115 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 116 | "ld15", "ld16", "ld17", "ldc", "ldi", |
| 117 | "lhp0", "lhp1", "lhp2", "lhs", "lm0", |
| 118 | "lm1", "lpp", "lpw0", "lpw1", "lpw2", |
| 119 | "lsc0", "lsc1", "lspi", "lvp0", "lvp1", |
| 120 | "lvs"; |
| 121 | nvidia,function = "displaya"; |
| 122 | }; |
| 123 | owc { |
| 124 | nvidia,pins = "owc", "uac"; |
| 125 | nvidia,function = "owr"; |
| 126 | }; |
| 127 | pmc { |
| 128 | nvidia,pins = "pmc"; |
| 129 | nvidia,function = "pwr_on"; |
| 130 | }; |
| 131 | rm { |
| 132 | nvidia,pins = "rm"; |
| 133 | nvidia,function = "i2c1"; |
| 134 | }; |
| 135 | sdb { |
| 136 | nvidia,pins = "sdb", "sdc", "sdd", "slxa", |
| 137 | "slxc", "slxd", "slxk"; |
| 138 | nvidia,function = "sdio3"; |
| 139 | }; |
| 140 | sdio1 { |
| 141 | nvidia,pins = "sdio1"; |
| 142 | nvidia,function = "sdio1"; |
| 143 | }; |
| 144 | spdi { |
| 145 | nvidia,pins = "spdi", "spdo"; |
| 146 | nvidia,function = "rsvd2"; |
| 147 | }; |
| 148 | spid { |
| 149 | nvidia,pins = "spid", "spie", "spig", "spih"; |
| 150 | nvidia,function = "spi2_alt"; |
| 151 | }; |
| 152 | spif { |
| 153 | nvidia,pins = "spif"; |
| 154 | nvidia,function = "spi2"; |
| 155 | }; |
| 156 | uaa { |
| 157 | nvidia,pins = "uaa", "uab"; |
| 158 | nvidia,function = "uarta"; |
| 159 | }; |
| 160 | uad { |
| 161 | nvidia,pins = "uad"; |
| 162 | nvidia,function = "irda"; |
| 163 | }; |
| 164 | uca { |
| 165 | nvidia,pins = "uca", "ucb"; |
| 166 | nvidia,function = "uartc"; |
| 167 | }; |
| 168 | uda { |
| 169 | nvidia,pins = "uda"; |
| 170 | nvidia,function = "spi1"; |
| 171 | }; |
| 172 | conf_ata { |
| 173 | nvidia,pins = "ata", "atb", "atc", "ddc", "gma", |
| 174 | "gmb", "gmc", "gmd", "irrx", "irtx", |
| 175 | "kbca", "kbcb", "kbcc", "kbcd", "kbce", |
| 176 | "kbcf", "sdc", "sdd", "spie", "spig", |
| 177 | "spih", "uaa", "uab", "uad", "uca", |
| 178 | "ucb"; |
| 179 | nvidia,pull = <2>; |
| 180 | nvidia,tristate = <0>; |
| 181 | }; |
| 182 | conf_atd { |
| 183 | nvidia,pins = "atd", "ate", "cdev1", "csus", |
| 184 | "dap1", "dap2", "dap3", "dap4", "dte", |
| 185 | "dtf", "gpu", "gpu7", "gpv", "i2cp", |
| 186 | "rm", "sdio1", "slxa", "slxc", "slxd", |
| 187 | "slxk", "spdi", "spdo", "uac", "uda"; |
| 188 | nvidia,pull = <0>; |
| 189 | nvidia,tristate = <0>; |
| 190 | }; |
| 191 | conf_cdev2 { |
| 192 | nvidia,pins = "cdev2", "spia", "spib"; |
| 193 | nvidia,pull = <1>; |
| 194 | nvidia,tristate = <1>; |
| 195 | }; |
| 196 | conf_ck32 { |
| 197 | nvidia,pins = "ck32", "ddrc", "lc", "pmca", |
| 198 | "pmcb", "pmcc", "pmcd", "xm2c", |
| 199 | "xm2d"; |
| 200 | nvidia,pull = <0>; |
| 201 | }; |
| 202 | conf_crtp { |
| 203 | nvidia,pins = "crtp"; |
| 204 | nvidia,pull = <0>; |
| 205 | nvidia,tristate = <1>; |
| 206 | }; |
| 207 | conf_dta { |
| 208 | nvidia,pins = "dta", "dtb", "dtc", "dtd", |
| 209 | "spid", "spif"; |
| 210 | nvidia,pull = <1>; |
| 211 | nvidia,tristate = <0>; |
| 212 | }; |
| 213 | conf_gme { |
| 214 | nvidia,pins = "gme", "owc", "pta", "spic"; |
| 215 | nvidia,pull = <2>; |
| 216 | nvidia,tristate = <1>; |
| 217 | }; |
| 218 | conf_ld17_0 { |
| 219 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 220 | "ld23_22"; |
| 221 | nvidia,pull = <1>; |
| 222 | }; |
| 223 | conf_ls { |
| 224 | nvidia,pins = "ls", "pmce"; |
| 225 | nvidia,pull = <2>; |
| 226 | }; |
| 227 | drive_dap1 { |
| 228 | nvidia,pins = "drive_dap1"; |
| 229 | nvidia,high-speed-mode = <0>; |
| 230 | nvidia,schmitt = <1>; |
| 231 | nvidia,low-power-mode = <0>; |
| 232 | nvidia,pull-down-strength = <0>; |
| 233 | nvidia,pull-up-strength = <0>; |
| 234 | nvidia,slew-rate-rising = <0>; |
| 235 | nvidia,slew-rate-falling = <0>; |
| 236 | }; |
| 237 | }; |
| 238 | }; |
| 239 | |
| 240 | i2s@70002800 { |
| 241 | status = "okay"; |
| 242 | }; |
| 243 | |
| 244 | serial@70006000 { |
| 245 | status = "okay"; |
| 246 | clock-frequency = <216000000>; |
| 247 | }; |
| 248 | |
| 249 | i2c@7000d000 { |
| 250 | status = "okay"; |
| 251 | clock-frequency = <100000>; |
| 252 | |
| 253 | codec: codec@1a { |
| 254 | compatible = "wlf,wm8753"; |
| 255 | reg = <0x1a>; |
| 256 | }; |
| 257 | |
| 258 | tca6416: gpio@20 { |
| 259 | compatible = "ti,tca6416"; |
| 260 | reg = <0x20>; |
| 261 | gpio-controller; |
| 262 | #gpio-cells = <2>; |
| 263 | }; |
| Stephen Warren | e7765b3 | 2012-06-25 16:41:25 -0600 | [diff] [blame] | 264 | |
| 265 | max8907@3c { |
| 266 | compatible = "maxim,max8907"; |
| 267 | reg = <0x3c>; |
| 268 | interrupts = <0 86 0x4>; |
| 269 | |
| Stephen Warren | b37ed4a | 2012-09-11 13:13:05 -0600 | [diff] [blame^] | 270 | maxim,system-power-controller; |
| 271 | |
| Stephen Warren | e7765b3 | 2012-06-25 16:41:25 -0600 | [diff] [blame] | 272 | mbatt-supply = <&usb0_vbus_reg>; |
| 273 | in-v1-supply = <&mbatt_reg>; |
| 274 | in-v2-supply = <&mbatt_reg>; |
| 275 | in-v3-supply = <&mbatt_reg>; |
| 276 | in1-supply = <&mbatt_reg>; |
| 277 | in2-supply = <&nvvdd_sv3_reg>; |
| 278 | in3-supply = <&mbatt_reg>; |
| 279 | in4-supply = <&mbatt_reg>; |
| 280 | in5-supply = <&mbatt_reg>; |
| 281 | in6-supply = <&mbatt_reg>; |
| 282 | in7-supply = <&mbatt_reg>; |
| 283 | in8-supply = <&mbatt_reg>; |
| 284 | in9-supply = <&mbatt_reg>; |
| 285 | in10-supply = <&mbatt_reg>; |
| 286 | in11-supply = <&mbatt_reg>; |
| 287 | in12-supply = <&mbatt_reg>; |
| 288 | in13-supply = <&mbatt_reg>; |
| 289 | in14-supply = <&mbatt_reg>; |
| 290 | in15-supply = <&mbatt_reg>; |
| 291 | in16-supply = <&mbatt_reg>; |
| 292 | in17-supply = <&nvvdd_sv3_reg>; |
| 293 | in18-supply = <&nvvdd_sv3_reg>; |
| 294 | in19-supply = <&mbatt_reg>; |
| 295 | in20-supply = <&mbatt_reg>; |
| 296 | |
| 297 | regulators { |
| 298 | #address-cells = <1>; |
| 299 | #size-cells = <0>; |
| 300 | |
| 301 | mbatt_reg: regulator@0 { |
| 302 | reg = <0>; |
| 303 | regulator-compatible = "mbatt"; |
| 304 | regulator-name = "vbat_pmu"; |
| 305 | regulator-always-on; |
| 306 | }; |
| 307 | |
| 308 | regulator@1 { |
| 309 | reg = <1>; |
| 310 | regulator-compatible = "sd1"; |
| 311 | regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; |
| 312 | regulator-min-microvolt = <1000000>; |
| 313 | regulator-max-microvolt = <1000000>; |
| 314 | regulator-always-on; |
| 315 | }; |
| 316 | |
| 317 | regulator@2 { |
| 318 | reg = <2>; |
| 319 | regulator-compatible = "sd2"; |
| 320 | regulator-name = "nvvdd_sv2,vdd_core"; |
| 321 | regulator-min-microvolt = <1200000>; |
| 322 | regulator-max-microvolt = <1200000>; |
| 323 | regulator-always-on; |
| 324 | }; |
| 325 | |
| 326 | nvvdd_sv3_reg: regulator@3 { |
| 327 | reg = <3>; |
| 328 | regulator-compatible = "sd3"; |
| 329 | regulator-name = "nvvdd_sv3"; |
| 330 | regulator-min-microvolt = <1800000>; |
| 331 | regulator-max-microvolt = <1800000>; |
| 332 | regulator-always-on; |
| 333 | }; |
| 334 | |
| 335 | regulator@4 { |
| 336 | reg = <4>; |
| 337 | regulator-compatible = "ldo1"; |
| 338 | regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; |
| 339 | regulator-min-microvolt = <3300000>; |
| 340 | regulator-max-microvolt = <3300000>; |
| 341 | regulator-always-on; |
| 342 | }; |
| 343 | |
| 344 | regulator@5 { |
| 345 | reg = <5>; |
| 346 | regulator-compatible = "ldo2"; |
| 347 | regulator-name = "nvvdd_ldo2,avdd_pll*"; |
| 348 | regulator-min-microvolt = <1100000>; |
| 349 | regulator-max-microvolt = <1100000>; |
| 350 | regulator-always-on; |
| 351 | }; |
| 352 | |
| 353 | regulator@6 { |
| 354 | reg = <6>; |
| 355 | regulator-compatible = "ldo3"; |
| 356 | regulator-name = "nvvdd_ldo3,vcom_1v8b"; |
| 357 | regulator-min-microvolt = <1800000>; |
| 358 | regulator-max-microvolt = <1800000>; |
| 359 | regulator-always-on; |
| 360 | }; |
| 361 | |
| 362 | regulator@7 { |
| 363 | reg = <7>; |
| 364 | regulator-compatible = "ldo4"; |
| 365 | regulator-name = "nvvdd_ldo4,avdd_usb*"; |
| 366 | regulator-min-microvolt = <3300000>; |
| 367 | regulator-max-microvolt = <3300000>; |
| 368 | regulator-always-on; |
| 369 | }; |
| 370 | |
| 371 | regulator@8 { |
| 372 | reg = <8>; |
| 373 | regulator-compatible = "ldo5"; |
| 374 | regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; |
| 375 | regulator-min-microvolt = <2800000>; |
| 376 | regulator-max-microvolt = <2800000>; |
| 377 | regulator-always-on; |
| 378 | }; |
| 379 | |
| 380 | regulator@9 { |
| 381 | reg = <9>; |
| 382 | regulator-compatible = "ldo6"; |
| 383 | regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; |
| 384 | regulator-min-microvolt = <1800000>; |
| 385 | regulator-max-microvolt = <1800000>; |
| 386 | }; |
| 387 | |
| 388 | regulator@10 { |
| 389 | reg = <10>; |
| 390 | regulator-compatible = "ldo7"; |
| 391 | regulator-name = "nvvdd_ldo7,avddio_audio"; |
| 392 | regulator-min-microvolt = <2800000>; |
| 393 | regulator-max-microvolt = <2800000>; |
| 394 | regulator-always-on; |
| 395 | }; |
| 396 | |
| 397 | regulator@11 { |
| 398 | reg = <11>; |
| 399 | regulator-compatible = "ldo8"; |
| 400 | regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; |
| 401 | regulator-min-microvolt = <3000000>; |
| 402 | regulator-max-microvolt = <3000000>; |
| 403 | }; |
| 404 | |
| 405 | regulator@12 { |
| 406 | reg = <12>; |
| 407 | regulator-compatible = "ldo9"; |
| 408 | regulator-name = "nvvdd_ldo9,avdd_cam*"; |
| 409 | regulator-min-microvolt = <2800000>; |
| 410 | regulator-max-microvolt = <2800000>; |
| 411 | }; |
| 412 | |
| 413 | regulator@13 { |
| 414 | reg = <13>; |
| 415 | regulator-compatible = "ldo10"; |
| 416 | regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; |
| 417 | regulator-min-microvolt = <3000000>; |
| 418 | regulator-max-microvolt = <3000000>; |
| 419 | regulator-always-on; |
| 420 | }; |
| 421 | |
| 422 | regulator@14 { |
| 423 | reg = <14>; |
| 424 | regulator-compatible = "ldo11"; |
| 425 | regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; |
| 426 | regulator-min-microvolt = <3300000>; |
| 427 | regulator-max-microvolt = <3300000>; |
| 428 | }; |
| 429 | |
| 430 | regulator@15 { |
| 431 | reg = <15>; |
| 432 | regulator-compatible = "ldo12"; |
| 433 | regulator-name = "nvvdd_ldo12,vddio_sdio"; |
| 434 | regulator-min-microvolt = <2800000>; |
| 435 | regulator-max-microvolt = <2800000>; |
| 436 | regulator-always-on; |
| 437 | }; |
| 438 | |
| 439 | regulator@16 { |
| 440 | reg = <16>; |
| 441 | regulator-compatible = "ldo13"; |
| 442 | regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; |
| 443 | regulator-min-microvolt = <2800000>; |
| 444 | regulator-max-microvolt = <2800000>; |
| 445 | }; |
| 446 | |
| 447 | regulator@17 { |
| 448 | reg = <17>; |
| 449 | regulator-compatible = "ldo14"; |
| 450 | regulator-name = "nvvdd_ldo14,avdd_vdac"; |
| 451 | regulator-min-microvolt = <2800000>; |
| 452 | regulator-max-microvolt = <2800000>; |
| 453 | }; |
| 454 | |
| 455 | regulator@18 { |
| 456 | reg = <18>; |
| 457 | regulator-compatible = "ldo15"; |
| 458 | regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; |
| 459 | regulator-min-microvolt = <3300000>; |
| 460 | regulator-max-microvolt = <3300000>; |
| 461 | }; |
| 462 | |
| 463 | regulator@19 { |
| 464 | reg = <19>; |
| 465 | regulator-compatible = "ldo16"; |
| 466 | regulator-name = "nvvdd_ldo16,vdd_dbrtr"; |
| 467 | regulator-min-microvolt = <1300000>; |
| 468 | regulator-max-microvolt = <1300000>; |
| 469 | }; |
| 470 | |
| 471 | regulator@20 { |
| 472 | reg = <20>; |
| 473 | regulator-compatible = "ldo17"; |
| 474 | regulator-name = "nvvdd_ldo17,vddio_mipi"; |
| 475 | regulator-min-microvolt = <1200000>; |
| 476 | regulator-max-microvolt = <1200000>; |
| 477 | }; |
| 478 | |
| 479 | regulator@21 { |
| 480 | reg = <21>; |
| 481 | regulator-compatible = "ldo18"; |
| 482 | regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; |
| 483 | regulator-min-microvolt = <1800000>; |
| 484 | regulator-max-microvolt = <1800000>; |
| 485 | }; |
| 486 | |
| 487 | regulator@22 { |
| 488 | reg = <22>; |
| 489 | regulator-compatible = "ldo19"; |
| 490 | regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; |
| 491 | regulator-min-microvolt = <2800000>; |
| 492 | regulator-max-microvolt = <2800000>; |
| 493 | }; |
| 494 | |
| 495 | regulator@23 { |
| 496 | reg = <23>; |
| 497 | regulator-compatible = "ldo20"; |
| 498 | regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; |
| 499 | regulator-min-microvolt = <1200000>; |
| 500 | regulator-max-microvolt = <1200000>; |
| 501 | regulator-always-on; |
| 502 | }; |
| 503 | |
| 504 | regulator@24 { |
| 505 | reg = <24>; |
| 506 | regulator-compatible = "out5v"; |
| 507 | regulator-name = "usb0_vbus_reg"; |
| 508 | }; |
| 509 | |
| 510 | regulator@25 { |
| 511 | reg = <25>; |
| 512 | regulator-compatible = "out33v"; |
| 513 | regulator-name = "pmu_out3v3"; |
| 514 | }; |
| 515 | |
| 516 | regulator@26 { |
| 517 | reg = <26>; |
| 518 | regulator-compatible = "bbat"; |
| 519 | regulator-name = "pmu_bbat"; |
| 520 | regulator-min-microvolt = <2400000>; |
| 521 | regulator-max-microvolt = <2400000>; |
| 522 | regulator-always-on; |
| 523 | }; |
| 524 | |
| 525 | regulator@27 { |
| 526 | reg = <27>; |
| 527 | regulator-compatible = "sdby"; |
| 528 | regulator-name = "vdd_aon"; |
| 529 | regulator-always-on; |
| 530 | }; |
| 531 | |
| 532 | regulator@28 { |
| 533 | reg = <28>; |
| 534 | regulator-compatible = "vrtc"; |
| 535 | regulator-name = "vrtc,pmu_vccadc"; |
| 536 | regulator-always-on; |
| 537 | }; |
| 538 | }; |
| 539 | }; |
| 540 | }; |
| 541 | |
| 542 | pmc { |
| 543 | nvidia,invert-interrupt; |
| Stephen Warren | c80efba | 2012-04-20 16:57:38 -0600 | [diff] [blame] | 544 | }; |
| 545 | |
| 546 | usb@c5000000 { |
| 547 | status = "okay"; |
| 548 | nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ |
| 549 | }; |
| 550 | |
| 551 | usb@c5008000 { |
| 552 | status = "okay"; |
| 553 | nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ |
| 554 | }; |
| 555 | |
| 556 | sdhci@c8000400 { |
| 557 | status = "okay"; |
| 558 | wp-gpios = <&gpio 173 0>; /* gpio PV5 */ |
| 559 | bus-width = <8>; |
| 560 | }; |
| 561 | |
| 562 | sdhci@c8000600 { |
| 563 | status = "okay"; |
| 564 | bus-width = <8>; |
| 565 | }; |
| 566 | |
| Stephen Warren | e7765b3 | 2012-06-25 16:41:25 -0600 | [diff] [blame] | 567 | regulators { |
| 568 | compatible = "simple-bus"; |
| 569 | #address-cells = <1>; |
| 570 | #size-cells = <0>; |
| 571 | |
| 572 | usb0_vbus_reg: regulator { |
| 573 | compatible = "regulator-fixed"; |
| 574 | reg = <0>; |
| 575 | regulator-name = "usb0_vbus"; |
| 576 | regulator-min-microvolt = <5000000>; |
| 577 | regulator-max-microvolt = <5000000>; |
| 578 | regulator-always-on; |
| 579 | }; |
| 580 | }; |
| 581 | |
| Stephen Warren | c80efba | 2012-04-20 16:57:38 -0600 | [diff] [blame] | 582 | sound { |
| 583 | compatible = "nvidia,tegra-audio-wm8753-whistler", |
| 584 | "nvidia,tegra-audio-wm8753"; |
| 585 | nvidia,model = "NVIDIA Tegra Whistler"; |
| 586 | |
| 587 | nvidia,audio-routing = |
| 588 | "Headphone Jack", "LOUT1", |
| 589 | "Headphone Jack", "ROUT1", |
| 590 | "MIC2", "Mic Jack", |
| 591 | "MIC2N", "Mic Jack"; |
| 592 | |
| 593 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 594 | nvidia,audio-codec = <&codec>; |
| 595 | }; |
| 596 | }; |