H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_MSR_H |
| 2 | #define _ASM_X86_MSR_H |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 3 | |
Borislav Petkov | b72e746 | 2015-06-04 18:55:26 +0200 | [diff] [blame] | 4 | #include "msr-index.h" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 5 | |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 6 | #ifndef __ASSEMBLY__ |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 7 | |
| 8 | #include <asm/asm.h> |
| 9 | #include <asm/errno.h> |
Borislav Petkov | 6bc1096 | 2009-05-22 12:12:01 +0200 | [diff] [blame] | 10 | #include <asm/cpumask.h> |
Borislav Petkov | b72e746 | 2015-06-04 18:55:26 +0200 | [diff] [blame] | 11 | #include <uapi/asm/msr.h> |
Borislav Petkov | 6bc1096 | 2009-05-22 12:12:01 +0200 | [diff] [blame] | 12 | |
| 13 | struct msr { |
| 14 | union { |
| 15 | struct { |
| 16 | u32 l; |
| 17 | u32 h; |
| 18 | }; |
| 19 | u64 q; |
| 20 | }; |
| 21 | }; |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 22 | |
Borislav Petkov | 6ede31e | 2009-12-17 00:16:25 +0100 | [diff] [blame] | 23 | struct msr_info { |
| 24 | u32 msr_no; |
| 25 | struct msr reg; |
| 26 | struct msr *msrs; |
| 27 | int err; |
| 28 | }; |
| 29 | |
| 30 | struct msr_regs_info { |
| 31 | u32 *regs; |
| 32 | int err; |
| 33 | }; |
| 34 | |
Andrew Morton | 1e160cc | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 35 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 36 | { |
| 37 | unsigned long low, high; |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 38 | asm volatile(".byte 0x0f,0x01,0xf9" |
| 39 | : "=a" (low), "=d" (high), "=c" (*aux)); |
Max Asbock | 41aefdc | 2008-06-25 14:45:28 -0700 | [diff] [blame] | 40 | return low | ((u64)high << 32); |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 41 | } |
| 42 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 43 | /* |
Jike Song | d4f1b10 | 2008-10-17 13:25:07 +0800 | [diff] [blame] | 44 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
| 45 | * constraint has different meanings. For i386, "A" means exactly |
| 46 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, |
| 47 | * it means rax *or* rdx. |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 48 | */ |
| 49 | #ifdef CONFIG_X86_64 |
| 50 | #define DECLARE_ARGS(val, low, high) unsigned low, high |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 51 | #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 52 | #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
| 53 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
| 54 | #else |
| 55 | #define DECLARE_ARGS(val, low, high) unsigned long long val |
| 56 | #define EAX_EDX_VAL(val, low, high) (val) |
| 57 | #define EAX_EDX_ARGS(val, low, high) "A" (val) |
| 58 | #define EAX_EDX_RET(val, low, high) "=A" (val) |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 59 | #endif |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 60 | |
| 61 | static inline unsigned long long native_read_msr(unsigned int msr) |
| 62 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 63 | DECLARE_ARGS(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 64 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 65 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
| 66 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | static inline unsigned long long native_read_msr_safe(unsigned int msr, |
| 70 | int *err) |
| 71 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 72 | DECLARE_ARGS(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 73 | |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 74 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 75 | "1:\n\t" |
| 76 | ".section .fixup,\"ax\"\n\t" |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 77 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 78 | ".previous\n\t" |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 79 | _ASM_EXTABLE(2b, 3b) |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 80 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
H. Peter Anvin | 0cc0213 | 2009-08-31 14:23:29 -0700 | [diff] [blame] | 81 | : "c" (msr), [fault] "i" (-EIO)); |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 82 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 83 | } |
| 84 | |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 85 | static inline void native_write_msr(unsigned int msr, |
| 86 | unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 87 | { |
Jeremy Fitzhardinge | af2b1c6 | 2008-06-25 00:18:59 -0400 | [diff] [blame] | 88 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 89 | } |
| 90 | |
Frederic Weisbecker | 0ca59dd | 2008-12-24 23:30:02 +0100 | [diff] [blame] | 91 | /* Can be uninlined because referenced by paravirt */ |
| 92 | notrace static inline int native_write_msr_safe(unsigned int msr, |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 93 | unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 94 | { |
| 95 | int err; |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 96 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 97 | "1:\n\t" |
| 98 | ".section .fixup,\"ax\"\n\t" |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 99 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 100 | ".previous\n\t" |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 101 | _ASM_EXTABLE(2b, 3b) |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 102 | : [err] "=a" (err) |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 103 | : "c" (msr), "0" (low), "d" (high), |
H. Peter Anvin | 0cc0213 | 2009-08-31 14:23:29 -0700 | [diff] [blame] | 104 | [fault] "i" (-EIO) |
Jeremy Fitzhardinge | af2b1c6 | 2008-06-25 00:18:59 -0400 | [diff] [blame] | 105 | : "memory"); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 106 | return err; |
| 107 | } |
| 108 | |
Ingo Molnar | cdc7957 | 2008-01-30 13:32:39 +0100 | [diff] [blame] | 109 | extern unsigned long long native_read_tsc(void); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 110 | |
Andre Przywara | 1f975f7 | 2012-06-01 16:52:35 +0200 | [diff] [blame] | 111 | extern int rdmsr_safe_regs(u32 regs[8]); |
| 112 | extern int wrmsr_safe_regs(u32 regs[8]); |
Borislav Petkov | 132ec92 | 2009-08-31 09:50:09 +0200 | [diff] [blame] | 113 | |
Ingo Molnar | 92767af | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 114 | static __always_inline unsigned long long __native_read_tsc(void) |
| 115 | { |
| 116 | DECLARE_ARGS(val, low, high); |
| 117 | |
Ingo Molnar | 92767af | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 118 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
Ingo Molnar | 92767af | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 119 | |
| 120 | return EAX_EDX_VAL(val, low, high); |
| 121 | } |
| 122 | |
Glauber de Oliveira Costa | b8d1fae | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 123 | static inline unsigned long long native_read_pmc(int counter) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 124 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 125 | DECLARE_ARGS(val, low, high); |
| 126 | |
| 127 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); |
| 128 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | #ifdef CONFIG_PARAVIRT |
| 132 | #include <asm/paravirt.h> |
Thomas Gleixner | 96a388d | 2007-10-11 11:20:03 +0200 | [diff] [blame] | 133 | #else |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 134 | #include <linux/errno.h> |
| 135 | /* |
| 136 | * Access to machine-specific registers (available on 586 and better only) |
| 137 | * Note: the rd* operations modify the parameters directly (without using |
| 138 | * pointer indirection), this allows gcc to optimize better |
| 139 | */ |
| 140 | |
Borislav Petkov | 1423bed | 2013-03-04 21:16:19 +0100 | [diff] [blame] | 141 | #define rdmsr(msr, low, high) \ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 142 | do { \ |
| 143 | u64 __val = native_read_msr((msr)); \ |
Borislav Petkov | 1423bed | 2013-03-04 21:16:19 +0100 | [diff] [blame] | 144 | (void)((low) = (u32)__val); \ |
| 145 | (void)((high) = (u32)(__val >> 32)); \ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 146 | } while (0) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 147 | |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 148 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 149 | { |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 150 | native_write_msr(msr, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 151 | } |
| 152 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 153 | #define rdmsrl(msr, val) \ |
| 154 | ((val) = native_read_msr((msr))) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 155 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 156 | #define wrmsrl(msr, val) \ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 157 | native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 158 | |
| 159 | /* wrmsr with exception handling */ |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 160 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 161 | { |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 162 | return native_write_msr_safe(msr, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 163 | } |
| 164 | |
H. Peter Anvin | 060feb6 | 2012-04-19 17:07:34 -0700 | [diff] [blame] | 165 | /* rdmsr with exception handling */ |
Borislav Petkov | 1423bed | 2013-03-04 21:16:19 +0100 | [diff] [blame] | 166 | #define rdmsr_safe(msr, low, high) \ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 167 | ({ \ |
| 168 | int __err; \ |
| 169 | u64 __val = native_read_msr_safe((msr), &__err); \ |
Borislav Petkov | 1423bed | 2013-03-04 21:16:19 +0100 | [diff] [blame] | 170 | (*low) = (u32)__val; \ |
| 171 | (*high) = (u32)(__val >> 32); \ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 172 | __err; \ |
| 173 | }) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 174 | |
Andi Kleen | 1de87bd | 2008-03-22 10:59:28 +0100 | [diff] [blame] | 175 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
| 176 | { |
| 177 | int err; |
| 178 | |
| 179 | *p = native_read_msr_safe(msr, &err); |
| 180 | return err; |
| 181 | } |
Borislav Petkov | 177fed1 | 2009-08-31 09:50:10 +0200 | [diff] [blame] | 182 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 183 | #define rdtscl(low) \ |
Ken Chen | 205516c | 2008-12-16 00:32:21 -0800 | [diff] [blame] | 184 | ((low) = (u32)__native_read_tsc()) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 185 | |
| 186 | #define rdtscll(val) \ |
Ken Chen | 205516c | 2008-12-16 00:32:21 -0800 | [diff] [blame] | 187 | ((val) = __native_read_tsc()) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 188 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 189 | #define rdpmc(counter, low, high) \ |
| 190 | do { \ |
| 191 | u64 _l = native_read_pmc((counter)); \ |
| 192 | (low) = (u32)_l; \ |
| 193 | (high) = (u32)(_l >> 32); \ |
| 194 | } while (0) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 195 | |
Andi Kleen | 1ff4d58 | 2012-06-05 17:56:50 -0700 | [diff] [blame] | 196 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
| 197 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 198 | #define rdtscp(low, high, aux) \ |
| 199 | do { \ |
| 200 | unsigned long long _val = native_read_tscp(&(aux)); \ |
| 201 | (low) = (u32)_val; \ |
| 202 | (high) = (u32)(_val >> 32); \ |
| 203 | } while (0) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 204 | |
| 205 | #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) |
| 206 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 207 | #endif /* !CONFIG_PARAVIRT */ |
| 208 | |
Andy Lutomirski | cf991de | 2015-06-04 17:13:44 -0700 | [diff] [blame] | 209 | /* |
| 210 | * 64-bit version of wrmsr_safe(): |
| 211 | */ |
| 212 | static inline int wrmsrl_safe(u32 msr, u64 val) |
| 213 | { |
| 214 | return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); |
| 215 | } |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 216 | |
Borislav Petkov | 1423bed | 2013-03-04 21:16:19 +0100 | [diff] [blame] | 217 | #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 218 | |
Sheng Yang | 5df9740 | 2009-12-16 13:48:04 +0800 | [diff] [blame] | 219 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 220 | |
Borislav Petkov | 5054225 | 2009-12-11 18:14:40 +0100 | [diff] [blame] | 221 | struct msr *msrs_alloc(void); |
| 222 | void msrs_free(struct msr *msrs); |
Borislav Petkov | 22085a6 | 2014-03-09 18:05:23 +0100 | [diff] [blame] | 223 | int msr_set_bit(u32 msr, u8 bit); |
| 224 | int msr_clear_bit(u32 msr, u8 bit); |
Borislav Petkov | 5054225 | 2009-12-11 18:14:40 +0100 | [diff] [blame] | 225 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 226 | #ifdef CONFIG_SMP |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 227 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
| 228 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
Jacob Pan | 1a6b991 | 2013-10-11 16:54:58 -0700 | [diff] [blame] | 229 | int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
| 230 | int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
Borislav Petkov | b8a4754 | 2009-07-30 11:10:02 +0200 | [diff] [blame] | 231 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
| 232 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 233 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
| 234 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
Jacob Pan | 1a6b991 | 2013-10-11 16:54:58 -0700 | [diff] [blame] | 235 | int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
| 236 | int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
H. Peter Anvin | 8b956bf | 2009-08-31 14:13:48 -0700 | [diff] [blame] | 237 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
| 238 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 239 | #else /* CONFIG_SMP */ |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 240 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 241 | { |
| 242 | rdmsr(msr_no, *l, *h); |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 243 | return 0; |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 244 | } |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 245 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 246 | { |
| 247 | wrmsr(msr_no, l, h); |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 248 | return 0; |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 249 | } |
Jacob Pan | 1a6b991 | 2013-10-11 16:54:58 -0700 | [diff] [blame] | 250 | static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
| 251 | { |
| 252 | rdmsrl(msr_no, *q); |
| 253 | return 0; |
| 254 | } |
| 255 | static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
| 256 | { |
| 257 | wrmsrl(msr_no, q); |
| 258 | return 0; |
| 259 | } |
Rusty Russell | 0d0fbbd | 2009-11-05 22:45:41 +1030 | [diff] [blame] | 260 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
Borislav Petkov | b034c19 | 2009-05-22 13:52:19 +0200 | [diff] [blame] | 261 | struct msr *msrs) |
| 262 | { |
| 263 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); |
| 264 | } |
Rusty Russell | 0d0fbbd | 2009-11-05 22:45:41 +1030 | [diff] [blame] | 265 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
Borislav Petkov | b034c19 | 2009-05-22 13:52:19 +0200 | [diff] [blame] | 266 | struct msr *msrs) |
| 267 | { |
| 268 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); |
| 269 | } |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 270 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
| 271 | u32 *l, u32 *h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 272 | { |
| 273 | return rdmsr_safe(msr_no, l, h); |
| 274 | } |
| 275 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
| 276 | { |
| 277 | return wrmsr_safe(msr_no, l, h); |
| 278 | } |
Jacob Pan | 1a6b991 | 2013-10-11 16:54:58 -0700 | [diff] [blame] | 279 | static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
| 280 | { |
| 281 | return rdmsrl_safe(msr_no, q); |
| 282 | } |
| 283 | static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
| 284 | { |
| 285 | return wrmsrl_safe(msr_no, q); |
| 286 | } |
H. Peter Anvin | 8b956bf | 2009-08-31 14:13:48 -0700 | [diff] [blame] | 287 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
| 288 | { |
| 289 | return rdmsr_safe_regs(regs); |
| 290 | } |
| 291 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
| 292 | { |
| 293 | return wrmsr_safe_regs(regs); |
| 294 | } |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 295 | #endif /* CONFIG_SMP */ |
H. Peter Anvin | ff55df5 | 2009-08-31 14:16:57 -0700 | [diff] [blame] | 296 | #endif /* __ASSEMBLY__ */ |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 297 | #endif /* _ASM_X86_MSR_H */ |