blob: b4209898f11526eb33dd39d53d03b92a6da7e1bb [file] [log] [blame]
Dave Airlief453ba02008-11-07 14:05:41 -08001/*
2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#ifndef __DRM_EDID_H__
24#define __DRM_EDID_H__
25
26#include <linux/types.h>
27
28#define EDID_LENGTH 128
29#define DDC_ADDR 0x50
30
Dave Airlief453ba02008-11-07 14:05:41 -080031struct est_timings {
32 u8 t1;
33 u8 t2;
34 u8 mfg_rsvd;
35} __attribute__((packed));
36
Michel Dänzer0454bea2009-06-15 16:56:07 +020037/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
Michel Dänzere14cbee2009-06-23 12:36:32 +020038#define EDID_TIMING_ASPECT_SHIFT 6
Michel Dänzer0454bea2009-06-15 16:56:07 +020039#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
40
41/* need to add 60 */
Michel Dänzere14cbee2009-06-23 12:36:32 +020042#define EDID_TIMING_VFREQ_SHIFT 0
Michel Dänzer0454bea2009-06-15 16:56:07 +020043#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
44
Dave Airlief453ba02008-11-07 14:05:41 -080045struct std_timing {
46 u8 hsize; /* need to multiply by 8 then add 248 */
Michel Dänzer0454bea2009-06-15 16:56:07 +020047 u8 vfreq_aspect;
Dave Airlief453ba02008-11-07 14:05:41 -080048} __attribute__((packed));
49
Michel Dänzere14cbee2009-06-23 12:36:32 +020050#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
51#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
Michel Dänzer0454bea2009-06-15 16:56:07 +020052#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
Michel Dänzere14cbee2009-06-23 12:36:32 +020053#define DRM_EDID_PT_STEREO (1 << 5)
54#define DRM_EDID_PT_INTERLACED (1 << 7)
Michel Dänzer0454bea2009-06-15 16:56:07 +020055
Dave Airlief453ba02008-11-07 14:05:41 -080056/* If detailed data is pixel timing */
57struct detailed_pixel_timing {
58 u8 hactive_lo;
59 u8 hblank_lo;
Michel Dänzer0454bea2009-06-15 16:56:07 +020060 u8 hactive_hblank_hi;
Dave Airlief453ba02008-11-07 14:05:41 -080061 u8 vactive_lo;
62 u8 vblank_lo;
Michel Dänzer0454bea2009-06-15 16:56:07 +020063 u8 vactive_vblank_hi;
Dave Airlief453ba02008-11-07 14:05:41 -080064 u8 hsync_offset_lo;
65 u8 hsync_pulse_width_lo;
Michel Dänzer0454bea2009-06-15 16:56:07 +020066 u8 vsync_offset_pulse_width_lo;
67 u8 hsync_vsync_offset_pulse_width_hi;
Dave Airlief453ba02008-11-07 14:05:41 -080068 u8 width_mm_lo;
69 u8 height_mm_lo;
Michel Dänzer0454bea2009-06-15 16:56:07 +020070 u8 width_height_mm_hi;
Dave Airlief453ba02008-11-07 14:05:41 -080071 u8 hborder;
72 u8 vborder;
Michel Dänzer0454bea2009-06-15 16:56:07 +020073 u8 misc;
Dave Airlief453ba02008-11-07 14:05:41 -080074} __attribute__((packed));
75
76/* If it's not pixel timing, it'll be one of the below */
77struct detailed_data_string {
78 u8 str[13];
79} __attribute__((packed));
80
81struct detailed_data_monitor_range {
82 u8 min_vfreq;
83 u8 max_vfreq;
84 u8 min_hfreq_khz;
85 u8 max_hfreq_khz;
86 u8 pixel_clock_mhz; /* need to multiply by 10 */
Michel Dänzer0454bea2009-06-15 16:56:07 +020087 __le16 sec_gtf_toggle; /* A000=use above, 20=use below */
Dave Airlief453ba02008-11-07 14:05:41 -080088 u8 hfreq_start_khz; /* need to multiply by 2 */
89 u8 c; /* need to divide by 2 */
Michel Dänzer0454bea2009-06-15 16:56:07 +020090 __le16 m;
Dave Airlief453ba02008-11-07 14:05:41 -080091 u8 k;
92 u8 j; /* need to divide by 2 */
93} __attribute__((packed));
94
95struct detailed_data_wpindex {
Michel Dänzere14cbee2009-06-23 12:36:32 +020096 u8 white_yx_lo; /* Lower 2 bits each */
Dave Airlief453ba02008-11-07 14:05:41 -080097 u8 white_x_hi;
98 u8 white_y_hi;
99 u8 gamma; /* need to divide by 100 then add 1 */
100} __attribute__((packed));
101
102struct detailed_data_color_point {
103 u8 windex1;
104 u8 wpindex1[3];
105 u8 windex2;
106 u8 wpindex2[3];
107} __attribute__((packed));
108
Adam Jackson9340d8c2009-12-03 17:44:40 -0500109struct cvt_timing {
110 u8 code[3];
111} __attribute__((packed));
112
Dave Airlief453ba02008-11-07 14:05:41 -0800113struct detailed_non_pixel {
114 u8 pad1;
115 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
116 fb=color point data, fa=standard timing data,
117 f9=undefined, f8=mfg. reserved */
118 u8 pad2;
119 union {
120 struct detailed_data_string str;
121 struct detailed_data_monitor_range range;
122 struct detailed_data_wpindex color;
123 struct std_timing timings[5];
Adam Jackson9340d8c2009-12-03 17:44:40 -0500124 struct cvt_timing cvt[4];
Dave Airlief453ba02008-11-07 14:05:41 -0800125 } data;
126} __attribute__((packed));
127
Adam Jackson2dbdc522009-12-03 17:44:39 -0500128#define EDID_DETAIL_EST_TIMINGS 0xf7
129#define EDID_DETAIL_CVT_3BYTE 0xf8
130#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
Dave Airlief453ba02008-11-07 14:05:41 -0800131#define EDID_DETAIL_STD_MODES 0xfa
132#define EDID_DETAIL_MONITOR_CPDATA 0xfb
133#define EDID_DETAIL_MONITOR_NAME 0xfc
134#define EDID_DETAIL_MONITOR_RANGE 0xfd
135#define EDID_DETAIL_MONITOR_STRING 0xfe
136#define EDID_DETAIL_MONITOR_SERIAL 0xff
137
138struct detailed_timing {
Michel Dänzer0454bea2009-06-15 16:56:07 +0200139 __le16 pixel_clock; /* need to multiply by 10 KHz */
Dave Airlief453ba02008-11-07 14:05:41 -0800140 union {
141 struct detailed_pixel_timing pixel_data;
142 struct detailed_non_pixel other_data;
143 } data;
144} __attribute__((packed));
145
Michel Dänzere14cbee2009-06-23 12:36:32 +0200146#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
147#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
148#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
Michel Dänzer0454bea2009-06-15 16:56:07 +0200149#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
Michel Dänzere14cbee2009-06-23 12:36:32 +0200150#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
151#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
152#define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */
Michel Dänzer0454bea2009-06-15 16:56:07 +0200153
Michel Dänzere14cbee2009-06-23 12:36:32 +0200154#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
155#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
156#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
Michel Dänzer0454bea2009-06-15 16:56:07 +0200157#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
Michel Dänzere14cbee2009-06-23 12:36:32 +0200158#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
159#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
160#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
Michel Dänzer0454bea2009-06-15 16:56:07 +0200161
Dave Airlief453ba02008-11-07 14:05:41 -0800162struct edid {
163 u8 header[8];
164 /* Vendor & product info */
165 u8 mfg_id[2];
166 u8 prod_code[2];
167 u32 serial; /* FIXME: byte order */
168 u8 mfg_week;
169 u8 mfg_year;
170 /* EDID version */
171 u8 version;
172 u8 revision;
173 /* Display info: */
Michel Dänzer0454bea2009-06-15 16:56:07 +0200174 u8 input;
Dave Airlief453ba02008-11-07 14:05:41 -0800175 u8 width_cm;
176 u8 height_cm;
177 u8 gamma;
Michel Dänzer0454bea2009-06-15 16:56:07 +0200178 u8 features;
Dave Airlief453ba02008-11-07 14:05:41 -0800179 /* Color characteristics */
180 u8 red_green_lo;
181 u8 black_white_lo;
182 u8 red_x;
183 u8 red_y;
184 u8 green_x;
185 u8 green_y;
186 u8 blue_x;
187 u8 blue_y;
188 u8 white_x;
189 u8 white_y;
190 /* Est. timings and mfg rsvd timings*/
191 struct est_timings established_timings;
192 /* Standard timings 1-8*/
193 struct std_timing standard_timings[8];
194 /* Detailing timings 1-4 */
195 struct detailed_timing detailed_timings[4];
196 /* Number of 128 byte ext. blocks */
197 u8 extensions;
198 /* Checksum */
199 u8 checksum;
200} __attribute__((packed));
201
Dave Airlief453ba02008-11-07 14:05:41 -0800202#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
203
Alex Deucher3c537882010-02-05 04:21:19 -0500204/* define the number of Extension EDID block */
205#define DRM_MAX_EDID_EXT_NUM 4
206
Dave Airlief453ba02008-11-07 14:05:41 -0800207#endif /* __DRM_EDID_H__ */