blob: d35f90527c38d030fe37d72984352d900f4c4f1d [file] [log] [blame]
Felipe Balbi72246da2011-08-19 18:10:58 +03001/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
Felipe Balbi72246da2011-08-19 18:10:58 +03005 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
Felipe Balbia72e6582011-09-05 13:37:28 +030039#include <linux/module.h>
Felipe Balbi72246da2011-08-19 18:10:58 +030040#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/ioport.h>
47#include <linux/io.h>
48#include <linux/list.h>
49#include <linux/delay.h>
50#include <linux/dma-mapping.h>
51
52#include <linux/usb/ch9.h>
53#include <linux/usb/gadget.h>
54
55#include "core.h"
56#include "gadget.h"
57#include "io.h"
58
59#include "debug.h"
60
61/**
62 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
63 * @dwc: pointer to our context structure
64 */
65static void dwc3_core_soft_reset(struct dwc3 *dwc)
66{
67 u32 reg;
68
69 /* Before Resetting PHY, put Core in Reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
71 reg |= DWC3_GCTL_CORESOFTRESET;
72 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
73
74 /* Assert USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
78
79 /* Assert USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
83
84 mdelay(100);
85
86 /* Clear USB3 PHY reset */
87 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
88 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
89 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
90
91 /* Clear USB2 PHY reset */
92 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
93 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
94 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
95
96 /* After PHYs are stable we can take Core out of reset state */
97 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
98 reg &= ~DWC3_GCTL_CORESOFTRESET;
99 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
100}
101
102/**
103 * dwc3_free_one_event_buffer - Frees one event buffer
104 * @dwc: Pointer to our controller context structure
105 * @evt: Pointer to event buffer to be freed
106 */
107static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
108 struct dwc3_event_buffer *evt)
109{
110 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
111 kfree(evt);
112}
113
114/**
115 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
116 * @dwc: Pointer to our controller context structure
117 * @length: size of the event buffer
118 *
119 * Returns a pointer to the allocated event buffer structure on succes
120 * otherwise ERR_PTR(errno).
121 */
122static struct dwc3_event_buffer *__devinit
123dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
124{
125 struct dwc3_event_buffer *evt;
126
127 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
128 if (!evt)
129 return ERR_PTR(-ENOMEM);
130
131 evt->dwc = dwc;
132 evt->length = length;
133 evt->buf = dma_alloc_coherent(dwc->dev, length,
134 &evt->dma, GFP_KERNEL);
135 if (!evt->buf) {
136 kfree(evt);
137 return ERR_PTR(-ENOMEM);
138 }
139
140 return evt;
141}
142
143/**
144 * dwc3_free_event_buffers - frees all allocated event buffers
145 * @dwc: Pointer to our controller context structure
146 */
147static void dwc3_free_event_buffers(struct dwc3 *dwc)
148{
149 struct dwc3_event_buffer *evt;
150 int i;
151
152 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
153 evt = dwc->ev_buffs[i];
154 if (evt) {
155 dwc3_free_one_event_buffer(dwc, evt);
156 dwc->ev_buffs[i] = NULL;
157 }
158 }
159}
160
161/**
162 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
163 * @dwc: Pointer to out controller context structure
164 * @num: number of event buffers to allocate
165 * @length: size of event buffer
166 *
167 * Returns 0 on success otherwise negative errno. In error the case, dwc
168 * may contain some buffers allocated but not all which were requested.
169 */
170static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num,
171 unsigned length)
172{
173 int i;
174
175 for (i = 0; i < num; i++) {
176 struct dwc3_event_buffer *evt;
177
178 evt = dwc3_alloc_one_event_buffer(dwc, length);
179 if (IS_ERR(evt)) {
180 dev_err(dwc->dev, "can't allocate event buffer\n");
181 return PTR_ERR(evt);
182 }
183 dwc->ev_buffs[i] = evt;
184 }
185
186 return 0;
187}
188
189/**
190 * dwc3_event_buffers_setup - setup our allocated event buffers
191 * @dwc: Pointer to out controller context structure
192 *
193 * Returns 0 on success otherwise negative errno.
194 */
195static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
196{
197 struct dwc3_event_buffer *evt;
198 int n;
199
200 for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
201 evt = dwc->ev_buffs[n];
202 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
203 evt->buf, (unsigned long long) evt->dma,
204 evt->length);
205
206 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
207 lower_32_bits(evt->dma));
208 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
209 upper_32_bits(evt->dma));
210 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
211 evt->length & 0xffff);
212 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
213 }
214
215 return 0;
216}
217
218static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
219{
220 struct dwc3_event_buffer *evt;
221 int n;
222
223 for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
224 evt = dwc->ev_buffs[n];
225 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
226 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
227 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
228 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
229 }
230}
231
Felipe Balbi26ceca92011-09-30 10:58:49 +0300232static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
233{
234 struct dwc3_hwparams *parms = &dwc->hwparams;
235
236 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
237 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
238 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
239 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
240 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
241 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
242 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
243 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
244 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
245}
246
Felipe Balbi72246da2011-08-19 18:10:58 +0300247/**
248 * dwc3_core_init - Low-level initialization of DWC3 Core
249 * @dwc: Pointer to our controller context structure
250 *
251 * Returns 0 on success otherwise negative errno.
252 */
253static int __devinit dwc3_core_init(struct dwc3 *dwc)
254{
255 unsigned long timeout;
256 u32 reg;
257 int ret;
258
Sebastian Andrzej Siewior7650bd72011-08-29 13:56:36 +0200259 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
260 /* This should read as U3 followed by revision number */
261 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
262 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
263 ret = -ENODEV;
264 goto err0;
265 }
266 dwc->revision = reg & DWC3_GSNPSREV_MASK;
267
Felipe Balbi72246da2011-08-19 18:10:58 +0300268 dwc3_core_soft_reset(dwc);
269
270 /* issue device SoftReset too */
271 timeout = jiffies + msecs_to_jiffies(500);
272 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
273 do {
274 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
275 if (!(reg & DWC3_DCTL_CSFTRST))
276 break;
277
278 if (time_after(jiffies, timeout)) {
279 dev_err(dwc->dev, "Reset Timed Out\n");
280 ret = -ETIMEDOUT;
281 goto err0;
282 }
283
284 cpu_relax();
285 } while (true);
286
Felipe Balbi72246da2011-08-19 18:10:58 +0300287 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,
288 DWC3_EVENT_BUFFERS_SIZE);
289 if (ret) {
290 dev_err(dwc->dev, "failed to allocate event buffers\n");
291 ret = -ENOMEM;
292 goto err1;
293 }
294
295 ret = dwc3_event_buffers_setup(dwc);
296 if (ret) {
297 dev_err(dwc->dev, "failed to setup event buffers\n");
298 goto err1;
299 }
300
Felipe Balbi26ceca92011-09-30 10:58:49 +0300301 dwc3_cache_hwparams(dwc);
302
Felipe Balbi72246da2011-08-19 18:10:58 +0300303 return 0;
304
305err1:
306 dwc3_free_event_buffers(dwc);
307
308err0:
309 return ret;
310}
311
312static void dwc3_core_exit(struct dwc3 *dwc)
313{
314 dwc3_event_buffers_cleanup(dwc);
315 dwc3_free_event_buffers(dwc);
316}
317
318#define DWC3_ALIGN_MASK (16 - 1)
319
320static int __devinit dwc3_probe(struct platform_device *pdev)
321{
322 const struct platform_device_id *id = platform_get_device_id(pdev);
323 struct resource *res;
324 struct dwc3 *dwc;
325 void __iomem *regs;
326 unsigned int features = id->driver_data;
327 int ret = -ENOMEM;
328 int irq;
329 void *mem;
330
331 mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
332 if (!mem) {
333 dev_err(&pdev->dev, "not enough memory\n");
334 goto err0;
335 }
336 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
337 dwc->mem = mem;
338
339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
340 if (!res) {
341 dev_err(&pdev->dev, "missing resource\n");
342 goto err1;
343 }
344
345 res = request_mem_region(res->start, resource_size(res),
346 dev_name(&pdev->dev));
347 if (!res) {
348 dev_err(&pdev->dev, "can't request mem region\n");
349 goto err1;
350 }
351
352 regs = ioremap(res->start, resource_size(res));
353 if (!regs) {
354 dev_err(&pdev->dev, "ioremap failed\n");
355 goto err2;
356 }
357
358 irq = platform_get_irq(pdev, 0);
359 if (irq < 0) {
360 dev_err(&pdev->dev, "missing IRQ\n");
361 goto err3;
362 }
363
364 spin_lock_init(&dwc->lock);
365 platform_set_drvdata(pdev, dwc);
366
367 dwc->regs = regs;
368 dwc->regs_size = resource_size(res);
369 dwc->dev = &pdev->dev;
370 dwc->irq = irq;
371
372 pm_runtime_enable(&pdev->dev);
373 pm_runtime_get_sync(&pdev->dev);
374 pm_runtime_forbid(&pdev->dev);
375
376 ret = dwc3_core_init(dwc);
377 if (ret) {
378 dev_err(&pdev->dev, "failed to initialize core\n");
379 goto err3;
380 }
381
382 if (features & DWC3_HAS_PERIPHERAL) {
383 ret = dwc3_gadget_init(dwc);
384 if (ret) {
385 dev_err(&pdev->dev, "failed to initialized gadget\n");
386 goto err4;
387 }
388 }
389
390 ret = dwc3_debugfs_init(dwc);
391 if (ret) {
392 dev_err(&pdev->dev, "failed to initialize debugfs\n");
393 goto err5;
394 }
395
396 pm_runtime_allow(&pdev->dev);
397
398 return 0;
399
400err5:
401 if (features & DWC3_HAS_PERIPHERAL)
402 dwc3_gadget_exit(dwc);
403
404err4:
405 dwc3_core_exit(dwc);
406
407err3:
408 iounmap(regs);
409
410err2:
411 release_mem_region(res->start, resource_size(res));
412
413err1:
414 kfree(dwc->mem);
415
416err0:
417 return ret;
418}
419
420static int __devexit dwc3_remove(struct platform_device *pdev)
421{
422 const struct platform_device_id *id = platform_get_device_id(pdev);
423 struct dwc3 *dwc = platform_get_drvdata(pdev);
424 struct resource *res;
425 unsigned int features = id->driver_data;
426
427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428
429 pm_runtime_put(&pdev->dev);
430 pm_runtime_disable(&pdev->dev);
431
432 dwc3_debugfs_exit(dwc);
433
434 if (features & DWC3_HAS_PERIPHERAL)
435 dwc3_gadget_exit(dwc);
436
437 dwc3_core_exit(dwc);
438 release_mem_region(res->start, resource_size(res));
439 iounmap(dwc->regs);
440 kfree(dwc->mem);
441
442 return 0;
443}
444
445static const struct platform_device_id dwc3_id_table[] __devinitconst = {
446 {
447 .name = "dwc3-omap",
448 .driver_data = (DWC3_HAS_PERIPHERAL
449 | DWC3_HAS_XHCI
450 | DWC3_HAS_OTG),
451 },
452 {
453 .name = "dwc3-pci",
454 .driver_data = DWC3_HAS_PERIPHERAL,
455 },
456 { }, /* Terminating Entry */
457};
458MODULE_DEVICE_TABLE(platform, dwc3_id_table);
459
460static struct platform_driver dwc3_driver = {
461 .probe = dwc3_probe,
462 .remove = __devexit_p(dwc3_remove),
463 .driver = {
464 .name = "dwc3",
465 },
466 .id_table = dwc3_id_table,
467};
468
469MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
470MODULE_LICENSE("Dual BSD/GPL");
471MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
472
473static int __devinit dwc3_init(void)
474{
475 return platform_driver_register(&dwc3_driver);
476}
477module_init(dwc3_init);
478
479static void __exit dwc3_exit(void)
480{
481 platform_driver_unregister(&dwc3_driver);
482}
483module_exit(dwc3_exit);