blob: 1a82f3a17681b77926a11c29ba23cbdc27d8b6b5 [file] [log] [blame]
Kishon Vijay Abraham I26a84b32012-08-22 14:10:02 +05301#
2# Bus Devices
3#
4
5menu "Bus devices"
6
Geert Uytterhoeven13fbf3c2015-02-05 11:11:24 +01007config ARM_CCI
Olof Johansson47f36e42015-04-03 13:38:43 -07008 bool
9
Suzuki K. Poulosef4d58932015-05-26 10:53:14 +010010config ARM_CCI_PMU
11 bool
12 select ARM_CCI
13
Olof Johansson47f36e42015-04-03 13:38:43 -070014config ARM_CCI400_COMMON
15 bool
16 select ARM_CCI
17
18config ARM_CCI400_PMU
19 bool "ARM CCI400 PMU support"
Suzuki K. Poulose85bbba72015-05-26 10:53:10 +010020 depends on (ARM && CPU_V7) || ARM64
21 depends on PERF_EVENTS
Olof Johansson47f36e42015-04-03 13:38:43 -070022 select ARM_CCI400_COMMON
Suzuki K. Poulosef4d58932015-05-26 10:53:14 +010023 select ARM_CCI_PMU
Geert Uytterhoeven13fbf3c2015-02-05 11:11:24 +010024 help
Suzuki K. Poulose85bbba72015-05-26 10:53:10 +010025 Support for PMU events monitoring on the ARM CCI-400 (cache coherent
26 interconnect). CCI-400 supports counting events related to the
27 connected slave/master interfaces.
Olof Johansson47f36e42015-04-03 13:38:43 -070028
29config ARM_CCI400_PORT_CTRL
30 bool
31 depends on ARM && OF && CPU_V7
32 select ARM_CCI400_COMMON
33 help
34 Low level power management driver for CCI400 cache coherent
35 interconnect for ARM platforms.
Geert Uytterhoeven13fbf3c2015-02-05 11:11:24 +010036
Suzuki K. Poulosea95791e2015-05-26 10:53:15 +010037config ARM_CCI500_PMU
38 bool "ARM CCI500 PMU support"
39 default y
40 depends on (ARM && CPU_V7) || ARM64
41 depends on PERF_EVENTS
42 select ARM_CCI_PMU
43 help
44 Support for PMU events monitoring on the ARM CCI-500 cache coherent
45 interconnect. CCI-500 provides 8 independent event counters, which
46 can count events pertaining to the slave/master interfaces as well
47 as the internal events to the CCI.
48
49 If unsure, say Y
50
Geert Uytterhoeven13fbf3c2015-02-05 11:11:24 +010051config ARM_CCN
52 bool "ARM CCN driver support"
53 depends on ARM || ARM64
54 depends on PERF_EVENTS
55 help
56 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
57 interconnect.
58
Florian Fainelli44127b72014-05-19 13:05:59 -070059config BRCMSTB_GISB_ARB
60 bool "Broadcom STB GISB bus arbiter"
Kevin Cernekeedd1d78a2014-11-25 16:49:49 -080061 depends on ARM || MIPS
Florian Fainelli44127b72014-05-19 13:05:59 -070062 help
63 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
64 arbiter. This driver provides timeout and target abort error handling
65 and internal bus master decoding.
66
Huang Shijie85bf6d42013-05-28 14:20:07 +080067config IMX_WEIM
68 bool "Freescale EIM DRIVER"
69 depends on ARCH_MXC
70 help
Alexander Shiyan3f98b6b2013-06-29 08:27:54 +040071 Driver for i.MX WEIM controller.
Huang Shijie85bf6d42013-05-28 14:20:07 +080072 The WEIM(Wireless External Interface Module) works like a bus.
73 You can attach many different devices on it, such as NOR, onenand.
Huang Shijie85bf6d42013-05-28 14:20:07 +080074
James Hogan8286ae02015-03-25 15:39:50 +000075config MIPS_CDMM
76 bool "MIPS Common Device Memory Map (CDMM) Driver"
77 depends on CPU_MIPSR2
78 help
79 Driver needed for the MIPS Common Device Memory Map bus in MIPS
80 cores. This bus is for per-CPU tightly coupled devices such as the
81 Fast Debug Channel (FDC).
82
83 For this to work, either your bootloader needs to enable the CDMM
84 region at an unused physical address on the boot CPU, or else your
85 platform code needs to implement mips_cdmm_phys_base() (see
86 asm/cdmm.h).
87
Thomas Petazzonifddddb52013-03-21 17:59:14 +010088config MVEBU_MBUS
89 bool
90 depends on PLAT_ORION
91 help
92 Driver needed for the MBus configuration on Marvell EBU SoCs
93 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
94
Geert Uytterhoeven13fbf3c2015-02-05 11:11:24 +010095config OMAP_INTERCONNECT
96 tristate "OMAP INTERCONNECT DRIVER"
97 depends on ARCH_OMAP2PLUS
98
99 help
100 Driver to enable OMAP interconnect error handling driver.
101
Kishon Vijay Abraham I26a84b32012-08-22 14:10:02 +0530102config OMAP_OCP2SCP
103 tristate "OMAP OCP2SCP DRIVER"
Tony Lindgren770b6cb2012-12-16 12:28:46 -0800104 depends on ARCH_OMAP2PLUS
Kishon Vijay Abraham I26a84b32012-08-22 14:10:02 +0530105 help
106 Driver to enable ocp2scp module which transforms ocp interface
107 protocol to scp protocol. In OMAP4, USB PHY is connected via
108 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
109 OCP2SCP.
110
Geert Uytterhoeven89d463e2015-02-05 11:11:28 +0100111config SIMPLE_PM_BUS
112 bool "Simple Power-Managed Bus Driver"
113 depends on OF && PM
114 depends on ARCH_SHMOBILE || COMPILE_TEST
Santosh Shilimkar0ee72612012-09-14 14:50:34 +0530115 help
Geert Uytterhoeven89d463e2015-02-05 11:11:28 +0100116 Driver for transparent busses that don't need a real driver, but
117 where the bus controller is part of a PM domain, or under the control
118 of a functional clock, and thus relies on runtime PM for managing
119 this PM domain and/or clock.
120 An example of such a bus controller is the Renesas Bus State
121 Controller (BSC, sometimes called "LBSC within Bus Bridge", or
122 "External Bus Interface") as found on several Renesas ARM SoCs.
Pawel Molla33b0da2014-07-22 18:32:59 +0100123
Pawel Moll3b9334a2014-04-30 16:46:29 +0100124config VEXPRESS_CONFIG
125 bool "Versatile Express configuration bus"
126 default y if ARCH_VEXPRESS
127 depends on ARM || ARM64
Arnd Bergmannb33cdd22014-05-26 17:25:22 +0200128 depends on OF
Pawel Moll3b9334a2014-04-30 16:46:29 +0100129 select REGMAP
130 help
131 Platform configuration infrastructure for the ARM Ltd.
132 Versatile Express.
Kishon Vijay Abraham I26a84b32012-08-22 14:10:02 +0530133endmenu