Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * OMAP DMAengine support |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | #include <linux/dmaengine.h> |
| 9 | #include <linux/dma-mapping.h> |
| 10 | #include <linux/err.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/list.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/omap-dma.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/spinlock.h> |
| 19 | |
| 20 | #include "virt-dma.h" |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 21 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 22 | #include <plat/dma.h> |
| 23 | |
Tony Lindgren | 27615a9 | 2012-10-15 16:24:23 -0700 | [diff] [blame^] | 24 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 25 | #define dma_omap2plus() 1 |
| 26 | #else |
| 27 | #define dma_omap2plus() 0 |
| 28 | #endif |
| 29 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 30 | struct omap_dmadev { |
| 31 | struct dma_device ddev; |
| 32 | spinlock_t lock; |
| 33 | struct tasklet_struct task; |
| 34 | struct list_head pending; |
| 35 | }; |
| 36 | |
| 37 | struct omap_chan { |
| 38 | struct virt_dma_chan vc; |
| 39 | struct list_head node; |
| 40 | |
| 41 | struct dma_slave_config cfg; |
| 42 | unsigned dma_sig; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 43 | bool cyclic; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 44 | bool paused; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 45 | |
| 46 | int dma_ch; |
| 47 | struct omap_desc *desc; |
| 48 | unsigned sgidx; |
| 49 | }; |
| 50 | |
| 51 | struct omap_sg { |
| 52 | dma_addr_t addr; |
| 53 | uint32_t en; /* number of elements (24-bit) */ |
| 54 | uint32_t fn; /* number of frames (16-bit) */ |
| 55 | }; |
| 56 | |
| 57 | struct omap_desc { |
| 58 | struct virt_dma_desc vd; |
| 59 | enum dma_transfer_direction dir; |
| 60 | dma_addr_t dev_addr; |
| 61 | |
Russell King | 7c836bc | 2012-06-18 16:45:19 +0100 | [diff] [blame] | 62 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 63 | uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */ |
| 64 | uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */ |
| 65 | uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */ |
| 66 | uint8_t periph_port; /* Peripheral port */ |
| 67 | |
| 68 | unsigned sglen; |
| 69 | struct omap_sg sg[0]; |
| 70 | }; |
| 71 | |
| 72 | static const unsigned es_bytes[] = { |
| 73 | [OMAP_DMA_DATA_TYPE_S8] = 1, |
| 74 | [OMAP_DMA_DATA_TYPE_S16] = 2, |
| 75 | [OMAP_DMA_DATA_TYPE_S32] = 4, |
| 76 | }; |
| 77 | |
| 78 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
| 79 | { |
| 80 | return container_of(d, struct omap_dmadev, ddev); |
| 81 | } |
| 82 | |
| 83 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) |
| 84 | { |
| 85 | return container_of(c, struct omap_chan, vc.chan); |
| 86 | } |
| 87 | |
| 88 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) |
| 89 | { |
| 90 | return container_of(t, struct omap_desc, vd.tx); |
| 91 | } |
| 92 | |
| 93 | static void omap_dma_desc_free(struct virt_dma_desc *vd) |
| 94 | { |
| 95 | kfree(container_of(vd, struct omap_desc, vd)); |
| 96 | } |
| 97 | |
| 98 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
| 99 | unsigned idx) |
| 100 | { |
| 101 | struct omap_sg *sg = d->sg + idx; |
| 102 | |
| 103 | if (d->dir == DMA_DEV_TO_MEM) |
| 104 | omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF, |
| 105 | OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0); |
| 106 | else |
| 107 | omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF, |
| 108 | OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0); |
| 109 | |
| 110 | omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn, |
| 111 | d->sync_mode, c->dma_sig, d->sync_type); |
| 112 | |
| 113 | omap_start_dma(c->dma_ch); |
| 114 | } |
| 115 | |
| 116 | static void omap_dma_start_desc(struct omap_chan *c) |
| 117 | { |
| 118 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); |
| 119 | struct omap_desc *d; |
| 120 | |
| 121 | if (!vd) { |
| 122 | c->desc = NULL; |
| 123 | return; |
| 124 | } |
| 125 | |
| 126 | list_del(&vd->node); |
| 127 | |
| 128 | c->desc = d = to_omap_dma_desc(&vd->tx); |
| 129 | c->sgidx = 0; |
| 130 | |
| 131 | if (d->dir == DMA_DEV_TO_MEM) |
| 132 | omap_set_dma_src_params(c->dma_ch, d->periph_port, |
Russell King | 7c836bc | 2012-06-18 16:45:19 +0100 | [diff] [blame] | 133 | OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 134 | else |
| 135 | omap_set_dma_dest_params(c->dma_ch, d->periph_port, |
Russell King | 7c836bc | 2012-06-18 16:45:19 +0100 | [diff] [blame] | 136 | OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 137 | |
| 138 | omap_dma_start_sg(c, d, 0); |
| 139 | } |
| 140 | |
| 141 | static void omap_dma_callback(int ch, u16 status, void *data) |
| 142 | { |
| 143 | struct omap_chan *c = data; |
| 144 | struct omap_desc *d; |
| 145 | unsigned long flags; |
| 146 | |
| 147 | spin_lock_irqsave(&c->vc.lock, flags); |
| 148 | d = c->desc; |
| 149 | if (d) { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 150 | if (!c->cyclic) { |
| 151 | if (++c->sgidx < d->sglen) { |
| 152 | omap_dma_start_sg(c, d, c->sgidx); |
| 153 | } else { |
| 154 | omap_dma_start_desc(c); |
| 155 | vchan_cookie_complete(&d->vd); |
| 156 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 157 | } else { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 158 | vchan_cyclic_callback(&d->vd); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 159 | } |
| 160 | } |
| 161 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * This callback schedules all pending channels. We could be more |
| 166 | * clever here by postponing allocation of the real DMA channels to |
| 167 | * this point, and freeing them when our virtual channel becomes idle. |
| 168 | * |
| 169 | * We would then need to deal with 'all channels in-use' |
| 170 | */ |
| 171 | static void omap_dma_sched(unsigned long data) |
| 172 | { |
| 173 | struct omap_dmadev *d = (struct omap_dmadev *)data; |
| 174 | LIST_HEAD(head); |
| 175 | |
| 176 | spin_lock_irq(&d->lock); |
| 177 | list_splice_tail_init(&d->pending, &head); |
| 178 | spin_unlock_irq(&d->lock); |
| 179 | |
| 180 | while (!list_empty(&head)) { |
| 181 | struct omap_chan *c = list_first_entry(&head, |
| 182 | struct omap_chan, node); |
| 183 | |
| 184 | spin_lock_irq(&c->vc.lock); |
| 185 | list_del_init(&c->node); |
| 186 | omap_dma_start_desc(c); |
| 187 | spin_unlock_irq(&c->vc.lock); |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) |
| 192 | { |
| 193 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 194 | |
| 195 | dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig); |
| 196 | |
| 197 | return omap_request_dma(c->dma_sig, "DMA engine", |
| 198 | omap_dma_callback, c, &c->dma_ch); |
| 199 | } |
| 200 | |
| 201 | static void omap_dma_free_chan_resources(struct dma_chan *chan) |
| 202 | { |
| 203 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 204 | |
| 205 | vchan_free_chan_resources(&c->vc); |
| 206 | omap_free_dma(c->dma_ch); |
| 207 | |
| 208 | dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig); |
| 209 | } |
| 210 | |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 211 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
| 212 | { |
| 213 | return sg->en * sg->fn; |
| 214 | } |
| 215 | |
| 216 | static size_t omap_dma_desc_size(struct omap_desc *d) |
| 217 | { |
| 218 | unsigned i; |
| 219 | size_t size; |
| 220 | |
| 221 | for (size = i = 0; i < d->sglen; i++) |
| 222 | size += omap_dma_sg_size(&d->sg[i]); |
| 223 | |
| 224 | return size * es_bytes[d->es]; |
| 225 | } |
| 226 | |
| 227 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) |
| 228 | { |
| 229 | unsigned i; |
| 230 | size_t size, es_size = es_bytes[d->es]; |
| 231 | |
| 232 | for (size = i = 0; i < d->sglen; i++) { |
| 233 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; |
| 234 | |
| 235 | if (size) |
| 236 | size += this_size; |
| 237 | else if (addr >= d->sg[i].addr && |
| 238 | addr < d->sg[i].addr + this_size) |
| 239 | size += d->sg[i].addr + this_size - addr; |
| 240 | } |
| 241 | return size; |
| 242 | } |
| 243 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 244 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
| 245 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
| 246 | { |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 247 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 248 | struct virt_dma_desc *vd; |
| 249 | enum dma_status ret; |
| 250 | unsigned long flags; |
| 251 | |
| 252 | ret = dma_cookie_status(chan, cookie, txstate); |
| 253 | if (ret == DMA_SUCCESS || !txstate) |
| 254 | return ret; |
| 255 | |
| 256 | spin_lock_irqsave(&c->vc.lock, flags); |
| 257 | vd = vchan_find_desc(&c->vc, cookie); |
| 258 | if (vd) { |
| 259 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); |
| 260 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { |
| 261 | struct omap_desc *d = c->desc; |
| 262 | dma_addr_t pos; |
| 263 | |
| 264 | if (d->dir == DMA_MEM_TO_DEV) |
| 265 | pos = omap_get_dma_src_pos(c->dma_ch); |
| 266 | else if (d->dir == DMA_DEV_TO_MEM) |
| 267 | pos = omap_get_dma_dst_pos(c->dma_ch); |
| 268 | else |
| 269 | pos = 0; |
| 270 | |
| 271 | txstate->residue = omap_dma_desc_size_pos(d, pos); |
| 272 | } else { |
| 273 | txstate->residue = 0; |
| 274 | } |
| 275 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 276 | |
| 277 | return ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | static void omap_dma_issue_pending(struct dma_chan *chan) |
| 281 | { |
| 282 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 283 | unsigned long flags; |
| 284 | |
| 285 | spin_lock_irqsave(&c->vc.lock, flags); |
| 286 | if (vchan_issue_pending(&c->vc) && !c->desc) { |
| 287 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); |
| 288 | spin_lock(&d->lock); |
| 289 | if (list_empty(&c->node)) |
| 290 | list_add_tail(&c->node, &d->pending); |
| 291 | spin_unlock(&d->lock); |
| 292 | tasklet_schedule(&d->task); |
| 293 | } |
| 294 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 295 | } |
| 296 | |
| 297 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( |
| 298 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, |
| 299 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) |
| 300 | { |
| 301 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 302 | enum dma_slave_buswidth dev_width; |
| 303 | struct scatterlist *sgent; |
| 304 | struct omap_desc *d; |
| 305 | dma_addr_t dev_addr; |
| 306 | unsigned i, j = 0, es, en, frame_bytes, sync_type; |
| 307 | u32 burst; |
| 308 | |
| 309 | if (dir == DMA_DEV_TO_MEM) { |
| 310 | dev_addr = c->cfg.src_addr; |
| 311 | dev_width = c->cfg.src_addr_width; |
| 312 | burst = c->cfg.src_maxburst; |
| 313 | sync_type = OMAP_DMA_SRC_SYNC; |
| 314 | } else if (dir == DMA_MEM_TO_DEV) { |
| 315 | dev_addr = c->cfg.dst_addr; |
| 316 | dev_width = c->cfg.dst_addr_width; |
| 317 | burst = c->cfg.dst_maxburst; |
| 318 | sync_type = OMAP_DMA_DST_SYNC; |
| 319 | } else { |
| 320 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 321 | return NULL; |
| 322 | } |
| 323 | |
| 324 | /* Bus width translates to the element size (ES) */ |
| 325 | switch (dev_width) { |
| 326 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
| 327 | es = OMAP_DMA_DATA_TYPE_S8; |
| 328 | break; |
| 329 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
| 330 | es = OMAP_DMA_DATA_TYPE_S16; |
| 331 | break; |
| 332 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
| 333 | es = OMAP_DMA_DATA_TYPE_S32; |
| 334 | break; |
| 335 | default: /* not reached */ |
| 336 | return NULL; |
| 337 | } |
| 338 | |
| 339 | /* Now allocate and setup the descriptor. */ |
| 340 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); |
| 341 | if (!d) |
| 342 | return NULL; |
| 343 | |
| 344 | d->dir = dir; |
| 345 | d->dev_addr = dev_addr; |
| 346 | d->es = es; |
| 347 | d->sync_mode = OMAP_DMA_SYNC_FRAME; |
| 348 | d->sync_type = sync_type; |
| 349 | d->periph_port = OMAP_DMA_PORT_TIPB; |
| 350 | |
| 351 | /* |
| 352 | * Build our scatterlist entries: each contains the address, |
| 353 | * the number of elements (EN) in each frame, and the number of |
| 354 | * frames (FN). Number of bytes for this entry = ES * EN * FN. |
| 355 | * |
| 356 | * Burst size translates to number of elements with frame sync. |
| 357 | * Note: DMA engine defines burst to be the number of dev-width |
| 358 | * transfers. |
| 359 | */ |
| 360 | en = burst; |
| 361 | frame_bytes = es_bytes[es] * en; |
| 362 | for_each_sg(sgl, sgent, sglen, i) { |
| 363 | d->sg[j].addr = sg_dma_address(sgent); |
| 364 | d->sg[j].en = en; |
| 365 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; |
| 366 | j++; |
| 367 | } |
| 368 | |
| 369 | d->sglen = j; |
| 370 | |
| 371 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); |
| 372 | } |
| 373 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 374 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
| 375 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
Peter Ujfalusi | ec8b5e4 | 2012-09-14 15:05:47 +0300 | [diff] [blame] | 376 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags, |
| 377 | void *context) |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 378 | { |
| 379 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 380 | enum dma_slave_buswidth dev_width; |
| 381 | struct omap_desc *d; |
| 382 | dma_addr_t dev_addr; |
| 383 | unsigned es, sync_type; |
| 384 | u32 burst; |
| 385 | |
| 386 | if (dir == DMA_DEV_TO_MEM) { |
| 387 | dev_addr = c->cfg.src_addr; |
| 388 | dev_width = c->cfg.src_addr_width; |
| 389 | burst = c->cfg.src_maxburst; |
| 390 | sync_type = OMAP_DMA_SRC_SYNC; |
| 391 | } else if (dir == DMA_MEM_TO_DEV) { |
| 392 | dev_addr = c->cfg.dst_addr; |
| 393 | dev_width = c->cfg.dst_addr_width; |
| 394 | burst = c->cfg.dst_maxburst; |
| 395 | sync_type = OMAP_DMA_DST_SYNC; |
| 396 | } else { |
| 397 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 398 | return NULL; |
| 399 | } |
| 400 | |
| 401 | /* Bus width translates to the element size (ES) */ |
| 402 | switch (dev_width) { |
| 403 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
| 404 | es = OMAP_DMA_DATA_TYPE_S8; |
| 405 | break; |
| 406 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
| 407 | es = OMAP_DMA_DATA_TYPE_S16; |
| 408 | break; |
| 409 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
| 410 | es = OMAP_DMA_DATA_TYPE_S32; |
| 411 | break; |
| 412 | default: /* not reached */ |
| 413 | return NULL; |
| 414 | } |
| 415 | |
| 416 | /* Now allocate and setup the descriptor. */ |
| 417 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); |
| 418 | if (!d) |
| 419 | return NULL; |
| 420 | |
| 421 | d->dir = dir; |
| 422 | d->dev_addr = dev_addr; |
| 423 | d->fi = burst; |
| 424 | d->es = es; |
Peter Ujfalusi | ccffa38 | 2012-09-14 15:05:44 +0300 | [diff] [blame] | 425 | if (burst) |
| 426 | d->sync_mode = OMAP_DMA_SYNC_PACKET; |
| 427 | else |
| 428 | d->sync_mode = OMAP_DMA_SYNC_ELEMENT; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 429 | d->sync_type = sync_type; |
| 430 | d->periph_port = OMAP_DMA_PORT_MPUI; |
| 431 | d->sg[0].addr = buf_addr; |
| 432 | d->sg[0].en = period_len / es_bytes[es]; |
| 433 | d->sg[0].fn = buf_len / period_len; |
| 434 | d->sglen = 1; |
| 435 | |
| 436 | if (!c->cyclic) { |
| 437 | c->cyclic = true; |
| 438 | omap_dma_link_lch(c->dma_ch, c->dma_ch); |
Peter Ujfalusi | 2dde5b9 | 2012-09-14 15:05:48 +0300 | [diff] [blame] | 439 | |
| 440 | if (flags & DMA_PREP_INTERRUPT) |
| 441 | omap_enable_dma_irq(c->dma_ch, OMAP_DMA_FRAME_IRQ); |
| 442 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 443 | omap_disable_dma_irq(c->dma_ch, OMAP_DMA_BLOCK_IRQ); |
| 444 | } |
| 445 | |
Tony Lindgren | 27615a9 | 2012-10-15 16:24:23 -0700 | [diff] [blame^] | 446 | if (dma_omap2plus()) { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 447 | omap_set_dma_src_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16); |
| 448 | omap_set_dma_dest_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16); |
| 449 | } |
| 450 | |
Peter Ujfalusi | 2dde5b9 | 2012-09-14 15:05:48 +0300 | [diff] [blame] | 451 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 452 | } |
| 453 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 454 | static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg) |
| 455 | { |
| 456 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
| 457 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) |
| 458 | return -EINVAL; |
| 459 | |
| 460 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | static int omap_dma_terminate_all(struct omap_chan *c) |
| 466 | { |
| 467 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); |
| 468 | unsigned long flags; |
| 469 | LIST_HEAD(head); |
| 470 | |
| 471 | spin_lock_irqsave(&c->vc.lock, flags); |
| 472 | |
| 473 | /* Prevent this channel being scheduled */ |
| 474 | spin_lock(&d->lock); |
| 475 | list_del_init(&c->node); |
| 476 | spin_unlock(&d->lock); |
| 477 | |
| 478 | /* |
| 479 | * Stop DMA activity: we assume the callback will not be called |
| 480 | * after omap_stop_dma() returns (even if it does, it will see |
| 481 | * c->desc is NULL and exit.) |
| 482 | */ |
| 483 | if (c->desc) { |
| 484 | c->desc = NULL; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 485 | /* Avoid stopping the dma twice */ |
| 486 | if (!c->paused) |
| 487 | omap_stop_dma(c->dma_ch); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 488 | } |
| 489 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 490 | if (c->cyclic) { |
| 491 | c->cyclic = false; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 492 | c->paused = false; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 493 | omap_dma_unlink_lch(c->dma_ch, c->dma_ch); |
| 494 | } |
| 495 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 496 | vchan_get_all_descriptors(&c->vc, &head); |
| 497 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 498 | vchan_dma_desc_free_list(&c->vc, &head); |
| 499 | |
| 500 | return 0; |
| 501 | } |
| 502 | |
| 503 | static int omap_dma_pause(struct omap_chan *c) |
| 504 | { |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 505 | /* Pause/Resume only allowed with cyclic mode */ |
| 506 | if (!c->cyclic) |
| 507 | return -EINVAL; |
| 508 | |
| 509 | if (!c->paused) { |
| 510 | omap_stop_dma(c->dma_ch); |
| 511 | c->paused = true; |
| 512 | } |
| 513 | |
| 514 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 515 | } |
| 516 | |
| 517 | static int omap_dma_resume(struct omap_chan *c) |
| 518 | { |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 519 | /* Pause/Resume only allowed with cyclic mode */ |
| 520 | if (!c->cyclic) |
| 521 | return -EINVAL; |
| 522 | |
| 523 | if (c->paused) { |
| 524 | omap_start_dma(c->dma_ch); |
| 525 | c->paused = false; |
| 526 | } |
| 527 | |
| 528 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 532 | unsigned long arg) |
| 533 | { |
| 534 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 535 | int ret; |
| 536 | |
| 537 | switch (cmd) { |
| 538 | case DMA_SLAVE_CONFIG: |
| 539 | ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg); |
| 540 | break; |
| 541 | |
| 542 | case DMA_TERMINATE_ALL: |
| 543 | ret = omap_dma_terminate_all(c); |
| 544 | break; |
| 545 | |
| 546 | case DMA_PAUSE: |
| 547 | ret = omap_dma_pause(c); |
| 548 | break; |
| 549 | |
| 550 | case DMA_RESUME: |
| 551 | ret = omap_dma_resume(c); |
| 552 | break; |
| 553 | |
| 554 | default: |
| 555 | ret = -ENXIO; |
| 556 | break; |
| 557 | } |
| 558 | |
| 559 | return ret; |
| 560 | } |
| 561 | |
| 562 | static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig) |
| 563 | { |
| 564 | struct omap_chan *c; |
| 565 | |
| 566 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
| 567 | if (!c) |
| 568 | return -ENOMEM; |
| 569 | |
| 570 | c->dma_sig = dma_sig; |
| 571 | c->vc.desc_free = omap_dma_desc_free; |
| 572 | vchan_init(&c->vc, &od->ddev); |
| 573 | INIT_LIST_HEAD(&c->node); |
| 574 | |
| 575 | od->ddev.chancnt++; |
| 576 | |
| 577 | return 0; |
| 578 | } |
| 579 | |
| 580 | static void omap_dma_free(struct omap_dmadev *od) |
| 581 | { |
| 582 | tasklet_kill(&od->task); |
| 583 | while (!list_empty(&od->ddev.channels)) { |
| 584 | struct omap_chan *c = list_first_entry(&od->ddev.channels, |
| 585 | struct omap_chan, vc.chan.device_node); |
| 586 | |
| 587 | list_del(&c->vc.chan.device_node); |
| 588 | tasklet_kill(&c->vc.task); |
| 589 | kfree(c); |
| 590 | } |
| 591 | kfree(od); |
| 592 | } |
| 593 | |
| 594 | static int omap_dma_probe(struct platform_device *pdev) |
| 595 | { |
| 596 | struct omap_dmadev *od; |
| 597 | int rc, i; |
| 598 | |
| 599 | od = kzalloc(sizeof(*od), GFP_KERNEL); |
| 600 | if (!od) |
| 601 | return -ENOMEM; |
| 602 | |
| 603 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 604 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 605 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
| 606 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; |
| 607 | od->ddev.device_tx_status = omap_dma_tx_status; |
| 608 | od->ddev.device_issue_pending = omap_dma_issue_pending; |
| 609 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 610 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 611 | od->ddev.device_control = omap_dma_control; |
| 612 | od->ddev.dev = &pdev->dev; |
| 613 | INIT_LIST_HEAD(&od->ddev.channels); |
| 614 | INIT_LIST_HEAD(&od->pending); |
| 615 | spin_lock_init(&od->lock); |
| 616 | |
| 617 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); |
| 618 | |
| 619 | for (i = 0; i < 127; i++) { |
| 620 | rc = omap_dma_chan_init(od, i); |
| 621 | if (rc) { |
| 622 | omap_dma_free(od); |
| 623 | return rc; |
| 624 | } |
| 625 | } |
| 626 | |
| 627 | rc = dma_async_device_register(&od->ddev); |
| 628 | if (rc) { |
| 629 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", |
| 630 | rc); |
| 631 | omap_dma_free(od); |
| 632 | } else { |
| 633 | platform_set_drvdata(pdev, od); |
| 634 | } |
| 635 | |
| 636 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); |
| 637 | |
| 638 | return rc; |
| 639 | } |
| 640 | |
| 641 | static int omap_dma_remove(struct platform_device *pdev) |
| 642 | { |
| 643 | struct omap_dmadev *od = platform_get_drvdata(pdev); |
| 644 | |
| 645 | dma_async_device_unregister(&od->ddev); |
| 646 | omap_dma_free(od); |
| 647 | |
| 648 | return 0; |
| 649 | } |
| 650 | |
| 651 | static struct platform_driver omap_dma_driver = { |
| 652 | .probe = omap_dma_probe, |
| 653 | .remove = omap_dma_remove, |
| 654 | .driver = { |
| 655 | .name = "omap-dma-engine", |
| 656 | .owner = THIS_MODULE, |
| 657 | }, |
| 658 | }; |
| 659 | |
| 660 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) |
| 661 | { |
| 662 | if (chan->device->dev->driver == &omap_dma_driver.driver) { |
| 663 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 664 | unsigned req = *(unsigned *)param; |
| 665 | |
| 666 | return req == c->dma_sig; |
| 667 | } |
| 668 | return false; |
| 669 | } |
| 670 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); |
| 671 | |
| 672 | static struct platform_device *pdev; |
| 673 | |
| 674 | static const struct platform_device_info omap_dma_dev_info = { |
| 675 | .name = "omap-dma-engine", |
| 676 | .id = -1, |
| 677 | .dma_mask = DMA_BIT_MASK(32), |
| 678 | }; |
| 679 | |
| 680 | static int omap_dma_init(void) |
| 681 | { |
| 682 | int rc = platform_driver_register(&omap_dma_driver); |
| 683 | |
| 684 | if (rc == 0) { |
| 685 | pdev = platform_device_register_full(&omap_dma_dev_info); |
| 686 | if (IS_ERR(pdev)) { |
| 687 | platform_driver_unregister(&omap_dma_driver); |
| 688 | rc = PTR_ERR(pdev); |
| 689 | } |
| 690 | } |
| 691 | return rc; |
| 692 | } |
| 693 | subsys_initcall(omap_dma_init); |
| 694 | |
| 695 | static void __exit omap_dma_exit(void) |
| 696 | { |
| 697 | platform_device_unregister(pdev); |
| 698 | platform_driver_unregister(&omap_dma_driver); |
| 699 | } |
| 700 | module_exit(omap_dma_exit); |
| 701 | |
| 702 | MODULE_AUTHOR("Russell King"); |
| 703 | MODULE_LICENSE("GPL"); |