| David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 1 | /* MN103E010 Processor initialisation |
| 2 | * |
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public Licence |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the Licence, or (at your option) any later version. |
| 10 | */ |
| 11 | #include <linux/kernel.h> |
| Akira Takeuchi | 278d91c | 2010-10-27 17:28:52 +0100 | [diff] [blame^] | 12 | #include <asm/fpu.h> |
| David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 13 | #include <asm/rtc.h> |
| 14 | |
| 15 | /* |
| 16 | * initialise the on-silicon processor peripherals |
| 17 | */ |
| 18 | asmlinkage void __init processor_init(void) |
| 19 | { |
| 20 | int loop; |
| 21 | |
| 22 | /* set up the exception table first */ |
| 23 | for (loop = 0x000; loop < 0x400; loop += 8) |
| 24 | __set_intr_stub(loop, __common_exception); |
| 25 | |
| 26 | __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); |
| 27 | __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); |
| 28 | __set_intr_stub(EXCEP_IAERROR, itlb_aerror); |
| 29 | __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); |
| 30 | __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); |
| 31 | __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); |
| Akira Takeuchi | 278d91c | 2010-10-27 17:28:52 +0100 | [diff] [blame^] | 32 | __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); |
| David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 33 | __set_intr_stub(EXCEP_SYSCALL0, system_call); |
| 34 | |
| 35 | __set_intr_stub(EXCEP_NMI, nmi_handler); |
| 36 | __set_intr_stub(EXCEP_WDT, nmi_handler); |
| 37 | __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); |
| 38 | __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); |
| 39 | __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); |
| 40 | __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); |
| 41 | __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); |
| 42 | __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); |
| 43 | __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); |
| 44 | |
| 45 | IVAR0 = EXCEP_IRQ_LEVEL0; |
| 46 | IVAR1 = EXCEP_IRQ_LEVEL1; |
| 47 | IVAR2 = EXCEP_IRQ_LEVEL2; |
| 48 | IVAR3 = EXCEP_IRQ_LEVEL3; |
| 49 | IVAR4 = EXCEP_IRQ_LEVEL4; |
| 50 | IVAR5 = EXCEP_IRQ_LEVEL5; |
| 51 | IVAR6 = EXCEP_IRQ_LEVEL6; |
| 52 | |
| 53 | mn10300_dcache_flush_inv(); |
| 54 | mn10300_icache_inv(); |
| 55 | |
| 56 | /* disable all interrupts and set to priority 6 (lowest) */ |
| 57 | for (loop = 0; loop < NR_IRQS; loop++) |
| 58 | GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; |
| 59 | |
| 60 | /* clear the timers */ |
| 61 | TM0MD = 0; |
| 62 | TM1MD = 0; |
| 63 | TM2MD = 0; |
| 64 | TM3MD = 0; |
| 65 | TM4MD = 0; |
| 66 | TM5MD = 0; |
| 67 | TM6MD = 0; |
| 68 | TM6MDA = 0; |
| 69 | TM6MDB = 0; |
| 70 | TM7MD = 0; |
| 71 | TM8MD = 0; |
| 72 | TM9MD = 0; |
| 73 | TM10MD = 0; |
| 74 | TM11MD = 0; |
| 75 | |
| 76 | calibrate_clock(); |
| 77 | } |