blob: fef7b722b05dfda1b33bb624d6d4b79291793d5d [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Jerome Glisse
23 */
24#include <drm/drmP.h>
25#include <drm/radeon_drm.h>
26#include "radeon_reg.h"
27#include "radeon.h"
28
Ilija Hadziccc340512011-10-12 23:29:38 -040029#define RADEON_BENCHMARK_COPY_BLIT 1
30#define RADEON_BENCHMARK_COPY_DMA 0
31
32#define RADEON_BENCHMARK_ITERATIONS 1024
Ilija Hadzic638dd7d2011-10-12 23:29:39 -040033#define RADEON_BENCHMARK_COMMON_MODES_N 17
Ilija Hadziccc340512011-10-12 23:29:38 -040034
35static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size,
36 uint64_t saddr, uint64_t daddr,
37 int flag, int n)
38{
39 unsigned long start_jiffies;
40 unsigned long end_jiffies;
41 struct radeon_fence *fence = NULL;
42 int i, r;
43
44 start_jiffies = jiffies;
45 for (i = 0; i < n; i++) {
Ilija Hadziccc340512011-10-12 23:29:38 -040046 switch (flag) {
47 case RADEON_BENCHMARK_COPY_DMA:
Alex Deucher27cd7762012-02-23 17:53:42 -050048 r = radeon_fence_create(rdev, &fence, radeon_copy_dma_ring_index(rdev));
49 if (r)
50 return r;
Ilija Hadziccc340512011-10-12 23:29:38 -040051 r = radeon_copy_dma(rdev, saddr, daddr,
52 size / RADEON_GPU_PAGE_SIZE,
53 fence);
54 break;
55 case RADEON_BENCHMARK_COPY_BLIT:
Alex Deucher27cd7762012-02-23 17:53:42 -050056 r = radeon_fence_create(rdev, &fence, radeon_copy_blit_ring_index(rdev));
57 if (r)
58 return r;
Ilija Hadziccc340512011-10-12 23:29:38 -040059 r = radeon_copy_blit(rdev, saddr, daddr,
60 size / RADEON_GPU_PAGE_SIZE,
61 fence);
62 break;
63 default:
64 DRM_ERROR("Unknown copy method\n");
65 r = -EINVAL;
66 }
67 if (r)
68 goto exit_do_move;
69 r = radeon_fence_wait(fence, false);
70 if (r)
71 goto exit_do_move;
72 radeon_fence_unref(&fence);
73 }
74 end_jiffies = jiffies;
75 r = jiffies_to_msecs(end_jiffies - start_jiffies);
76
77exit_do_move:
78 if (fence)
79 radeon_fence_unref(&fence);
80 return r;
81}
82
83
84static void radeon_benchmark_log_results(int n, unsigned size,
85 unsigned int time,
86 unsigned sdomain, unsigned ddomain,
87 char *kind)
88{
89 unsigned int throughput = (n * (size >> 10)) / time;
90 DRM_INFO("radeon: %s %u bo moves of %u kB from"
91 " %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
92 kind, n, size >> 10, sdomain, ddomain, time,
93 throughput * 8, throughput);
94}
95
96static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
97 unsigned sdomain, unsigned ddomain)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020098{
Jerome Glisse4c788672009-11-20 14:29:23 +010099 struct radeon_bo *dobj = NULL;
100 struct radeon_bo *sobj = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200101 uint64_t saddr, daddr;
Ilija Hadziccc340512011-10-12 23:29:38 -0400102 int r, n;
Dan Carpenterbfba1652011-10-29 10:21:28 +0300103 int time;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200104
Ilija Hadziccc340512011-10-12 23:29:38 -0400105 n = RADEON_BENCHMARK_ITERATIONS;
Daniel Vetter441921d2011-02-18 17:59:16 +0100106 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, &sobj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200107 if (r) {
108 goto out_cleanup;
109 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100110 r = radeon_bo_reserve(sobj, false);
111 if (unlikely(r != 0))
112 goto out_cleanup;
113 r = radeon_bo_pin(sobj, sdomain, &saddr);
114 radeon_bo_unreserve(sobj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200115 if (r) {
116 goto out_cleanup;
117 }
Daniel Vetter441921d2011-02-18 17:59:16 +0100118 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, &dobj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200119 if (r) {
120 goto out_cleanup;
121 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100122 r = radeon_bo_reserve(dobj, false);
123 if (unlikely(r != 0))
124 goto out_cleanup;
125 r = radeon_bo_pin(dobj, ddomain, &daddr);
126 radeon_bo_unreserve(dobj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200127 if (r) {
128 goto out_cleanup;
129 }
Pauli Nieminenc60a2842010-02-11 00:10:33 +0200130
131 /* r100 doesn't have dma engine so skip the test */
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400132 /* also, VRAM-to-VRAM test doesn't make much sense for DMA */
133 /* skip it as well if domains are the same */
Alex Deucher27cd7762012-02-23 17:53:42 -0500134 if ((rdev->asic->copy.dma) && (sdomain != ddomain)) {
Ilija Hadziccc340512011-10-12 23:29:38 -0400135 time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
136 RADEON_BENCHMARK_COPY_DMA, n);
137 if (time < 0)
138 goto out_cleanup;
139 if (time > 0)
140 radeon_benchmark_log_results(n, size, time,
141 sdomain, ddomain, "dma");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200142 }
Pauli Nieminenc60a2842010-02-11 00:10:33 +0200143
Ilija Hadziccc340512011-10-12 23:29:38 -0400144 time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
145 RADEON_BENCHMARK_COPY_BLIT, n);
146 if (time < 0)
147 goto out_cleanup;
148 if (time > 0)
149 radeon_benchmark_log_results(n, size, time,
150 sdomain, ddomain, "blit");
151
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200152out_cleanup:
153 if (sobj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100154 r = radeon_bo_reserve(sobj, false);
155 if (likely(r == 0)) {
156 radeon_bo_unpin(sobj);
157 radeon_bo_unreserve(sobj);
158 }
159 radeon_bo_unref(&sobj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200160 }
161 if (dobj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100162 r = radeon_bo_reserve(dobj, false);
163 if (likely(r == 0)) {
164 radeon_bo_unpin(dobj);
165 radeon_bo_unreserve(dobj);
166 }
167 radeon_bo_unref(&dobj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200168 }
Ilija Hadziccc340512011-10-12 23:29:38 -0400169
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170 if (r) {
Ilija Hadziccc340512011-10-12 23:29:38 -0400171 DRM_ERROR("Error while benchmarking BO move.\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200172 }
173}
174
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400175void radeon_benchmark(struct radeon_device *rdev, int test_number)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200176{
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400177 int i;
178 int common_modes[RADEON_BENCHMARK_COMMON_MODES_N] = {
179 640 * 480 * 4,
180 720 * 480 * 4,
181 800 * 600 * 4,
182 848 * 480 * 4,
183 1024 * 768 * 4,
184 1152 * 768 * 4,
185 1280 * 720 * 4,
186 1280 * 800 * 4,
187 1280 * 854 * 4,
188 1280 * 960 * 4,
189 1280 * 1024 * 4,
190 1440 * 900 * 4,
191 1400 * 1050 * 4,
192 1680 * 1050 * 4,
193 1600 * 1200 * 4,
194 1920 * 1080 * 4,
195 1920 * 1200 * 4
196 };
197
198 switch (test_number) {
199 case 1:
200 /* simple test, VRAM to GTT and GTT to VRAM */
201 radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_GTT,
202 RADEON_GEM_DOMAIN_VRAM);
203 radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
204 RADEON_GEM_DOMAIN_GTT);
205 break;
206 case 2:
207 /* simple test, VRAM to VRAM */
208 radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
209 RADEON_GEM_DOMAIN_VRAM);
210 break;
211 case 3:
212 /* GTT to VRAM, buffer size sweep, powers of 2 */
Ilija Hadzic6d75e832012-01-31 09:35:25 -0500213 for (i = 1; i <= 16384; i <<= 1)
214 radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400215 RADEON_GEM_DOMAIN_GTT,
216 RADEON_GEM_DOMAIN_VRAM);
217 break;
218 case 4:
219 /* VRAM to GTT, buffer size sweep, powers of 2 */
Ilija Hadzic6d75e832012-01-31 09:35:25 -0500220 for (i = 1; i <= 16384; i <<= 1)
221 radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400222 RADEON_GEM_DOMAIN_VRAM,
223 RADEON_GEM_DOMAIN_GTT);
224 break;
225 case 5:
226 /* VRAM to VRAM, buffer size sweep, powers of 2 */
Ilija Hadzic6d75e832012-01-31 09:35:25 -0500227 for (i = 1; i <= 16384; i <<= 1)
228 radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400229 RADEON_GEM_DOMAIN_VRAM,
230 RADEON_GEM_DOMAIN_VRAM);
231 break;
232 case 6:
233 /* GTT to VRAM, buffer size sweep, common modes */
Chen Jied7d0a752011-12-07 10:18:18 +0800234 for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400235 radeon_benchmark_move(rdev, common_modes[i],
236 RADEON_GEM_DOMAIN_GTT,
237 RADEON_GEM_DOMAIN_VRAM);
238 break;
239 case 7:
240 /* VRAM to GTT, buffer size sweep, common modes */
Chen Jied7d0a752011-12-07 10:18:18 +0800241 for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400242 radeon_benchmark_move(rdev, common_modes[i],
243 RADEON_GEM_DOMAIN_VRAM,
244 RADEON_GEM_DOMAIN_GTT);
245 break;
246 case 8:
247 /* VRAM to VRAM, buffer size sweep, common modes */
Chen Jied7d0a752011-12-07 10:18:18 +0800248 for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400249 radeon_benchmark_move(rdev, common_modes[i],
250 RADEON_GEM_DOMAIN_VRAM,
251 RADEON_GEM_DOMAIN_VRAM);
252 break;
253
254 default:
255 DRM_ERROR("Unknown benchmark\n");
256 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200257}