Dan Williams | 285f5fa | 2006-12-07 02:59:39 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * linux/include/asm-arm/arch-iop13xx/system.h |
| 3 | * |
| 4 | * Copyright (C) 2004 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #include <asm/arch/iop13xx.h> |
| 11 | static inline void arch_idle(void) |
| 12 | { |
| 13 | cpu_do_idle(); |
| 14 | } |
| 15 | |
| 16 | /* WDTCR CP6 R7 Page 9 */ |
| 17 | static inline u32 read_wdtcr(void) |
| 18 | { |
| 19 | u32 val; |
| 20 | asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); |
| 21 | return val; |
| 22 | } |
| 23 | static inline void write_wdtcr(u32 val) |
| 24 | { |
| 25 | asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); |
| 26 | } |
| 27 | |
| 28 | /* WDTSR CP6 R8 Page 9 */ |
| 29 | static inline u32 read_wdtsr(void) |
| 30 | { |
| 31 | u32 val; |
| 32 | asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); |
| 33 | return val; |
| 34 | } |
| 35 | static inline void write_wdtsr(u32 val) |
| 36 | { |
| 37 | asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); |
| 38 | } |
| 39 | |
| 40 | #define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e |
| 41 | #define IOP13XX_WDTCR_EN 0xe1e1e1e1 |
| 42 | #define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f |
| 43 | #define IOP13XX_WDTCR_DIS 0xf1f1f1f1 |
| 44 | #define IOP13XX_WDTSR_WRITE_EN (1 << 31) |
| 45 | #define IOP13XX_WDTCR_IB_RESET (1 << 0) |
| 46 | static inline void arch_reset(char mode) |
| 47 | { |
| 48 | /* |
| 49 | * Reset the internal bus (warning both cores are reset) |
| 50 | */ |
| 51 | u32 cp_flags = iop13xx_cp6_save(); |
| 52 | write_wdtcr(IOP13XX_WDTCR_EN_ARM); |
| 53 | write_wdtcr(IOP13XX_WDTCR_EN); |
| 54 | write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); |
| 55 | write_wdtcr(0x1000); |
| 56 | iop13xx_cp6_restore(cp_flags); |
| 57 | |
| 58 | for(;;); |
| 59 | } |