Blame - drivers/net/ethernet/stmicro/stmmac/Kconfig - kernel/msm-4.9

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Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	1	config STMMAC_ETH
				2	tristate "STMicroelectronics 10/100/1000 Ethernet driver"
Jeff Kirsher	7ac6653	2011-05-16 00:05:19 -0700	[diff] [blame]	3	depends on HAS_IOMEM
Jeff Kirsher	aaba215	2011-09-14 21:23:14 +0000	[diff] [blame]	4	select NET_CORE
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	5	select MII
				6	select PHYLIB
Carmelo AMOROSO	7ba8a9b	2010-03-31 21:44:03 +0000	[diff] [blame]	7	select CRC32
Jeff Kirsher	7ac6653	2011-05-16 00:05:19 -0700	[diff] [blame]	8	---help---
Giuseppe CAVALLARO	7187c1a	2010-01-06 23:07:22 +0000	[diff] [blame]	9	This is the driver for the Ethernet IPs are built around a
Giuseppe CAVALLARO	ac75791	2010-08-23 20:40:41 +0000	[diff] [blame]	10	Synopsys IP Core and only tested on the STMicroelectronics
Giuseppe CAVALLARO	7187c1a	2010-01-06 23:07:22 +0000	[diff] [blame]	11	platforms.
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	12
				13	if STMMAC_ETH
				14
Giuseppe CAVALLARO	7ac2905	2011-09-01 21:51:39 +0000	[diff] [blame]	15	config STMMAC_DEBUG_FS
				16	bool "Enable monitoring via sysFS "
				17	default n
				18	depends on STMMAC_ETH && DEBUG_FS
				19	-- help
Giuseppe CAVALLARO	e743482	2011-09-01 21:51:41 +0000	[diff] [blame]	20	The stmmac entry in /sys reports DMA TX/RX rings
				21	or (if supported) the HW cap register.
Giuseppe CAVALLARO	7ac2905	2011-09-01 21:51:39 +0000	[diff] [blame]	22
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	23	config STMMAC_DA
				24	bool "STMMAC DMA arbitration scheme"
				25	default n
Jeff Kirsher	7ac6653	2011-05-16 00:05:19 -0700	[diff] [blame]	26	---help---
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	27	Selecting this option, rx has priority over Tx (only for Giga
				28	Ethernet device).
				29	By default, the DMA arbitration scheme is based on Round-robin
				30	(rx:tx priority is 1:1).
				31
				32	config STMMAC_DUAL_MAC
				33	bool "STMMAC: dual mac support (EXPERIMENTAL)"
				34	default n
				35	depends on EXPERIMENTAL && STMMAC_ETH && !STMMAC_TIMER
Jeff Kirsher	7ac6653	2011-05-16 00:05:19 -0700	[diff] [blame]	36	---help---
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	37	Some ST SoCs (for example the stx7141 and stx7200c2) have two
				38	Ethernet Controllers. This option turns on the second Ethernet
				39	device on this kind of platforms.
				40
				41	config STMMAC_TIMER
				42	bool "STMMAC Timer optimisation"
				43	default n
David S. Miller	250ad8f	2010-08-26 20:32:02 -0700	[diff] [blame]	44	depends on RTC_HCTOSYS_DEVICE
Jeff Kirsher	7ac6653	2011-05-16 00:05:19 -0700	[diff] [blame]	45	---help---
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	46	Use an external timer for mitigating the number of network
Giuseppe CAVALLARO	7187c1a	2010-01-06 23:07:22 +0000	[diff] [blame]	47	interrupts. Currently, for SH architectures, it is possible
				48	to use the TMU channel 2 and the SH-RTC device.
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	49
				50	choice
				51	prompt "Select Timer device"
				52	depends on STMMAC_TIMER
				53
				54	config STMMAC_TMU_TIMER
				55	bool "TMU channel 2"
				56	depends on CPU_SH4
Jeff Kirsher	7ac6653	2011-05-16 00:05:19 -0700	[diff] [blame]	57	---help---
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	58
				59	config STMMAC_RTC_TIMER
				60	bool "Real time clock"
				61	depends on RTC_CLASS
Jeff Kirsher	7ac6653	2011-05-16 00:05:19 -0700	[diff] [blame]	62	---help---
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	63
				64	endchoice
				65
Giuseppe CAVALLARO	286a837	2011-10-18 00:01:24 +0000	[diff] [blame^]	66	choice
				67	prompt "Select the DMA TX/RX descriptor operating modes"
				68	depends on STMMAC_ETH
				69	---help---
				70	This driver supports DMA descriptor to operate both in dual buffer
				71	(RING) and linked-list(CHAINED) mode. In RING mode each descriptor
				72	points to two data buffer pointers whereas in CHAINED mode they
				73	points to only one data buffer pointer.
				74
				75	config STMMAC_RING
				76	bool "Enable Descriptor Ring Mode"
				77
				78	config STMMAC_CHAINED
				79	bool "Enable Descriptor Chained Mode"
				80
				81	endchoice
				82
				83
Giuseppe Cavallaro	47dd7a5	2009-10-14 15:13:45 -0700	[diff] [blame]	84	endif