Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1 | /* |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 2 | * Copyright (C) Ericsson AB 2007-2008 |
| 3 | * Copyright (C) ST-Ericsson SA 2008-2010 |
Per Forlin | 661385f | 2010-10-06 09:05:28 +0000 | [diff] [blame] | 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 6 | * License terms: GNU General Public License (GPL) version 2 |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
Alexey Dobriyan | b7f080c | 2011-06-16 11:01:34 +0000 | [diff] [blame] | 9 | #include <linux/dma-mapping.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 10 | #include <linux/kernel.h> |
| 11 | #include <linux/slab.h> |
Paul Gortmaker | f492b21 | 2011-07-31 16:17:36 -0400 | [diff] [blame] | 12 | #include <linux/export.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 13 | #include <linux/dmaengine.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/delay.h> |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 17 | #include <linux/pm.h> |
| 18 | #include <linux/pm_runtime.h> |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 19 | #include <linux/err.h> |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 20 | #include <linux/amba/bus.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 21 | |
| 22 | #include <plat/ste_dma40.h> |
| 23 | |
| 24 | #include "ste_dma40_ll.h" |
| 25 | |
| 26 | #define D40_NAME "dma40" |
| 27 | |
| 28 | #define D40_PHY_CHAN -1 |
| 29 | |
| 30 | /* For masking out/in 2 bit channel positions */ |
| 31 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) |
| 32 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) |
| 33 | |
| 34 | /* Maximum iterations taken before giving up suspending a channel */ |
| 35 | #define D40_SUSPEND_MAX_IT 500 |
| 36 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 37 | /* Milliseconds */ |
| 38 | #define DMA40_AUTOSUSPEND_DELAY 100 |
| 39 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 40 | /* Hardware requirement on LCLA alignment */ |
| 41 | #define LCLA_ALIGNMENT 0x40000 |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 42 | |
| 43 | /* Max number of links per event group */ |
| 44 | #define D40_LCLA_LINK_PER_EVENT_GRP 128 |
| 45 | #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP |
| 46 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 47 | /* Attempts before giving up to trying to get pages that are aligned */ |
| 48 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 |
| 49 | |
| 50 | /* Bit markings for allocation map */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 51 | #define D40_ALLOC_FREE (1 << 31) |
| 52 | #define D40_ALLOC_PHY (1 << 30) |
| 53 | #define D40_ALLOC_LOG_FREE 0 |
| 54 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 55 | /** |
| 56 | * enum 40_command - The different commands and/or statuses. |
| 57 | * |
| 58 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, |
| 59 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. |
| 60 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. |
| 61 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. |
| 62 | */ |
| 63 | enum d40_command { |
| 64 | D40_DMA_STOP = 0, |
| 65 | D40_DMA_RUN = 1, |
| 66 | D40_DMA_SUSPEND_REQ = 2, |
| 67 | D40_DMA_SUSPENDED = 3 |
| 68 | }; |
| 69 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 70 | /* |
| 71 | * These are the registers that has to be saved and later restored |
| 72 | * when the DMA hw is powered off. |
| 73 | * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. |
| 74 | */ |
| 75 | static u32 d40_backup_regs[] = { |
| 76 | D40_DREG_LCPA, |
| 77 | D40_DREG_LCLA, |
| 78 | D40_DREG_PRMSE, |
| 79 | D40_DREG_PRMSO, |
| 80 | D40_DREG_PRMOE, |
| 81 | D40_DREG_PRMOO, |
| 82 | }; |
| 83 | |
| 84 | #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs) |
| 85 | |
| 86 | /* TODO: Check if all these registers have to be saved/restored on dma40 v3 */ |
| 87 | static u32 d40_backup_regs_v3[] = { |
| 88 | D40_DREG_PSEG1, |
| 89 | D40_DREG_PSEG2, |
| 90 | D40_DREG_PSEG3, |
| 91 | D40_DREG_PSEG4, |
| 92 | D40_DREG_PCEG1, |
| 93 | D40_DREG_PCEG2, |
| 94 | D40_DREG_PCEG3, |
| 95 | D40_DREG_PCEG4, |
| 96 | D40_DREG_RSEG1, |
| 97 | D40_DREG_RSEG2, |
| 98 | D40_DREG_RSEG3, |
| 99 | D40_DREG_RSEG4, |
| 100 | D40_DREG_RCEG1, |
| 101 | D40_DREG_RCEG2, |
| 102 | D40_DREG_RCEG3, |
| 103 | D40_DREG_RCEG4, |
| 104 | }; |
| 105 | |
| 106 | #define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3) |
| 107 | |
| 108 | static u32 d40_backup_regs_chan[] = { |
| 109 | D40_CHAN_REG_SSCFG, |
| 110 | D40_CHAN_REG_SSELT, |
| 111 | D40_CHAN_REG_SSPTR, |
| 112 | D40_CHAN_REG_SSLNK, |
| 113 | D40_CHAN_REG_SDCFG, |
| 114 | D40_CHAN_REG_SDELT, |
| 115 | D40_CHAN_REG_SDPTR, |
| 116 | D40_CHAN_REG_SDLNK, |
| 117 | }; |
| 118 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 119 | /** |
| 120 | * struct d40_lli_pool - Structure for keeping LLIs in memory |
| 121 | * |
| 122 | * @base: Pointer to memory area when the pre_alloc_lli's are not large |
| 123 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if |
| 124 | * pre_alloc_lli is used. |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 125 | * @dma_addr: DMA address, if mapped |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 126 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. |
| 127 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, |
| 128 | * one buffer to one buffer. |
| 129 | */ |
| 130 | struct d40_lli_pool { |
| 131 | void *base; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 132 | int size; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 133 | dma_addr_t dma_addr; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 134 | /* Space for dst and src, plus an extra for padding */ |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 135 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | /** |
| 139 | * struct d40_desc - A descriptor is one DMA job. |
| 140 | * |
| 141 | * @lli_phy: LLI settings for physical channel. Both src and dst= |
| 142 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if |
| 143 | * lli_len equals one. |
| 144 | * @lli_log: Same as above but for logical channels. |
| 145 | * @lli_pool: The pool with two entries pre-allocated. |
Per Friden | 941b77a | 2010-06-20 21:24:45 +0000 | [diff] [blame] | 146 | * @lli_len: Number of llis of current descriptor. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 147 | * @lli_current: Number of transferred llis. |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 148 | * @lcla_alloc: Number of LCLA entries allocated. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 149 | * @txd: DMA engine struct. Used for among other things for communication |
| 150 | * during a transfer. |
| 151 | * @node: List entry. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 152 | * @is_in_client_list: true if the client owns this descriptor. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 153 | * @cyclic: true if this is a cyclic job |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 154 | * |
| 155 | * This descriptor is used for both logical and physical transfers. |
| 156 | */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 157 | struct d40_desc { |
| 158 | /* LLI physical */ |
| 159 | struct d40_phy_lli_bidir lli_phy; |
| 160 | /* LLI logical */ |
| 161 | struct d40_log_lli_bidir lli_log; |
| 162 | |
| 163 | struct d40_lli_pool lli_pool; |
Per Friden | 941b77a | 2010-06-20 21:24:45 +0000 | [diff] [blame] | 164 | int lli_len; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 165 | int lli_current; |
| 166 | int lcla_alloc; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 167 | |
| 168 | struct dma_async_tx_descriptor txd; |
| 169 | struct list_head node; |
| 170 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 171 | bool is_in_client_list; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 172 | bool cyclic; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 173 | }; |
| 174 | |
| 175 | /** |
| 176 | * struct d40_lcla_pool - LCLA pool settings and data. |
| 177 | * |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 178 | * @base: The virtual address of LCLA. 18 bit aligned. |
| 179 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. |
| 180 | * This pointer is only there for clean-up on error. |
| 181 | * @pages: The number of pages needed for all physical channels. |
| 182 | * Only used later for clean-up on error |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 183 | * @lock: Lock to protect the content in this struct. |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 184 | * @alloc_map: big map over which LCLA entry is own by which job. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 185 | */ |
| 186 | struct d40_lcla_pool { |
| 187 | void *base; |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 188 | dma_addr_t dma_addr; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 189 | void *base_unaligned; |
| 190 | int pages; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 191 | spinlock_t lock; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 192 | struct d40_desc **alloc_map; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 193 | }; |
| 194 | |
| 195 | /** |
| 196 | * struct d40_phy_res - struct for handling eventlines mapped to physical |
| 197 | * channels. |
| 198 | * |
| 199 | * @lock: A lock protection this entity. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 200 | * @reserved: True if used by secure world or otherwise. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 201 | * @num: The physical channel number of this entity. |
| 202 | * @allocated_src: Bit mapped to show which src event line's are mapped to |
| 203 | * this physical channel. Can also be free or physically allocated. |
| 204 | * @allocated_dst: Same as for src but is dst. |
| 205 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 206 | * event line number. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 207 | */ |
| 208 | struct d40_phy_res { |
| 209 | spinlock_t lock; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 210 | bool reserved; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 211 | int num; |
| 212 | u32 allocated_src; |
| 213 | u32 allocated_dst; |
| 214 | }; |
| 215 | |
| 216 | struct d40_base; |
| 217 | |
| 218 | /** |
| 219 | * struct d40_chan - Struct that describes a channel. |
| 220 | * |
| 221 | * @lock: A spinlock to protect this struct. |
| 222 | * @log_num: The logical number, if any of this channel. |
| 223 | * @completed: Starts with 1, after first interrupt it is set to dma engine's |
| 224 | * current cookie. |
| 225 | * @pending_tx: The number of pending transfers. Used between interrupt handler |
| 226 | * and tasklet. |
| 227 | * @busy: Set to true when transfer is ongoing on this channel. |
Jonas Aaberg | 2a61434 | 2010-06-20 21:25:24 +0000 | [diff] [blame] | 228 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
| 229 | * point is NULL, then the channel is not allocated. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 230 | * @chan: DMA engine handle. |
| 231 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a |
| 232 | * transfer and call client callback. |
| 233 | * @client: Cliented owned descriptor list. |
Per Forlin | da063d2 | 2011-08-29 13:33:32 +0200 | [diff] [blame] | 234 | * @pending_queue: Submitted jobs, to be issued by issue_pending() |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 235 | * @active: Active descriptor. |
| 236 | * @queue: Queued jobs. |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 237 | * @prepare_queue: Prepared jobs. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 238 | * @dma_cfg: The client configuration of this dma channel. |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 239 | * @configured: whether the dma_cfg configuration is valid |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 240 | * @base: Pointer to the device instance struct. |
| 241 | * @src_def_cfg: Default cfg register setting for src. |
| 242 | * @dst_def_cfg: Default cfg register setting for dst. |
| 243 | * @log_def: Default logical channel settings. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 244 | * @lcpa: Pointer to dst and src lcpa settings. |
om prakash | ae752bf | 2011-06-27 11:33:31 +0200 | [diff] [blame] | 245 | * @runtime_addr: runtime configured address. |
| 246 | * @runtime_direction: runtime configured direction. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 247 | * |
| 248 | * This struct can either "be" a logical or a physical channel. |
| 249 | */ |
| 250 | struct d40_chan { |
| 251 | spinlock_t lock; |
| 252 | int log_num; |
| 253 | /* ID of the most recent completed transfer */ |
| 254 | int completed; |
| 255 | int pending_tx; |
| 256 | bool busy; |
| 257 | struct d40_phy_res *phy_chan; |
| 258 | struct dma_chan chan; |
| 259 | struct tasklet_struct tasklet; |
| 260 | struct list_head client; |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 261 | struct list_head pending_queue; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 262 | struct list_head active; |
| 263 | struct list_head queue; |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 264 | struct list_head prepare_queue; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 265 | struct stedma40_chan_cfg dma_cfg; |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 266 | bool configured; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 267 | struct d40_base *base; |
| 268 | /* Default register configurations */ |
| 269 | u32 src_def_cfg; |
| 270 | u32 dst_def_cfg; |
| 271 | struct d40_def_lcsp log_def; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 272 | struct d40_log_lli_full *lcpa; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 273 | /* Runtime reconfiguration */ |
| 274 | dma_addr_t runtime_addr; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 275 | enum dma_transfer_direction runtime_direction; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | /** |
| 279 | * struct d40_base - The big global struct, one for each probe'd instance. |
| 280 | * |
| 281 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. |
| 282 | * @execmd_lock: Lock for execute command usage since several channels share |
| 283 | * the same physical register. |
| 284 | * @dev: The device structure. |
| 285 | * @virtbase: The virtual base address of the DMA's register. |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 286 | * @rev: silicon revision detected. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 287 | * @clk: Pointer to the DMA clock structure. |
| 288 | * @phy_start: Physical memory start of the DMA registers. |
| 289 | * @phy_size: Size of the DMA register map. |
| 290 | * @irq: The IRQ number. |
| 291 | * @num_phy_chans: The number of physical channels. Read from HW. This |
| 292 | * is the number of available channels for this driver, not counting "Secure |
| 293 | * mode" allocated physical channels. |
| 294 | * @num_log_chans: The number of logical channels. Calculated from |
| 295 | * num_phy_chans. |
| 296 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. |
| 297 | * @dma_slave: dma_device channels that can do only do slave transfers. |
| 298 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 299 | * @phy_chans: Room for all possible physical channels in system. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 300 | * @log_chans: Room for all possible logical channels in system. |
| 301 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points |
| 302 | * to log_chans entries. |
| 303 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points |
| 304 | * to phy_chans entries. |
| 305 | * @plat_data: Pointer to provided platform_data which is the driver |
| 306 | * configuration. |
| 307 | * @phy_res: Vector containing all physical channels. |
| 308 | * @lcla_pool: lcla pool settings and data. |
| 309 | * @lcpa_base: The virtual mapped address of LCPA. |
| 310 | * @phy_lcpa: The physical address of the LCPA. |
| 311 | * @lcpa_size: The size of the LCPA area. |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 312 | * @desc_slab: cache for descriptors. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 313 | * @reg_val_backup: Here the values of some hardware registers are stored |
| 314 | * before the DMA is powered off. They are restored when the power is back on. |
| 315 | * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and |
| 316 | * later. |
| 317 | * @reg_val_backup_chan: Backup data for standard channel parameter registers. |
| 318 | * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off. |
| 319 | * @initialized: true if the dma has been initialized |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 320 | */ |
| 321 | struct d40_base { |
| 322 | spinlock_t interrupt_lock; |
| 323 | spinlock_t execmd_lock; |
| 324 | struct device *dev; |
| 325 | void __iomem *virtbase; |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 326 | u8 rev:4; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 327 | struct clk *clk; |
| 328 | phys_addr_t phy_start; |
| 329 | resource_size_t phy_size; |
| 330 | int irq; |
| 331 | int num_phy_chans; |
| 332 | int num_log_chans; |
| 333 | struct dma_device dma_both; |
| 334 | struct dma_device dma_slave; |
| 335 | struct dma_device dma_memcpy; |
| 336 | struct d40_chan *phy_chans; |
| 337 | struct d40_chan *log_chans; |
| 338 | struct d40_chan **lookup_log_chans; |
| 339 | struct d40_chan **lookup_phy_chans; |
| 340 | struct stedma40_platform_data *plat_data; |
| 341 | /* Physical half channels */ |
| 342 | struct d40_phy_res *phy_res; |
| 343 | struct d40_lcla_pool lcla_pool; |
| 344 | void *lcpa_base; |
| 345 | dma_addr_t phy_lcpa; |
| 346 | resource_size_t lcpa_size; |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 347 | struct kmem_cache *desc_slab; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 348 | u32 reg_val_backup[BACKUP_REGS_SZ]; |
| 349 | u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3]; |
| 350 | u32 *reg_val_backup_chan; |
| 351 | u16 gcc_pwr_off_mask; |
| 352 | bool initialized; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | /** |
| 356 | * struct d40_interrupt_lookup - lookup table for interrupt handler |
| 357 | * |
| 358 | * @src: Interrupt mask register. |
| 359 | * @clr: Interrupt clear register. |
| 360 | * @is_error: true if this is an error interrupt. |
| 361 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to |
| 362 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. |
| 363 | */ |
| 364 | struct d40_interrupt_lookup { |
| 365 | u32 src; |
| 366 | u32 clr; |
| 367 | bool is_error; |
| 368 | int offset; |
| 369 | }; |
| 370 | |
| 371 | /** |
| 372 | * struct d40_reg_val - simple lookup struct |
| 373 | * |
| 374 | * @reg: The register. |
| 375 | * @val: The value that belongs to the register in reg. |
| 376 | */ |
| 377 | struct d40_reg_val { |
| 378 | unsigned int reg; |
| 379 | unsigned int val; |
| 380 | }; |
| 381 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 382 | static struct device *chan2dev(struct d40_chan *d40c) |
| 383 | { |
| 384 | return &d40c->chan.dev->device; |
| 385 | } |
| 386 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 387 | static bool chan_is_physical(struct d40_chan *chan) |
| 388 | { |
| 389 | return chan->log_num == D40_PHY_CHAN; |
| 390 | } |
| 391 | |
| 392 | static bool chan_is_logical(struct d40_chan *chan) |
| 393 | { |
| 394 | return !chan_is_physical(chan); |
| 395 | } |
| 396 | |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 397 | static void __iomem *chan_base(struct d40_chan *chan) |
| 398 | { |
| 399 | return chan->base->virtbase + D40_DREG_PCBASE + |
| 400 | chan->phy_chan->num * D40_DREG_PCDELTA; |
| 401 | } |
| 402 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 403 | #define d40_err(dev, format, arg...) \ |
| 404 | dev_err(dev, "[%s] " format, __func__, ## arg) |
| 405 | |
| 406 | #define chan_err(d40c, format, arg...) \ |
| 407 | d40_err(chan2dev(d40c), format, ## arg) |
| 408 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 409 | static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 410 | int lli_len) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 411 | { |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 412 | bool is_log = chan_is_logical(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 413 | u32 align; |
| 414 | void *base; |
| 415 | |
| 416 | if (is_log) |
| 417 | align = sizeof(struct d40_log_lli); |
| 418 | else |
| 419 | align = sizeof(struct d40_phy_lli); |
| 420 | |
| 421 | if (lli_len == 1) { |
| 422 | base = d40d->lli_pool.pre_alloc_lli; |
| 423 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); |
| 424 | d40d->lli_pool.base = NULL; |
| 425 | } else { |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 426 | d40d->lli_pool.size = lli_len * 2 * align; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 427 | |
| 428 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); |
| 429 | d40d->lli_pool.base = base; |
| 430 | |
| 431 | if (d40d->lli_pool.base == NULL) |
| 432 | return -ENOMEM; |
| 433 | } |
| 434 | |
| 435 | if (is_log) { |
Rabin Vincent | d924aba | 2011-01-25 11:18:16 +0100 | [diff] [blame] | 436 | d40d->lli_log.src = PTR_ALIGN(base, align); |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 437 | d40d->lli_log.dst = d40d->lli_log.src + lli_len; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 438 | |
| 439 | d40d->lli_pool.dma_addr = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 440 | } else { |
Rabin Vincent | d924aba | 2011-01-25 11:18:16 +0100 | [diff] [blame] | 441 | d40d->lli_phy.src = PTR_ALIGN(base, align); |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 442 | d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 443 | |
| 444 | d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, |
| 445 | d40d->lli_phy.src, |
| 446 | d40d->lli_pool.size, |
| 447 | DMA_TO_DEVICE); |
| 448 | |
| 449 | if (dma_mapping_error(d40c->base->dev, |
| 450 | d40d->lli_pool.dma_addr)) { |
| 451 | kfree(d40d->lli_pool.base); |
| 452 | d40d->lli_pool.base = NULL; |
| 453 | d40d->lli_pool.dma_addr = 0; |
| 454 | return -ENOMEM; |
| 455 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 456 | } |
| 457 | |
| 458 | return 0; |
| 459 | } |
| 460 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 461 | static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 462 | { |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 463 | if (d40d->lli_pool.dma_addr) |
| 464 | dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, |
| 465 | d40d->lli_pool.size, DMA_TO_DEVICE); |
| 466 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 467 | kfree(d40d->lli_pool.base); |
| 468 | d40d->lli_pool.base = NULL; |
| 469 | d40d->lli_pool.size = 0; |
| 470 | d40d->lli_log.src = NULL; |
| 471 | d40d->lli_log.dst = NULL; |
| 472 | d40d->lli_phy.src = NULL; |
| 473 | d40d->lli_phy.dst = NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 474 | } |
| 475 | |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 476 | static int d40_lcla_alloc_one(struct d40_chan *d40c, |
| 477 | struct d40_desc *d40d) |
| 478 | { |
| 479 | unsigned long flags; |
| 480 | int i; |
| 481 | int ret = -EINVAL; |
| 482 | int p; |
| 483 | |
| 484 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
| 485 | |
| 486 | p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP; |
| 487 | |
| 488 | /* |
| 489 | * Allocate both src and dst at the same time, therefore the half |
| 490 | * start on 1 since 0 can't be used since zero is used as end marker. |
| 491 | */ |
| 492 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { |
| 493 | if (!d40c->base->lcla_pool.alloc_map[p + i]) { |
| 494 | d40c->base->lcla_pool.alloc_map[p + i] = d40d; |
| 495 | d40d->lcla_alloc++; |
| 496 | ret = i; |
| 497 | break; |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
| 502 | |
| 503 | return ret; |
| 504 | } |
| 505 | |
| 506 | static int d40_lcla_free_all(struct d40_chan *d40c, |
| 507 | struct d40_desc *d40d) |
| 508 | { |
| 509 | unsigned long flags; |
| 510 | int i; |
| 511 | int ret = -EINVAL; |
| 512 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 513 | if (chan_is_physical(d40c)) |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 514 | return 0; |
| 515 | |
| 516 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
| 517 | |
| 518 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { |
| 519 | if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * |
| 520 | D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) { |
| 521 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * |
| 522 | D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL; |
| 523 | d40d->lcla_alloc--; |
| 524 | if (d40d->lcla_alloc == 0) { |
| 525 | ret = 0; |
| 526 | break; |
| 527 | } |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
| 532 | |
| 533 | return ret; |
| 534 | |
| 535 | } |
| 536 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 537 | static void d40_desc_remove(struct d40_desc *d40d) |
| 538 | { |
| 539 | list_del(&d40d->node); |
| 540 | } |
| 541 | |
| 542 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) |
| 543 | { |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 544 | struct d40_desc *desc = NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 545 | |
| 546 | if (!list_empty(&d40c->client)) { |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 547 | struct d40_desc *d; |
| 548 | struct d40_desc *_d; |
| 549 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 550 | list_for_each_entry_safe(d, _d, &d40c->client, node) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 551 | if (async_tx_test_ack(&d->txd)) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 552 | d40_desc_remove(d); |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 553 | desc = d; |
| 554 | memset(desc, 0, sizeof(*desc)); |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 555 | break; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 556 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 557 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 558 | } |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 559 | |
| 560 | if (!desc) |
| 561 | desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); |
| 562 | |
| 563 | if (desc) |
| 564 | INIT_LIST_HEAD(&desc->node); |
| 565 | |
| 566 | return desc; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) |
| 570 | { |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 571 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 572 | d40_pool_lli_free(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 573 | d40_lcla_free_all(d40c, d40d); |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 574 | kmem_cache_free(d40c->base->desc_slab, d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) |
| 578 | { |
| 579 | list_add_tail(&desc->node, &d40c->active); |
| 580 | } |
| 581 | |
Rabin Vincent | 1c4b092 | 2011-01-25 11:18:24 +0100 | [diff] [blame] | 582 | static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) |
| 583 | { |
| 584 | struct d40_phy_lli *lli_dst = desc->lli_phy.dst; |
| 585 | struct d40_phy_lli *lli_src = desc->lli_phy.src; |
| 586 | void __iomem *base = chan_base(chan); |
| 587 | |
| 588 | writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); |
| 589 | writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); |
| 590 | writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); |
| 591 | writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); |
| 592 | |
| 593 | writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); |
| 594 | writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); |
| 595 | writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); |
| 596 | writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); |
| 597 | } |
| 598 | |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 599 | static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) |
| 600 | { |
| 601 | struct d40_lcla_pool *pool = &chan->base->lcla_pool; |
| 602 | struct d40_log_lli_bidir *lli = &desc->lli_log; |
| 603 | int lli_current = desc->lli_current; |
| 604 | int lli_len = desc->lli_len; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 605 | bool cyclic = desc->cyclic; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 606 | int curr_lcla = -EINVAL; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 607 | int first_lcla = 0; |
| 608 | bool linkback; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 609 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 610 | /* |
| 611 | * We may have partially running cyclic transfers, in case we did't get |
| 612 | * enough LCLA entries. |
| 613 | */ |
| 614 | linkback = cyclic && lli_current == 0; |
| 615 | |
| 616 | /* |
| 617 | * For linkback, we need one LCLA even with only one link, because we |
| 618 | * can't link back to the one in LCPA space |
| 619 | */ |
| 620 | if (linkback || (lli_len - lli_current > 1)) { |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 621 | curr_lcla = d40_lcla_alloc_one(chan, desc); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 622 | first_lcla = curr_lcla; |
| 623 | } |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 624 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 625 | /* |
| 626 | * For linkback, we normally load the LCPA in the loop since we need to |
| 627 | * link it to the second LCLA and not the first. However, if we |
| 628 | * couldn't even get a first LCLA, then we have to run in LCPA and |
| 629 | * reload manually. |
| 630 | */ |
| 631 | if (!linkback || curr_lcla == -EINVAL) { |
| 632 | unsigned int flags = 0; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 633 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 634 | if (curr_lcla == -EINVAL) |
| 635 | flags |= LLI_TERM_INT; |
| 636 | |
| 637 | d40_log_lli_lcpa_write(chan->lcpa, |
| 638 | &lli->dst[lli_current], |
| 639 | &lli->src[lli_current], |
| 640 | curr_lcla, |
| 641 | flags); |
| 642 | lli_current++; |
| 643 | } |
Rabin Vincent | 6045f0b | 2011-01-25 11:18:32 +0100 | [diff] [blame] | 644 | |
| 645 | if (curr_lcla < 0) |
| 646 | goto out; |
| 647 | |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 648 | for (; lli_current < lli_len; lli_current++) { |
| 649 | unsigned int lcla_offset = chan->phy_chan->num * 1024 + |
| 650 | 8 * curr_lcla * 2; |
| 651 | struct d40_log_lli *lcla = pool->base + lcla_offset; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 652 | unsigned int flags = 0; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 653 | int next_lcla; |
| 654 | |
| 655 | if (lli_current + 1 < lli_len) |
| 656 | next_lcla = d40_lcla_alloc_one(chan, desc); |
| 657 | else |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 658 | next_lcla = linkback ? first_lcla : -EINVAL; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 659 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 660 | if (cyclic || next_lcla == -EINVAL) |
| 661 | flags |= LLI_TERM_INT; |
| 662 | |
| 663 | if (linkback && curr_lcla == first_lcla) { |
| 664 | /* First link goes in both LCPA and LCLA */ |
| 665 | d40_log_lli_lcpa_write(chan->lcpa, |
| 666 | &lli->dst[lli_current], |
| 667 | &lli->src[lli_current], |
| 668 | next_lcla, flags); |
| 669 | } |
| 670 | |
| 671 | /* |
| 672 | * One unused LCLA in the cyclic case if the very first |
| 673 | * next_lcla fails... |
| 674 | */ |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 675 | d40_log_lli_lcla_write(lcla, |
| 676 | &lli->dst[lli_current], |
| 677 | &lli->src[lli_current], |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 678 | next_lcla, flags); |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 679 | |
| 680 | dma_sync_single_range_for_device(chan->base->dev, |
| 681 | pool->dma_addr, lcla_offset, |
| 682 | 2 * sizeof(struct d40_log_lli), |
| 683 | DMA_TO_DEVICE); |
| 684 | |
| 685 | curr_lcla = next_lcla; |
| 686 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 687 | if (curr_lcla == -EINVAL || curr_lcla == first_lcla) { |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 688 | lli_current++; |
| 689 | break; |
| 690 | } |
| 691 | } |
| 692 | |
Rabin Vincent | 6045f0b | 2011-01-25 11:18:32 +0100 | [diff] [blame] | 693 | out: |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 694 | desc->lli_current = lli_current; |
| 695 | } |
| 696 | |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 697 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) |
| 698 | { |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 699 | if (chan_is_physical(d40c)) { |
Rabin Vincent | 1c4b092 | 2011-01-25 11:18:24 +0100 | [diff] [blame] | 700 | d40_phy_lli_load(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 701 | d40d->lli_current = d40d->lli_len; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 702 | } else |
| 703 | d40_log_lli_to_lcxa(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 704 | } |
| 705 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 706 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) |
| 707 | { |
| 708 | struct d40_desc *d; |
| 709 | |
| 710 | if (list_empty(&d40c->active)) |
| 711 | return NULL; |
| 712 | |
| 713 | d = list_first_entry(&d40c->active, |
| 714 | struct d40_desc, |
| 715 | node); |
| 716 | return d; |
| 717 | } |
| 718 | |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 719 | /* remove desc from current queue and add it to the pending_queue */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 720 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) |
| 721 | { |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 722 | d40_desc_remove(desc); |
| 723 | desc->is_in_client_list = false; |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 724 | list_add_tail(&desc->node, &d40c->pending_queue); |
| 725 | } |
| 726 | |
| 727 | static struct d40_desc *d40_first_pending(struct d40_chan *d40c) |
| 728 | { |
| 729 | struct d40_desc *d; |
| 730 | |
| 731 | if (list_empty(&d40c->pending_queue)) |
| 732 | return NULL; |
| 733 | |
| 734 | d = list_first_entry(&d40c->pending_queue, |
| 735 | struct d40_desc, |
| 736 | node); |
| 737 | return d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 738 | } |
| 739 | |
| 740 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) |
| 741 | { |
| 742 | struct d40_desc *d; |
| 743 | |
| 744 | if (list_empty(&d40c->queue)) |
| 745 | return NULL; |
| 746 | |
| 747 | d = list_first_entry(&d40c->queue, |
| 748 | struct d40_desc, |
| 749 | node); |
| 750 | return d; |
| 751 | } |
| 752 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 753 | static int d40_psize_2_burst_size(bool is_log, int psize) |
| 754 | { |
| 755 | if (is_log) { |
| 756 | if (psize == STEDMA40_PSIZE_LOG_1) |
| 757 | return 1; |
| 758 | } else { |
| 759 | if (psize == STEDMA40_PSIZE_PHY_1) |
| 760 | return 1; |
| 761 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 762 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 763 | return 2 << psize; |
| 764 | } |
| 765 | |
| 766 | /* |
| 767 | * The dma only supports transmitting packages up to |
| 768 | * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of |
| 769 | * dma elements required to send the entire sg list |
| 770 | */ |
| 771 | static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) |
| 772 | { |
| 773 | int dmalen; |
| 774 | u32 max_w = max(data_width1, data_width2); |
| 775 | u32 min_w = min(data_width1, data_width2); |
| 776 | u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); |
| 777 | |
| 778 | if (seg_max > STEDMA40_MAX_SEG_SIZE) |
| 779 | seg_max -= (1 << max_w); |
| 780 | |
| 781 | if (!IS_ALIGNED(size, 1 << max_w)) |
| 782 | return -EINVAL; |
| 783 | |
| 784 | if (size <= seg_max) |
| 785 | dmalen = 1; |
| 786 | else { |
| 787 | dmalen = size / seg_max; |
| 788 | if (dmalen * seg_max < size) |
| 789 | dmalen++; |
| 790 | } |
| 791 | return dmalen; |
| 792 | } |
| 793 | |
| 794 | static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, |
| 795 | u32 data_width1, u32 data_width2) |
| 796 | { |
| 797 | struct scatterlist *sg; |
| 798 | int i; |
| 799 | int len = 0; |
| 800 | int ret; |
| 801 | |
| 802 | for_each_sg(sgl, sg, sg_len, i) { |
| 803 | ret = d40_size_2_dmalen(sg_dma_len(sg), |
| 804 | data_width1, data_width2); |
| 805 | if (ret < 0) |
| 806 | return ret; |
| 807 | len += ret; |
| 808 | } |
| 809 | return len; |
| 810 | } |
| 811 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 812 | |
| 813 | #ifdef CONFIG_PM |
| 814 | static void dma40_backup(void __iomem *baseaddr, u32 *backup, |
| 815 | u32 *regaddr, int num, bool save) |
| 816 | { |
| 817 | int i; |
| 818 | |
| 819 | for (i = 0; i < num; i++) { |
| 820 | void __iomem *addr = baseaddr + regaddr[i]; |
| 821 | |
| 822 | if (save) |
| 823 | backup[i] = readl_relaxed(addr); |
| 824 | else |
| 825 | writel_relaxed(backup[i], addr); |
| 826 | } |
| 827 | } |
| 828 | |
| 829 | static void d40_save_restore_registers(struct d40_base *base, bool save) |
| 830 | { |
| 831 | int i; |
| 832 | |
| 833 | /* Save/Restore channel specific registers */ |
| 834 | for (i = 0; i < base->num_phy_chans; i++) { |
| 835 | void __iomem *addr; |
| 836 | int idx; |
| 837 | |
| 838 | if (base->phy_res[i].reserved) |
| 839 | continue; |
| 840 | |
| 841 | addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; |
| 842 | idx = i * ARRAY_SIZE(d40_backup_regs_chan); |
| 843 | |
| 844 | dma40_backup(addr, &base->reg_val_backup_chan[idx], |
| 845 | d40_backup_regs_chan, |
| 846 | ARRAY_SIZE(d40_backup_regs_chan), |
| 847 | save); |
| 848 | } |
| 849 | |
| 850 | /* Save/Restore global registers */ |
| 851 | dma40_backup(base->virtbase, base->reg_val_backup, |
| 852 | d40_backup_regs, ARRAY_SIZE(d40_backup_regs), |
| 853 | save); |
| 854 | |
| 855 | /* Save/Restore registers only existing on dma40 v3 and later */ |
| 856 | if (base->rev >= 3) |
| 857 | dma40_backup(base->virtbase, base->reg_val_backup_v3, |
| 858 | d40_backup_regs_v3, |
| 859 | ARRAY_SIZE(d40_backup_regs_v3), |
| 860 | save); |
| 861 | } |
| 862 | #else |
| 863 | static void d40_save_restore_registers(struct d40_base *base, bool save) |
| 864 | { |
| 865 | } |
| 866 | #endif |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 867 | |
| 868 | static int d40_channel_execute_command(struct d40_chan *d40c, |
| 869 | enum d40_command command) |
| 870 | { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 871 | u32 status; |
| 872 | int i; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 873 | void __iomem *active_reg; |
| 874 | int ret = 0; |
| 875 | unsigned long flags; |
Jonas Aaberg | 1d392a7 | 2010-06-20 21:26:01 +0000 | [diff] [blame] | 876 | u32 wmask; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 877 | |
| 878 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); |
| 879 | |
| 880 | if (d40c->phy_chan->num % 2 == 0) |
| 881 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 882 | else |
| 883 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 884 | |
| 885 | if (command == D40_DMA_SUSPEND_REQ) { |
| 886 | status = (readl(active_reg) & |
| 887 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 888 | D40_CHAN_POS(d40c->phy_chan->num); |
| 889 | |
| 890 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) |
| 891 | goto done; |
| 892 | } |
| 893 | |
Jonas Aaberg | 1d392a7 | 2010-06-20 21:26:01 +0000 | [diff] [blame] | 894 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
| 895 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), |
| 896 | active_reg); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 897 | |
| 898 | if (command == D40_DMA_SUSPEND_REQ) { |
| 899 | |
| 900 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { |
| 901 | status = (readl(active_reg) & |
| 902 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 903 | D40_CHAN_POS(d40c->phy_chan->num); |
| 904 | |
| 905 | cpu_relax(); |
| 906 | /* |
| 907 | * Reduce the number of bus accesses while |
| 908 | * waiting for the DMA to suspend. |
| 909 | */ |
| 910 | udelay(3); |
| 911 | |
| 912 | if (status == D40_DMA_STOP || |
| 913 | status == D40_DMA_SUSPENDED) |
| 914 | break; |
| 915 | } |
| 916 | |
| 917 | if (i == D40_SUSPEND_MAX_IT) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 918 | chan_err(d40c, |
| 919 | "unable to suspend the chl %d (log: %d) status %x\n", |
| 920 | d40c->phy_chan->num, d40c->log_num, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 921 | status); |
| 922 | dump_stack(); |
| 923 | ret = -EBUSY; |
| 924 | } |
| 925 | |
| 926 | } |
| 927 | done: |
| 928 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); |
| 929 | return ret; |
| 930 | } |
| 931 | |
| 932 | static void d40_term_all(struct d40_chan *d40c) |
| 933 | { |
| 934 | struct d40_desc *d40d; |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 935 | struct d40_desc *_d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 936 | |
| 937 | /* Release active descriptors */ |
| 938 | while ((d40d = d40_first_active_get(d40c))) { |
| 939 | d40_desc_remove(d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 940 | d40_desc_free(d40c, d40d); |
| 941 | } |
| 942 | |
| 943 | /* Release queued descriptors waiting for transfer */ |
| 944 | while ((d40d = d40_first_queued(d40c))) { |
| 945 | d40_desc_remove(d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 946 | d40_desc_free(d40c, d40d); |
| 947 | } |
| 948 | |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 949 | /* Release pending descriptors */ |
| 950 | while ((d40d = d40_first_pending(d40c))) { |
| 951 | d40_desc_remove(d40d); |
| 952 | d40_desc_free(d40c, d40d); |
| 953 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 954 | |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 955 | /* Release client owned descriptors */ |
| 956 | if (!list_empty(&d40c->client)) |
| 957 | list_for_each_entry_safe(d40d, _d, &d40c->client, node) { |
| 958 | d40_desc_remove(d40d); |
| 959 | d40_desc_free(d40c, d40d); |
| 960 | } |
| 961 | |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 962 | /* Release descriptors in prepare queue */ |
| 963 | if (!list_empty(&d40c->prepare_queue)) |
| 964 | list_for_each_entry_safe(d40d, _d, |
| 965 | &d40c->prepare_queue, node) { |
| 966 | d40_desc_remove(d40d); |
| 967 | d40_desc_free(d40c, d40d); |
| 968 | } |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 969 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 970 | d40c->pending_tx = 0; |
| 971 | d40c->busy = false; |
| 972 | } |
| 973 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 974 | static void __d40_config_set_event(struct d40_chan *d40c, bool enable, |
| 975 | u32 event, int reg) |
| 976 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 977 | void __iomem *addr = chan_base(d40c) + reg; |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 978 | int tries; |
| 979 | |
| 980 | if (!enable) { |
| 981 | writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) |
| 982 | | ~D40_EVENTLINE_MASK(event), addr); |
| 983 | return; |
| 984 | } |
| 985 | |
| 986 | /* |
| 987 | * The hardware sometimes doesn't register the enable when src and dst |
| 988 | * event lines are active on the same logical channel. Retry to ensure |
| 989 | * it does. Usually only one retry is sufficient. |
| 990 | */ |
| 991 | tries = 100; |
| 992 | while (--tries) { |
| 993 | writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) |
| 994 | | ~D40_EVENTLINE_MASK(event), addr); |
| 995 | |
| 996 | if (readl(addr) & D40_EVENTLINE_MASK(event)) |
| 997 | break; |
| 998 | } |
| 999 | |
| 1000 | if (tries != 99) |
| 1001 | dev_dbg(chan2dev(d40c), |
| 1002 | "[%s] workaround enable S%cLNK (%d tries)\n", |
| 1003 | __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', |
| 1004 | 100 - tries); |
| 1005 | |
| 1006 | WARN_ON(!tries); |
| 1007 | } |
| 1008 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1009 | static void d40_config_set_event(struct d40_chan *d40c, bool do_enable) |
| 1010 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1011 | unsigned long flags; |
| 1012 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1013 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); |
| 1014 | |
| 1015 | /* Enable event line connected to device (or memcpy) */ |
| 1016 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || |
| 1017 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { |
| 1018 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
| 1019 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1020 | __d40_config_set_event(d40c, do_enable, event, |
| 1021 | D40_CHAN_REG_SSLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1022 | } |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1023 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1024 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { |
| 1025 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
| 1026 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1027 | __d40_config_set_event(d40c, do_enable, event, |
| 1028 | D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1029 | } |
| 1030 | |
| 1031 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); |
| 1032 | } |
| 1033 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1034 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1035 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1036 | void __iomem *chanbase = chan_base(d40c); |
Jonas Aaberg | be8cb7d | 2010-08-09 12:07:44 +0000 | [diff] [blame] | 1037 | u32 val; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1038 | |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1039 | val = readl(chanbase + D40_CHAN_REG_SSLNK); |
| 1040 | val |= readl(chanbase + D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1041 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1042 | return val; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1043 | } |
| 1044 | |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1045 | static u32 d40_get_prmo(struct d40_chan *d40c) |
| 1046 | { |
| 1047 | static const unsigned int phy_map[] = { |
| 1048 | [STEDMA40_PCHAN_BASIC_MODE] |
| 1049 | = D40_DREG_PRMO_PCHAN_BASIC, |
| 1050 | [STEDMA40_PCHAN_MODULO_MODE] |
| 1051 | = D40_DREG_PRMO_PCHAN_MODULO, |
| 1052 | [STEDMA40_PCHAN_DOUBLE_DST_MODE] |
| 1053 | = D40_DREG_PRMO_PCHAN_DOUBLE_DST, |
| 1054 | }; |
| 1055 | static const unsigned int log_map[] = { |
| 1056 | [STEDMA40_LCHAN_SRC_PHY_DST_LOG] |
| 1057 | = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, |
| 1058 | [STEDMA40_LCHAN_SRC_LOG_DST_PHY] |
| 1059 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, |
| 1060 | [STEDMA40_LCHAN_SRC_LOG_DST_LOG] |
| 1061 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, |
| 1062 | }; |
| 1063 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1064 | if (chan_is_physical(d40c)) |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1065 | return phy_map[d40c->dma_cfg.mode_opt]; |
| 1066 | else |
| 1067 | return log_map[d40c->dma_cfg.mode_opt]; |
| 1068 | } |
| 1069 | |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 1070 | static void d40_config_write(struct d40_chan *d40c) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1071 | { |
| 1072 | u32 addr_base; |
| 1073 | u32 var; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1074 | |
| 1075 | /* Odd addresses are even addresses + 4 */ |
| 1076 | addr_base = (d40c->phy_chan->num % 2) * 4; |
| 1077 | /* Setup channel mode to logical or physical */ |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1078 | var = ((u32)(chan_is_logical(d40c)) + 1) << |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1079 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1080 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); |
| 1081 | |
| 1082 | /* Setup operational mode option register */ |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1083 | var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1084 | |
| 1085 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); |
| 1086 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1087 | if (chan_is_logical(d40c)) { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1088 | int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) |
| 1089 | & D40_SREG_ELEM_LOG_LIDX_MASK; |
| 1090 | void __iomem *chanbase = chan_base(d40c); |
| 1091 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1092 | /* Set default config for CFG reg */ |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1093 | writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); |
| 1094 | writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1095 | |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 1096 | /* Set LIDX for lcla */ |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1097 | writel(lidx, chanbase + D40_CHAN_REG_SSELT); |
| 1098 | writel(lidx, chanbase + D40_CHAN_REG_SDELT); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1099 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1100 | } |
| 1101 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1102 | static u32 d40_residue(struct d40_chan *d40c) |
| 1103 | { |
| 1104 | u32 num_elt; |
| 1105 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1106 | if (chan_is_logical(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1107 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) |
| 1108 | >> D40_MEM_LCSP2_ECNT_POS; |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1109 | else { |
| 1110 | u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); |
| 1111 | num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) |
| 1112 | >> D40_SREG_ELEM_PHY_ECNT_POS; |
| 1113 | } |
| 1114 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1115 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); |
| 1116 | } |
| 1117 | |
| 1118 | static bool d40_tx_is_linked(struct d40_chan *d40c) |
| 1119 | { |
| 1120 | bool is_link; |
| 1121 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1122 | if (chan_is_logical(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1123 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; |
| 1124 | else |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1125 | is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) |
| 1126 | & D40_SREG_LNK_PHYS_LNK_MASK; |
| 1127 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1128 | return is_link; |
| 1129 | } |
| 1130 | |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 1131 | static int d40_pause(struct d40_chan *d40c) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1132 | { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1133 | int res = 0; |
| 1134 | unsigned long flags; |
| 1135 | |
Jonas Aaberg | 3ac012a | 2010-08-09 12:09:12 +0000 | [diff] [blame] | 1136 | if (!d40c->busy) |
| 1137 | return 0; |
| 1138 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1139 | pm_runtime_get_sync(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1140 | spin_lock_irqsave(&d40c->lock, flags); |
| 1141 | |
| 1142 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
| 1143 | if (res == 0) { |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1144 | if (chan_is_logical(d40c)) { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1145 | d40_config_set_event(d40c, false); |
| 1146 | /* Resume the other logical channels if any */ |
| 1147 | if (d40_chan_has_events(d40c)) |
| 1148 | res = d40_channel_execute_command(d40c, |
| 1149 | D40_DMA_RUN); |
| 1150 | } |
| 1151 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1152 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1153 | pm_runtime_put_autosuspend(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1154 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1155 | return res; |
| 1156 | } |
| 1157 | |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 1158 | static int d40_resume(struct d40_chan *d40c) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1159 | { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1160 | int res = 0; |
| 1161 | unsigned long flags; |
| 1162 | |
Jonas Aaberg | 3ac012a | 2010-08-09 12:09:12 +0000 | [diff] [blame] | 1163 | if (!d40c->busy) |
| 1164 | return 0; |
| 1165 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1166 | spin_lock_irqsave(&d40c->lock, flags); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1167 | pm_runtime_get_sync(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1168 | if (d40c->base->rev == 0) |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1169 | if (chan_is_logical(d40c)) { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1170 | res = d40_channel_execute_command(d40c, |
| 1171 | D40_DMA_SUSPEND_REQ); |
| 1172 | goto no_suspend; |
| 1173 | } |
| 1174 | |
| 1175 | /* If bytes left to transfer or linked tx resume job */ |
| 1176 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) { |
| 1177 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1178 | if (chan_is_logical(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1179 | d40_config_set_event(d40c, true); |
| 1180 | |
| 1181 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); |
| 1182 | } |
| 1183 | |
| 1184 | no_suspend: |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1185 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1186 | pm_runtime_put_autosuspend(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1187 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1188 | return res; |
| 1189 | } |
| 1190 | |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 1191 | static int d40_terminate_all(struct d40_chan *chan) |
| 1192 | { |
| 1193 | unsigned long flags; |
| 1194 | int ret = 0; |
| 1195 | |
| 1196 | ret = d40_pause(chan); |
| 1197 | if (!ret && chan_is_physical(chan)) |
| 1198 | ret = d40_channel_execute_command(chan, D40_DMA_STOP); |
| 1199 | |
| 1200 | spin_lock_irqsave(&chan->lock, flags); |
| 1201 | d40_term_all(chan); |
| 1202 | spin_unlock_irqrestore(&chan->lock, flags); |
| 1203 | |
| 1204 | return ret; |
| 1205 | } |
| 1206 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1207 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
| 1208 | { |
| 1209 | struct d40_chan *d40c = container_of(tx->chan, |
| 1210 | struct d40_chan, |
| 1211 | chan); |
| 1212 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); |
| 1213 | unsigned long flags; |
| 1214 | |
| 1215 | spin_lock_irqsave(&d40c->lock, flags); |
| 1216 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1217 | d40c->chan.cookie++; |
| 1218 | |
| 1219 | if (d40c->chan.cookie < 0) |
| 1220 | d40c->chan.cookie = 1; |
| 1221 | |
| 1222 | d40d->txd.cookie = d40c->chan.cookie; |
| 1223 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1224 | d40_desc_queue(d40c, d40d); |
| 1225 | |
| 1226 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1227 | |
| 1228 | return tx->cookie; |
| 1229 | } |
| 1230 | |
| 1231 | static int d40_start(struct d40_chan *d40c) |
| 1232 | { |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 1233 | if (d40c->base->rev == 0) { |
| 1234 | int err; |
| 1235 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1236 | if (chan_is_logical(d40c)) { |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 1237 | err = d40_channel_execute_command(d40c, |
| 1238 | D40_DMA_SUSPEND_REQ); |
| 1239 | if (err) |
| 1240 | return err; |
| 1241 | } |
| 1242 | } |
| 1243 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1244 | if (chan_is_logical(d40c)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1245 | d40_config_set_event(d40c, true); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1246 | |
Jonas Aaberg | 0c32269 | 2010-06-20 21:25:46 +0000 | [diff] [blame] | 1247 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1248 | } |
| 1249 | |
| 1250 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) |
| 1251 | { |
| 1252 | struct d40_desc *d40d; |
| 1253 | int err; |
| 1254 | |
| 1255 | /* Start queued jobs, if any */ |
| 1256 | d40d = d40_first_queued(d40c); |
| 1257 | |
| 1258 | if (d40d != NULL) { |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1259 | if (!d40c->busy) |
| 1260 | d40c->busy = true; |
| 1261 | |
| 1262 | pm_runtime_get_sync(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1263 | |
| 1264 | /* Remove from queue */ |
| 1265 | d40_desc_remove(d40d); |
| 1266 | |
| 1267 | /* Add to active queue */ |
| 1268 | d40_desc_submit(d40c, d40d); |
| 1269 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1270 | /* Initiate DMA job */ |
| 1271 | d40_desc_load(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 1272 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1273 | /* Start dma job */ |
| 1274 | err = d40_start(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1275 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1276 | if (err) |
| 1277 | return NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1278 | } |
| 1279 | |
| 1280 | return d40d; |
| 1281 | } |
| 1282 | |
| 1283 | /* called from interrupt context */ |
| 1284 | static void dma_tc_handle(struct d40_chan *d40c) |
| 1285 | { |
| 1286 | struct d40_desc *d40d; |
| 1287 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1288 | /* Get first active entry from list */ |
| 1289 | d40d = d40_first_active_get(d40c); |
| 1290 | |
| 1291 | if (d40d == NULL) |
| 1292 | return; |
| 1293 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1294 | if (d40d->cyclic) { |
| 1295 | /* |
| 1296 | * If this was a paritially loaded list, we need to reloaded |
| 1297 | * it, and only when the list is completed. We need to check |
| 1298 | * for done because the interrupt will hit for every link, and |
| 1299 | * not just the last one. |
| 1300 | */ |
| 1301 | if (d40d->lli_current < d40d->lli_len |
| 1302 | && !d40_tx_is_linked(d40c) |
| 1303 | && !d40_residue(d40c)) { |
| 1304 | d40_lcla_free_all(d40c, d40d); |
| 1305 | d40_desc_load(d40c, d40d); |
| 1306 | (void) d40_start(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1307 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1308 | if (d40d->lli_current == d40d->lli_len) |
| 1309 | d40d->lli_current = 0; |
| 1310 | } |
| 1311 | } else { |
| 1312 | d40_lcla_free_all(d40c, d40d); |
| 1313 | |
| 1314 | if (d40d->lli_current < d40d->lli_len) { |
| 1315 | d40_desc_load(d40c, d40d); |
| 1316 | /* Start dma job */ |
| 1317 | (void) d40_start(d40c); |
| 1318 | return; |
| 1319 | } |
| 1320 | |
| 1321 | if (d40_queue_start(d40c) == NULL) |
| 1322 | d40c->busy = false; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1323 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1324 | pm_runtime_put_autosuspend(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1325 | } |
| 1326 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1327 | d40c->pending_tx++; |
| 1328 | tasklet_schedule(&d40c->tasklet); |
| 1329 | |
| 1330 | } |
| 1331 | |
| 1332 | static void dma_tasklet(unsigned long data) |
| 1333 | { |
| 1334 | struct d40_chan *d40c = (struct d40_chan *) data; |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1335 | struct d40_desc *d40d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1336 | unsigned long flags; |
| 1337 | dma_async_tx_callback callback; |
| 1338 | void *callback_param; |
| 1339 | |
| 1340 | spin_lock_irqsave(&d40c->lock, flags); |
| 1341 | |
| 1342 | /* Get first active entry from list */ |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1343 | d40d = d40_first_active_get(d40c); |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1344 | if (d40d == NULL) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1345 | goto err; |
| 1346 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1347 | if (!d40d->cyclic) |
| 1348 | d40c->completed = d40d->txd.cookie; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1349 | |
| 1350 | /* |
| 1351 | * If terminating a channel pending_tx is set to zero. |
| 1352 | * This prevents any finished active jobs to return to the client. |
| 1353 | */ |
| 1354 | if (d40c->pending_tx == 0) { |
| 1355 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1356 | return; |
| 1357 | } |
| 1358 | |
| 1359 | /* Callback to client */ |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1360 | callback = d40d->txd.callback; |
| 1361 | callback_param = d40d->txd.callback_param; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1362 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1363 | if (!d40d->cyclic) { |
| 1364 | if (async_tx_test_ack(&d40d->txd)) { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1365 | d40_desc_remove(d40d); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1366 | d40_desc_free(d40c, d40d); |
| 1367 | } else { |
| 1368 | if (!d40d->is_in_client_list) { |
| 1369 | d40_desc_remove(d40d); |
| 1370 | d40_lcla_free_all(d40c, d40d); |
| 1371 | list_add_tail(&d40d->node, &d40c->client); |
| 1372 | d40d->is_in_client_list = true; |
| 1373 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1374 | } |
| 1375 | } |
| 1376 | |
| 1377 | d40c->pending_tx--; |
| 1378 | |
| 1379 | if (d40c->pending_tx) |
| 1380 | tasklet_schedule(&d40c->tasklet); |
| 1381 | |
| 1382 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1383 | |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1384 | if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1385 | callback(callback_param); |
| 1386 | |
| 1387 | return; |
| 1388 | |
| 1389 | err: |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1390 | /* Rescue manoeuvre if receiving double interrupts */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1391 | if (d40c->pending_tx > 0) |
| 1392 | d40c->pending_tx--; |
| 1393 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1394 | } |
| 1395 | |
| 1396 | static irqreturn_t d40_handle_interrupt(int irq, void *data) |
| 1397 | { |
| 1398 | static const struct d40_interrupt_lookup il[] = { |
| 1399 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, |
| 1400 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, |
| 1401 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, |
| 1402 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, |
| 1403 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, |
| 1404 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, |
| 1405 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, |
| 1406 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, |
| 1407 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, |
| 1408 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, |
| 1409 | }; |
| 1410 | |
| 1411 | int i; |
| 1412 | u32 regs[ARRAY_SIZE(il)]; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1413 | u32 idx; |
| 1414 | u32 row; |
| 1415 | long chan = -1; |
| 1416 | struct d40_chan *d40c; |
| 1417 | unsigned long flags; |
| 1418 | struct d40_base *base = data; |
| 1419 | |
| 1420 | spin_lock_irqsave(&base->interrupt_lock, flags); |
| 1421 | |
| 1422 | /* Read interrupt status of both logical and physical channels */ |
| 1423 | for (i = 0; i < ARRAY_SIZE(il); i++) |
| 1424 | regs[i] = readl(base->virtbase + il[i].src); |
| 1425 | |
| 1426 | for (;;) { |
| 1427 | |
| 1428 | chan = find_next_bit((unsigned long *)regs, |
| 1429 | BITS_PER_LONG * ARRAY_SIZE(il), chan + 1); |
| 1430 | |
| 1431 | /* No more set bits found? */ |
| 1432 | if (chan == BITS_PER_LONG * ARRAY_SIZE(il)) |
| 1433 | break; |
| 1434 | |
| 1435 | row = chan / BITS_PER_LONG; |
| 1436 | idx = chan & (BITS_PER_LONG - 1); |
| 1437 | |
| 1438 | /* ACK interrupt */ |
Jonas Aaberg | 1b00348 | 2010-08-09 12:07:54 +0000 | [diff] [blame] | 1439 | writel(1 << idx, base->virtbase + il[row].clr); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1440 | |
| 1441 | if (il[row].offset == D40_PHY_CHAN) |
| 1442 | d40c = base->lookup_phy_chans[idx]; |
| 1443 | else |
| 1444 | d40c = base->lookup_log_chans[il[row].offset + idx]; |
| 1445 | spin_lock(&d40c->lock); |
| 1446 | |
| 1447 | if (!il[row].is_error) |
| 1448 | dma_tc_handle(d40c); |
| 1449 | else |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1450 | d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", |
| 1451 | chan, il[row].offset, idx); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1452 | |
| 1453 | spin_unlock(&d40c->lock); |
| 1454 | } |
| 1455 | |
| 1456 | spin_unlock_irqrestore(&base->interrupt_lock, flags); |
| 1457 | |
| 1458 | return IRQ_HANDLED; |
| 1459 | } |
| 1460 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1461 | static int d40_validate_conf(struct d40_chan *d40c, |
| 1462 | struct stedma40_chan_cfg *conf) |
| 1463 | { |
| 1464 | int res = 0; |
| 1465 | u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); |
| 1466 | u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); |
Rabin Vincent | 38bdbf0 | 2010-10-12 13:00:51 +0000 | [diff] [blame] | 1467 | bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1468 | |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1469 | if (!conf->dir) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1470 | chan_err(d40c, "Invalid direction.\n"); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1471 | res = -EINVAL; |
| 1472 | } |
| 1473 | |
| 1474 | if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && |
| 1475 | d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && |
| 1476 | d40c->runtime_addr == 0) { |
| 1477 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1478 | chan_err(d40c, "Invalid TX channel address (%d)\n", |
| 1479 | conf->dst_dev_type); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1480 | res = -EINVAL; |
| 1481 | } |
| 1482 | |
| 1483 | if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && |
| 1484 | d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && |
| 1485 | d40c->runtime_addr == 0) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1486 | chan_err(d40c, "Invalid RX channel address (%d)\n", |
| 1487 | conf->src_dev_type); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1488 | res = -EINVAL; |
| 1489 | } |
| 1490 | |
| 1491 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1492 | dst_event_group == STEDMA40_DEV_DST_MEMORY) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1493 | chan_err(d40c, "Invalid dst\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1494 | res = -EINVAL; |
| 1495 | } |
| 1496 | |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1497 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1498 | src_event_group == STEDMA40_DEV_SRC_MEMORY) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1499 | chan_err(d40c, "Invalid src\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1500 | res = -EINVAL; |
| 1501 | } |
| 1502 | |
| 1503 | if (src_event_group == STEDMA40_DEV_SRC_MEMORY && |
| 1504 | dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1505 | chan_err(d40c, "No event line\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1506 | res = -EINVAL; |
| 1507 | } |
| 1508 | |
| 1509 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && |
| 1510 | (src_event_group != dst_event_group)) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1511 | chan_err(d40c, "Invalid event group\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1512 | res = -EINVAL; |
| 1513 | } |
| 1514 | |
| 1515 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { |
| 1516 | /* |
| 1517 | * DMAC HW supports it. Will be added to this driver, |
| 1518 | * in case any dma client requires it. |
| 1519 | */ |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1520 | chan_err(d40c, "periph to periph not supported\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1521 | res = -EINVAL; |
| 1522 | } |
| 1523 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 1524 | if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * |
| 1525 | (1 << conf->src_info.data_width) != |
| 1526 | d40_psize_2_burst_size(is_log, conf->dst_info.psize) * |
| 1527 | (1 << conf->dst_info.data_width)) { |
| 1528 | /* |
| 1529 | * The DMAC hardware only supports |
| 1530 | * src (burst x width) == dst (burst x width) |
| 1531 | */ |
| 1532 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1533 | chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 1534 | res = -EINVAL; |
| 1535 | } |
| 1536 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1537 | return res; |
| 1538 | } |
| 1539 | |
| 1540 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src, |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1541 | int log_event_line, bool is_log) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1542 | { |
| 1543 | unsigned long flags; |
| 1544 | spin_lock_irqsave(&phy->lock, flags); |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1545 | if (!is_log) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1546 | /* Physical interrupts are masked per physical full channel */ |
| 1547 | if (phy->allocated_src == D40_ALLOC_FREE && |
| 1548 | phy->allocated_dst == D40_ALLOC_FREE) { |
| 1549 | phy->allocated_dst = D40_ALLOC_PHY; |
| 1550 | phy->allocated_src = D40_ALLOC_PHY; |
| 1551 | goto found; |
| 1552 | } else |
| 1553 | goto not_found; |
| 1554 | } |
| 1555 | |
| 1556 | /* Logical channel */ |
| 1557 | if (is_src) { |
| 1558 | if (phy->allocated_src == D40_ALLOC_PHY) |
| 1559 | goto not_found; |
| 1560 | |
| 1561 | if (phy->allocated_src == D40_ALLOC_FREE) |
| 1562 | phy->allocated_src = D40_ALLOC_LOG_FREE; |
| 1563 | |
| 1564 | if (!(phy->allocated_src & (1 << log_event_line))) { |
| 1565 | phy->allocated_src |= 1 << log_event_line; |
| 1566 | goto found; |
| 1567 | } else |
| 1568 | goto not_found; |
| 1569 | } else { |
| 1570 | if (phy->allocated_dst == D40_ALLOC_PHY) |
| 1571 | goto not_found; |
| 1572 | |
| 1573 | if (phy->allocated_dst == D40_ALLOC_FREE) |
| 1574 | phy->allocated_dst = D40_ALLOC_LOG_FREE; |
| 1575 | |
| 1576 | if (!(phy->allocated_dst & (1 << log_event_line))) { |
| 1577 | phy->allocated_dst |= 1 << log_event_line; |
| 1578 | goto found; |
| 1579 | } else |
| 1580 | goto not_found; |
| 1581 | } |
| 1582 | |
| 1583 | not_found: |
| 1584 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1585 | return false; |
| 1586 | found: |
| 1587 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1588 | return true; |
| 1589 | } |
| 1590 | |
| 1591 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, |
| 1592 | int log_event_line) |
| 1593 | { |
| 1594 | unsigned long flags; |
| 1595 | bool is_free = false; |
| 1596 | |
| 1597 | spin_lock_irqsave(&phy->lock, flags); |
| 1598 | if (!log_event_line) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1599 | phy->allocated_dst = D40_ALLOC_FREE; |
| 1600 | phy->allocated_src = D40_ALLOC_FREE; |
| 1601 | is_free = true; |
| 1602 | goto out; |
| 1603 | } |
| 1604 | |
| 1605 | /* Logical channel */ |
| 1606 | if (is_src) { |
| 1607 | phy->allocated_src &= ~(1 << log_event_line); |
| 1608 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) |
| 1609 | phy->allocated_src = D40_ALLOC_FREE; |
| 1610 | } else { |
| 1611 | phy->allocated_dst &= ~(1 << log_event_line); |
| 1612 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) |
| 1613 | phy->allocated_dst = D40_ALLOC_FREE; |
| 1614 | } |
| 1615 | |
| 1616 | is_free = ((phy->allocated_src | phy->allocated_dst) == |
| 1617 | D40_ALLOC_FREE); |
| 1618 | |
| 1619 | out: |
| 1620 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1621 | |
| 1622 | return is_free; |
| 1623 | } |
| 1624 | |
| 1625 | static int d40_allocate_channel(struct d40_chan *d40c) |
| 1626 | { |
| 1627 | int dev_type; |
| 1628 | int event_group; |
| 1629 | int event_line; |
| 1630 | struct d40_phy_res *phys; |
| 1631 | int i; |
| 1632 | int j; |
| 1633 | int log_num; |
| 1634 | bool is_src; |
Rabin Vincent | 38bdbf0 | 2010-10-12 13:00:51 +0000 | [diff] [blame] | 1635 | bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1636 | |
| 1637 | phys = d40c->base->phy_res; |
| 1638 | |
| 1639 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
| 1640 | dev_type = d40c->dma_cfg.src_dev_type; |
| 1641 | log_num = 2 * dev_type; |
| 1642 | is_src = true; |
| 1643 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
| 1644 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1645 | /* dst event lines are used for logical memcpy */ |
| 1646 | dev_type = d40c->dma_cfg.dst_dev_type; |
| 1647 | log_num = 2 * dev_type + 1; |
| 1648 | is_src = false; |
| 1649 | } else |
| 1650 | return -EINVAL; |
| 1651 | |
| 1652 | event_group = D40_TYPE_TO_GROUP(dev_type); |
| 1653 | event_line = D40_TYPE_TO_EVENT(dev_type); |
| 1654 | |
| 1655 | if (!is_log) { |
| 1656 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1657 | /* Find physical half channel */ |
| 1658 | for (i = 0; i < d40c->base->num_phy_chans; i++) { |
| 1659 | |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1660 | if (d40_alloc_mask_set(&phys[i], is_src, |
| 1661 | 0, is_log)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1662 | goto found_phy; |
| 1663 | } |
| 1664 | } else |
| 1665 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { |
| 1666 | int phy_num = j + event_group * 2; |
| 1667 | for (i = phy_num; i < phy_num + 2; i++) { |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 1668 | if (d40_alloc_mask_set(&phys[i], |
| 1669 | is_src, |
| 1670 | 0, |
| 1671 | is_log)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1672 | goto found_phy; |
| 1673 | } |
| 1674 | } |
| 1675 | return -EINVAL; |
| 1676 | found_phy: |
| 1677 | d40c->phy_chan = &phys[i]; |
| 1678 | d40c->log_num = D40_PHY_CHAN; |
| 1679 | goto out; |
| 1680 | } |
| 1681 | if (dev_type == -1) |
| 1682 | return -EINVAL; |
| 1683 | |
| 1684 | /* Find logical channel */ |
| 1685 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { |
| 1686 | int phy_num = j + event_group * 2; |
| 1687 | /* |
| 1688 | * Spread logical channels across all available physical rather |
| 1689 | * than pack every logical channel at the first available phy |
| 1690 | * channels. |
| 1691 | */ |
| 1692 | if (is_src) { |
| 1693 | for (i = phy_num; i < phy_num + 2; i++) { |
| 1694 | if (d40_alloc_mask_set(&phys[i], is_src, |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1695 | event_line, is_log)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1696 | goto found_log; |
| 1697 | } |
| 1698 | } else { |
| 1699 | for (i = phy_num + 1; i >= phy_num; i--) { |
| 1700 | if (d40_alloc_mask_set(&phys[i], is_src, |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1701 | event_line, is_log)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1702 | goto found_log; |
| 1703 | } |
| 1704 | } |
| 1705 | } |
| 1706 | return -EINVAL; |
| 1707 | |
| 1708 | found_log: |
| 1709 | d40c->phy_chan = &phys[i]; |
| 1710 | d40c->log_num = log_num; |
| 1711 | out: |
| 1712 | |
| 1713 | if (is_log) |
| 1714 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; |
| 1715 | else |
| 1716 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; |
| 1717 | |
| 1718 | return 0; |
| 1719 | |
| 1720 | } |
| 1721 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1722 | static int d40_config_memcpy(struct d40_chan *d40c) |
| 1723 | { |
| 1724 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; |
| 1725 | |
| 1726 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { |
| 1727 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; |
| 1728 | d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; |
| 1729 | d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> |
| 1730 | memcpy[d40c->chan.chan_id]; |
| 1731 | |
| 1732 | } else if (dma_has_cap(DMA_MEMCPY, cap) && |
| 1733 | dma_has_cap(DMA_SLAVE, cap)) { |
| 1734 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; |
| 1735 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1736 | chan_err(d40c, "No memcpy\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1737 | return -EINVAL; |
| 1738 | } |
| 1739 | |
| 1740 | return 0; |
| 1741 | } |
| 1742 | |
| 1743 | |
| 1744 | static int d40_free_dma(struct d40_chan *d40c) |
| 1745 | { |
| 1746 | |
| 1747 | int res = 0; |
Jonas Aaberg | d181b3a | 2010-06-20 21:26:38 +0000 | [diff] [blame] | 1748 | u32 event; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1749 | struct d40_phy_res *phy = d40c->phy_chan; |
| 1750 | bool is_src; |
| 1751 | |
| 1752 | /* Terminate all queued and active transfers */ |
| 1753 | d40_term_all(d40c); |
| 1754 | |
| 1755 | if (phy == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1756 | chan_err(d40c, "phy == null\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1757 | return -EINVAL; |
| 1758 | } |
| 1759 | |
| 1760 | if (phy->allocated_src == D40_ALLOC_FREE && |
| 1761 | phy->allocated_dst == D40_ALLOC_FREE) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1762 | chan_err(d40c, "channel already free\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1763 | return -EINVAL; |
| 1764 | } |
| 1765 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1766 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
| 1767 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1768 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1769 | is_src = false; |
| 1770 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
| 1771 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1772 | is_src = true; |
| 1773 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1774 | chan_err(d40c, "Unknown direction\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1775 | return -EINVAL; |
| 1776 | } |
| 1777 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1778 | pm_runtime_get_sync(d40c->base->dev); |
Jonas Aaberg | d181b3a | 2010-06-20 21:26:38 +0000 | [diff] [blame] | 1779 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
| 1780 | if (res) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1781 | chan_err(d40c, "suspend failed\n"); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1782 | goto out; |
Jonas Aaberg | d181b3a | 2010-06-20 21:26:38 +0000 | [diff] [blame] | 1783 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1784 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1785 | if (chan_is_logical(d40c)) { |
Jonas Aaberg | d181b3a | 2010-06-20 21:26:38 +0000 | [diff] [blame] | 1786 | /* Release logical channel, deactivate the event line */ |
| 1787 | |
| 1788 | d40_config_set_event(d40c, false); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1789 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
| 1790 | |
| 1791 | /* |
| 1792 | * Check if there are more logical allocation |
| 1793 | * on this phy channel. |
| 1794 | */ |
| 1795 | if (!d40_alloc_mask_free(phy, is_src, event)) { |
| 1796 | /* Resume the other logical channels if any */ |
| 1797 | if (d40_chan_has_events(d40c)) { |
| 1798 | res = d40_channel_execute_command(d40c, |
| 1799 | D40_DMA_RUN); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1800 | if (res) |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1801 | chan_err(d40c, |
| 1802 | "Executing RUN command\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1803 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1804 | goto out; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1805 | } |
Jonas Aaberg | d181b3a | 2010-06-20 21:26:38 +0000 | [diff] [blame] | 1806 | } else { |
| 1807 | (void) d40_alloc_mask_free(phy, is_src, 0); |
| 1808 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1809 | |
| 1810 | /* Release physical channel */ |
| 1811 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); |
| 1812 | if (res) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1813 | chan_err(d40c, "Failed to stop channel\n"); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1814 | goto out; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1815 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1816 | |
| 1817 | if (d40c->busy) { |
| 1818 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1819 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 1820 | } |
| 1821 | |
| 1822 | d40c->busy = false; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1823 | d40c->phy_chan = NULL; |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 1824 | d40c->configured = false; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1825 | d40c->base->lookup_phy_chans[phy->num] = NULL; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1826 | out: |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1827 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1828 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1829 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 1830 | return res; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1831 | } |
| 1832 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1833 | static bool d40_is_paused(struct d40_chan *d40c) |
| 1834 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1835 | void __iomem *chanbase = chan_base(d40c); |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1836 | bool is_paused = false; |
| 1837 | unsigned long flags; |
| 1838 | void __iomem *active_reg; |
| 1839 | u32 status; |
| 1840 | u32 event; |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1841 | |
| 1842 | spin_lock_irqsave(&d40c->lock, flags); |
| 1843 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1844 | if (chan_is_physical(d40c)) { |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1845 | if (d40c->phy_chan->num % 2 == 0) |
| 1846 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 1847 | else |
| 1848 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 1849 | |
| 1850 | status = (readl(active_reg) & |
| 1851 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 1852 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1853 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) |
| 1854 | is_paused = true; |
| 1855 | |
| 1856 | goto _exit; |
| 1857 | } |
| 1858 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1859 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1860 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1861 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1862 | status = readl(chanbase + D40_CHAN_REG_SDLNK); |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1863 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1864 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1865 | status = readl(chanbase + D40_CHAN_REG_SSLNK); |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1866 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1867 | chan_err(d40c, "Unknown direction\n"); |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1868 | goto _exit; |
| 1869 | } |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1870 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1871 | status = (status & D40_EVENTLINE_MASK(event)) >> |
| 1872 | D40_EVENTLINE_POS(event); |
| 1873 | |
| 1874 | if (status != D40_DMA_RUN) |
| 1875 | is_paused = true; |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1876 | _exit: |
| 1877 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1878 | return is_paused; |
| 1879 | |
| 1880 | } |
| 1881 | |
| 1882 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1883 | static u32 stedma40_residue(struct dma_chan *chan) |
| 1884 | { |
| 1885 | struct d40_chan *d40c = |
| 1886 | container_of(chan, struct d40_chan, chan); |
| 1887 | u32 bytes_left; |
| 1888 | unsigned long flags; |
| 1889 | |
| 1890 | spin_lock_irqsave(&d40c->lock, flags); |
| 1891 | bytes_left = d40_residue(d40c); |
| 1892 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1893 | |
| 1894 | return bytes_left; |
| 1895 | } |
| 1896 | |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1897 | static int |
| 1898 | d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, |
| 1899 | struct scatterlist *sg_src, struct scatterlist *sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 1900 | unsigned int sg_len, dma_addr_t src_dev_addr, |
| 1901 | dma_addr_t dst_dev_addr) |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1902 | { |
| 1903 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 1904 | struct stedma40_half_channel_info *src_info = &cfg->src_info; |
| 1905 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1906 | int ret; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1907 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1908 | ret = d40_log_sg_to_lli(sg_src, sg_len, |
| 1909 | src_dev_addr, |
| 1910 | desc->lli_log.src, |
| 1911 | chan->log_def.lcsp1, |
| 1912 | src_info->data_width, |
| 1913 | dst_info->data_width); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1914 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1915 | ret = d40_log_sg_to_lli(sg_dst, sg_len, |
| 1916 | dst_dev_addr, |
| 1917 | desc->lli_log.dst, |
| 1918 | chan->log_def.lcsp3, |
| 1919 | dst_info->data_width, |
| 1920 | src_info->data_width); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1921 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1922 | return ret < 0 ? ret : 0; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1923 | } |
| 1924 | |
| 1925 | static int |
| 1926 | d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, |
| 1927 | struct scatterlist *sg_src, struct scatterlist *sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 1928 | unsigned int sg_len, dma_addr_t src_dev_addr, |
| 1929 | dma_addr_t dst_dev_addr) |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1930 | { |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1931 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 1932 | struct stedma40_half_channel_info *src_info = &cfg->src_info; |
| 1933 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1934 | unsigned long flags = 0; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1935 | int ret; |
| 1936 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1937 | if (desc->cyclic) |
| 1938 | flags |= LLI_CYCLIC | LLI_TERM_INT; |
| 1939 | |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1940 | ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, |
| 1941 | desc->lli_phy.src, |
| 1942 | virt_to_phys(desc->lli_phy.src), |
| 1943 | chan->src_def_cfg, |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1944 | src_info, dst_info, flags); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1945 | |
| 1946 | ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, |
| 1947 | desc->lli_phy.dst, |
| 1948 | virt_to_phys(desc->lli_phy.dst), |
| 1949 | chan->dst_def_cfg, |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1950 | dst_info, src_info, flags); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1951 | |
| 1952 | dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, |
| 1953 | desc->lli_pool.size, DMA_TO_DEVICE); |
| 1954 | |
| 1955 | return ret < 0 ? ret : 0; |
| 1956 | } |
| 1957 | |
| 1958 | |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 1959 | static struct d40_desc * |
| 1960 | d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, |
| 1961 | unsigned int sg_len, unsigned long dma_flags) |
| 1962 | { |
| 1963 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 1964 | struct d40_desc *desc; |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 1965 | int ret; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 1966 | |
| 1967 | desc = d40_desc_get(chan); |
| 1968 | if (!desc) |
| 1969 | return NULL; |
| 1970 | |
| 1971 | desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, |
| 1972 | cfg->dst_info.data_width); |
| 1973 | if (desc->lli_len < 0) { |
| 1974 | chan_err(chan, "Unaligned size\n"); |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 1975 | goto err; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 1976 | } |
| 1977 | |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 1978 | ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); |
| 1979 | if (ret < 0) { |
| 1980 | chan_err(chan, "Could not allocate lli\n"); |
| 1981 | goto err; |
| 1982 | } |
| 1983 | |
| 1984 | |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 1985 | desc->lli_current = 0; |
| 1986 | desc->txd.flags = dma_flags; |
| 1987 | desc->txd.tx_submit = d40_tx_submit; |
| 1988 | |
| 1989 | dma_async_tx_descriptor_init(&desc->txd, &chan->chan); |
| 1990 | |
| 1991 | return desc; |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 1992 | |
| 1993 | err: |
| 1994 | d40_desc_free(chan, desc); |
| 1995 | return NULL; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 1996 | } |
| 1997 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 1998 | static dma_addr_t |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1999 | d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2000 | { |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2001 | struct stedma40_platform_data *plat = chan->base->plat_data; |
| 2002 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
Philippe Langlais | 711b9ce | 2011-05-07 17:09:43 +0200 | [diff] [blame] | 2003 | dma_addr_t addr = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2004 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2005 | if (chan->runtime_addr) |
| 2006 | return chan->runtime_addr; |
| 2007 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2008 | if (direction == DMA_DEV_TO_MEM) |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2009 | addr = plat->dev_rx[cfg->src_dev_type]; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2010 | else if (direction == DMA_MEM_TO_DEV) |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2011 | addr = plat->dev_tx[cfg->dst_dev_type]; |
| 2012 | |
| 2013 | return addr; |
| 2014 | } |
| 2015 | |
| 2016 | static struct dma_async_tx_descriptor * |
| 2017 | d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, |
| 2018 | struct scatterlist *sg_dst, unsigned int sg_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2019 | enum dma_transfer_direction direction, unsigned long dma_flags) |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2020 | { |
| 2021 | struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2022 | dma_addr_t src_dev_addr = 0; |
| 2023 | dma_addr_t dst_dev_addr = 0; |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2024 | struct d40_desc *desc; |
| 2025 | unsigned long flags; |
| 2026 | int ret; |
| 2027 | |
| 2028 | if (!chan->phy_chan) { |
| 2029 | chan_err(chan, "Cannot prepare unallocated channel\n"); |
| 2030 | return NULL; |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2031 | } |
| 2032 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2033 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2034 | spin_lock_irqsave(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2035 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2036 | desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); |
| 2037 | if (desc == NULL) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2038 | goto err; |
| 2039 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2040 | if (sg_next(&sg_src[sg_len - 1]) == sg_src) |
| 2041 | desc->cyclic = true; |
| 2042 | |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2043 | if (direction != DMA_NONE) { |
| 2044 | dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); |
| 2045 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2046 | if (direction == DMA_DEV_TO_MEM) |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2047 | src_dev_addr = dev_addr; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2048 | else if (direction == DMA_MEM_TO_DEV) |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2049 | dst_dev_addr = dev_addr; |
| 2050 | } |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2051 | |
| 2052 | if (chan_is_logical(chan)) |
| 2053 | ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2054 | sg_len, src_dev_addr, dst_dev_addr); |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2055 | else |
| 2056 | ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2057 | sg_len, src_dev_addr, dst_dev_addr); |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2058 | |
| 2059 | if (ret) { |
| 2060 | chan_err(chan, "Failed to prepare %s sg job: %d\n", |
| 2061 | chan_is_logical(chan) ? "log" : "phy", ret); |
| 2062 | goto err; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2063 | } |
| 2064 | |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 2065 | /* |
| 2066 | * add descriptor to the prepare queue in order to be able |
| 2067 | * to free them later in terminate_all |
| 2068 | */ |
| 2069 | list_add_tail(&desc->node, &chan->prepare_queue); |
| 2070 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2071 | spin_unlock_irqrestore(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2072 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2073 | return &desc->txd; |
| 2074 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2075 | err: |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2076 | if (desc) |
| 2077 | d40_desc_free(chan, desc); |
| 2078 | spin_unlock_irqrestore(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2079 | return NULL; |
| 2080 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2081 | |
| 2082 | bool stedma40_filter(struct dma_chan *chan, void *data) |
| 2083 | { |
| 2084 | struct stedma40_chan_cfg *info = data; |
| 2085 | struct d40_chan *d40c = |
| 2086 | container_of(chan, struct d40_chan, chan); |
| 2087 | int err; |
| 2088 | |
| 2089 | if (data) { |
| 2090 | err = d40_validate_conf(d40c, info); |
| 2091 | if (!err) |
| 2092 | d40c->dma_cfg = *info; |
| 2093 | } else |
| 2094 | err = d40_config_memcpy(d40c); |
| 2095 | |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 2096 | if (!err) |
| 2097 | d40c->configured = true; |
| 2098 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2099 | return err == 0; |
| 2100 | } |
| 2101 | EXPORT_SYMBOL(stedma40_filter); |
| 2102 | |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2103 | static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) |
| 2104 | { |
| 2105 | bool realtime = d40c->dma_cfg.realtime; |
| 2106 | bool highprio = d40c->dma_cfg.high_priority; |
| 2107 | u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1; |
| 2108 | u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1; |
| 2109 | u32 event = D40_TYPE_TO_EVENT(dev_type); |
| 2110 | u32 group = D40_TYPE_TO_GROUP(dev_type); |
| 2111 | u32 bit = 1 << event; |
| 2112 | |
| 2113 | /* Destination event lines are stored in the upper halfword */ |
| 2114 | if (!src) |
| 2115 | bit <<= 16; |
| 2116 | |
| 2117 | writel(bit, d40c->base->virtbase + prioreg + group * 4); |
| 2118 | writel(bit, d40c->base->virtbase + rtreg + group * 4); |
| 2119 | } |
| 2120 | |
| 2121 | static void d40_set_prio_realtime(struct d40_chan *d40c) |
| 2122 | { |
| 2123 | if (d40c->base->rev < 3) |
| 2124 | return; |
| 2125 | |
| 2126 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || |
| 2127 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) |
| 2128 | __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); |
| 2129 | |
| 2130 | if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || |
| 2131 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) |
| 2132 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); |
| 2133 | } |
| 2134 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2135 | /* DMA ENGINE functions */ |
| 2136 | static int d40_alloc_chan_resources(struct dma_chan *chan) |
| 2137 | { |
| 2138 | int err; |
| 2139 | unsigned long flags; |
| 2140 | struct d40_chan *d40c = |
| 2141 | container_of(chan, struct d40_chan, chan); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2142 | bool is_free_phy; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2143 | spin_lock_irqsave(&d40c->lock, flags); |
| 2144 | |
| 2145 | d40c->completed = chan->cookie = 1; |
| 2146 | |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 2147 | /* If no dma configuration is set use default configuration (memcpy) */ |
| 2148 | if (!d40c->configured) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2149 | err = d40_config_memcpy(d40c); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2150 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2151 | chan_err(d40c, "Failed to configure memcpy channel\n"); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2152 | goto fail; |
| 2153 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2154 | } |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2155 | is_free_phy = (d40c->phy_chan == NULL); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2156 | |
| 2157 | err = d40_allocate_channel(d40c); |
| 2158 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2159 | chan_err(d40c, "Failed to allocate channel\n"); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2160 | d40c->configured = false; |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2161 | goto fail; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2162 | } |
| 2163 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2164 | pm_runtime_get_sync(d40c->base->dev); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2165 | /* Fill in basic CFG register values */ |
| 2166 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2167 | &d40c->dst_def_cfg, chan_is_logical(d40c)); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2168 | |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2169 | d40_set_prio_realtime(d40c); |
| 2170 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2171 | if (chan_is_logical(d40c)) { |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2172 | d40_log_cfg(&d40c->dma_cfg, |
| 2173 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
| 2174 | |
| 2175 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) |
| 2176 | d40c->lcpa = d40c->base->lcpa_base + |
| 2177 | d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; |
| 2178 | else |
| 2179 | d40c->lcpa = d40c->base->lcpa_base + |
| 2180 | d40c->dma_cfg.dst_dev_type * |
| 2181 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; |
| 2182 | } |
| 2183 | |
| 2184 | /* |
| 2185 | * Only write channel configuration to the DMA if the physical |
| 2186 | * resource is free. In case of multiple logical channels |
| 2187 | * on the same physical resource, only the first write is necessary. |
| 2188 | */ |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 2189 | if (is_free_phy) |
| 2190 | d40_config_write(d40c); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2191 | fail: |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2192 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2193 | pm_runtime_put_autosuspend(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2194 | spin_unlock_irqrestore(&d40c->lock, flags); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2195 | return err; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2196 | } |
| 2197 | |
| 2198 | static void d40_free_chan_resources(struct dma_chan *chan) |
| 2199 | { |
| 2200 | struct d40_chan *d40c = |
| 2201 | container_of(chan, struct d40_chan, chan); |
| 2202 | int err; |
| 2203 | unsigned long flags; |
| 2204 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2205 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2206 | chan_err(d40c, "Cannot free unallocated channel\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2207 | return; |
| 2208 | } |
| 2209 | |
| 2210 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2211 | spin_lock_irqsave(&d40c->lock, flags); |
| 2212 | |
| 2213 | err = d40_free_dma(d40c); |
| 2214 | |
| 2215 | if (err) |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2216 | chan_err(d40c, "Failed to free channel\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2217 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2218 | } |
| 2219 | |
| 2220 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, |
| 2221 | dma_addr_t dst, |
| 2222 | dma_addr_t src, |
| 2223 | size_t size, |
Jonas Aaberg | 2a61434 | 2010-06-20 21:25:24 +0000 | [diff] [blame] | 2224 | unsigned long dma_flags) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2225 | { |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2226 | struct scatterlist dst_sg; |
| 2227 | struct scatterlist src_sg; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2228 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2229 | sg_init_table(&dst_sg, 1); |
| 2230 | sg_init_table(&src_sg, 1); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2231 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2232 | sg_dma_address(&dst_sg) = dst; |
| 2233 | sg_dma_address(&src_sg) = src; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2234 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2235 | sg_dma_len(&dst_sg) = size; |
| 2236 | sg_dma_len(&src_sg) = size; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2237 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2238 | return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2239 | } |
| 2240 | |
Ira Snyder | 0d68866 | 2010-09-30 11:46:47 +0000 | [diff] [blame] | 2241 | static struct dma_async_tx_descriptor * |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2242 | d40_prep_memcpy_sg(struct dma_chan *chan, |
| 2243 | struct scatterlist *dst_sg, unsigned int dst_nents, |
| 2244 | struct scatterlist *src_sg, unsigned int src_nents, |
| 2245 | unsigned long dma_flags) |
Ira Snyder | 0d68866 | 2010-09-30 11:46:47 +0000 | [diff] [blame] | 2246 | { |
| 2247 | if (dst_nents != src_nents) |
| 2248 | return NULL; |
| 2249 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2250 | return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags); |
Rabin Vincent | 00ac034 | 2011-01-25 11:18:20 +0100 | [diff] [blame] | 2251 | } |
| 2252 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2253 | static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, |
| 2254 | struct scatterlist *sgl, |
| 2255 | unsigned int sg_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2256 | enum dma_transfer_direction direction, |
Jonas Aaberg | 2a61434 | 2010-06-20 21:25:24 +0000 | [diff] [blame] | 2257 | unsigned long dma_flags) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2258 | { |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2259 | if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) |
Rabin Vincent | 00ac034 | 2011-01-25 11:18:20 +0100 | [diff] [blame] | 2260 | return NULL; |
| 2261 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2262 | return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2263 | } |
| 2264 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2265 | static struct dma_async_tx_descriptor * |
| 2266 | dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, |
| 2267 | size_t buf_len, size_t period_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2268 | enum dma_transfer_direction direction) |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2269 | { |
| 2270 | unsigned int periods = buf_len / period_len; |
| 2271 | struct dma_async_tx_descriptor *txd; |
| 2272 | struct scatterlist *sg; |
| 2273 | int i; |
| 2274 | |
Robert Marklund | 79ca7ec | 2011-06-27 11:33:24 +0200 | [diff] [blame] | 2275 | sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2276 | for (i = 0; i < periods; i++) { |
| 2277 | sg_dma_address(&sg[i]) = dma_addr; |
| 2278 | sg_dma_len(&sg[i]) = period_len; |
| 2279 | dma_addr += period_len; |
| 2280 | } |
| 2281 | |
| 2282 | sg[periods].offset = 0; |
| 2283 | sg[periods].length = 0; |
| 2284 | sg[periods].page_link = |
| 2285 | ((unsigned long)sg | 0x01) & ~0x02; |
| 2286 | |
| 2287 | txd = d40_prep_sg(chan, sg, sg, periods, direction, |
| 2288 | DMA_PREP_INTERRUPT); |
| 2289 | |
| 2290 | kfree(sg); |
| 2291 | |
| 2292 | return txd; |
| 2293 | } |
| 2294 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2295 | static enum dma_status d40_tx_status(struct dma_chan *chan, |
| 2296 | dma_cookie_t cookie, |
| 2297 | struct dma_tx_state *txstate) |
| 2298 | { |
| 2299 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2300 | dma_cookie_t last_used; |
| 2301 | dma_cookie_t last_complete; |
| 2302 | int ret; |
| 2303 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2304 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2305 | chan_err(d40c, "Cannot read status of unallocated channel\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2306 | return -EINVAL; |
| 2307 | } |
| 2308 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2309 | last_complete = d40c->completed; |
| 2310 | last_used = chan->cookie; |
| 2311 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2312 | if (d40_is_paused(d40c)) |
| 2313 | ret = DMA_PAUSED; |
| 2314 | else |
| 2315 | ret = dma_async_is_complete(cookie, last_complete, last_used); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2316 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2317 | dma_set_tx_state(txstate, last_complete, last_used, |
| 2318 | stedma40_residue(chan)); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2319 | |
| 2320 | return ret; |
| 2321 | } |
| 2322 | |
| 2323 | static void d40_issue_pending(struct dma_chan *chan) |
| 2324 | { |
| 2325 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2326 | unsigned long flags; |
| 2327 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2328 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2329 | chan_err(d40c, "Channel is not allocated!\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2330 | return; |
| 2331 | } |
| 2332 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2333 | spin_lock_irqsave(&d40c->lock, flags); |
| 2334 | |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 2335 | list_splice_tail_init(&d40c->pending_queue, &d40c->queue); |
| 2336 | |
| 2337 | /* Busy means that queued jobs are already being processed */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2338 | if (!d40c->busy) |
| 2339 | (void) d40_queue_start(d40c); |
| 2340 | |
| 2341 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2342 | } |
| 2343 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2344 | static int |
| 2345 | dma40_config_to_halfchannel(struct d40_chan *d40c, |
| 2346 | struct stedma40_half_channel_info *info, |
| 2347 | enum dma_slave_buswidth width, |
| 2348 | u32 maxburst) |
| 2349 | { |
| 2350 | enum stedma40_periph_data_width addr_width; |
| 2351 | int psize; |
| 2352 | |
| 2353 | switch (width) { |
| 2354 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
| 2355 | addr_width = STEDMA40_BYTE_WIDTH; |
| 2356 | break; |
| 2357 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
| 2358 | addr_width = STEDMA40_HALFWORD_WIDTH; |
| 2359 | break; |
| 2360 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
| 2361 | addr_width = STEDMA40_WORD_WIDTH; |
| 2362 | break; |
| 2363 | case DMA_SLAVE_BUSWIDTH_8_BYTES: |
| 2364 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; |
| 2365 | break; |
| 2366 | default: |
| 2367 | dev_err(d40c->base->dev, |
| 2368 | "illegal peripheral address width " |
| 2369 | "requested (%d)\n", |
| 2370 | width); |
| 2371 | return -EINVAL; |
| 2372 | } |
| 2373 | |
| 2374 | if (chan_is_logical(d40c)) { |
| 2375 | if (maxburst >= 16) |
| 2376 | psize = STEDMA40_PSIZE_LOG_16; |
| 2377 | else if (maxburst >= 8) |
| 2378 | psize = STEDMA40_PSIZE_LOG_8; |
| 2379 | else if (maxburst >= 4) |
| 2380 | psize = STEDMA40_PSIZE_LOG_4; |
| 2381 | else |
| 2382 | psize = STEDMA40_PSIZE_LOG_1; |
| 2383 | } else { |
| 2384 | if (maxburst >= 16) |
| 2385 | psize = STEDMA40_PSIZE_PHY_16; |
| 2386 | else if (maxburst >= 8) |
| 2387 | psize = STEDMA40_PSIZE_PHY_8; |
| 2388 | else if (maxburst >= 4) |
| 2389 | psize = STEDMA40_PSIZE_PHY_4; |
| 2390 | else |
| 2391 | psize = STEDMA40_PSIZE_PHY_1; |
| 2392 | } |
| 2393 | |
| 2394 | info->data_width = addr_width; |
| 2395 | info->psize = psize; |
| 2396 | info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; |
| 2397 | |
| 2398 | return 0; |
| 2399 | } |
| 2400 | |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2401 | /* Runtime reconfiguration extension */ |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2402 | static int d40_set_runtime_config(struct dma_chan *chan, |
| 2403 | struct dma_slave_config *config) |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2404 | { |
| 2405 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2406 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2407 | enum dma_slave_buswidth src_addr_width, dst_addr_width; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2408 | dma_addr_t config_addr; |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2409 | u32 src_maxburst, dst_maxburst; |
| 2410 | int ret; |
| 2411 | |
| 2412 | src_addr_width = config->src_addr_width; |
| 2413 | src_maxburst = config->src_maxburst; |
| 2414 | dst_addr_width = config->dst_addr_width; |
| 2415 | dst_maxburst = config->dst_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2416 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2417 | if (config->direction == DMA_DEV_TO_MEM) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2418 | dma_addr_t dev_addr_rx = |
| 2419 | d40c->base->plat_data->dev_rx[cfg->src_dev_type]; |
| 2420 | |
| 2421 | config_addr = config->src_addr; |
| 2422 | if (dev_addr_rx) |
| 2423 | dev_dbg(d40c->base->dev, |
| 2424 | "channel has a pre-wired RX address %08x " |
| 2425 | "overriding with %08x\n", |
| 2426 | dev_addr_rx, config_addr); |
| 2427 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) |
| 2428 | dev_dbg(d40c->base->dev, |
| 2429 | "channel was not configured for peripheral " |
| 2430 | "to memory transfer (%d) overriding\n", |
| 2431 | cfg->dir); |
| 2432 | cfg->dir = STEDMA40_PERIPH_TO_MEM; |
| 2433 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2434 | /* Configure the memory side */ |
| 2435 | if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 2436 | dst_addr_width = src_addr_width; |
| 2437 | if (dst_maxburst == 0) |
| 2438 | dst_maxburst = src_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2439 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2440 | } else if (config->direction == DMA_MEM_TO_DEV) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2441 | dma_addr_t dev_addr_tx = |
| 2442 | d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; |
| 2443 | |
| 2444 | config_addr = config->dst_addr; |
| 2445 | if (dev_addr_tx) |
| 2446 | dev_dbg(d40c->base->dev, |
| 2447 | "channel has a pre-wired TX address %08x " |
| 2448 | "overriding with %08x\n", |
| 2449 | dev_addr_tx, config_addr); |
| 2450 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) |
| 2451 | dev_dbg(d40c->base->dev, |
| 2452 | "channel was not configured for memory " |
| 2453 | "to peripheral transfer (%d) overriding\n", |
| 2454 | cfg->dir); |
| 2455 | cfg->dir = STEDMA40_MEM_TO_PERIPH; |
| 2456 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2457 | /* Configure the memory side */ |
| 2458 | if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 2459 | src_addr_width = dst_addr_width; |
| 2460 | if (src_maxburst == 0) |
| 2461 | src_maxburst = dst_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2462 | } else { |
| 2463 | dev_err(d40c->base->dev, |
| 2464 | "unrecognized channel direction %d\n", |
| 2465 | config->direction); |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2466 | return -EINVAL; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2467 | } |
| 2468 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2469 | if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2470 | dev_err(d40c->base->dev, |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2471 | "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", |
| 2472 | src_maxburst, |
| 2473 | src_addr_width, |
| 2474 | dst_maxburst, |
| 2475 | dst_addr_width); |
| 2476 | return -EINVAL; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2477 | } |
| 2478 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2479 | ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, |
| 2480 | src_addr_width, |
| 2481 | src_maxburst); |
| 2482 | if (ret) |
| 2483 | return ret; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2484 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2485 | ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, |
| 2486 | dst_addr_width, |
| 2487 | dst_maxburst); |
| 2488 | if (ret) |
| 2489 | return ret; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2490 | |
Per Forlin | a59670a | 2010-10-06 09:05:27 +0000 | [diff] [blame] | 2491 | /* Fill in register values */ |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2492 | if (chan_is_logical(d40c)) |
Per Forlin | a59670a | 2010-10-06 09:05:27 +0000 | [diff] [blame] | 2493 | d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
| 2494 | else |
| 2495 | d40_phy_cfg(cfg, &d40c->src_def_cfg, |
| 2496 | &d40c->dst_def_cfg, false); |
| 2497 | |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2498 | /* These settings will take precedence later */ |
| 2499 | d40c->runtime_addr = config_addr; |
| 2500 | d40c->runtime_direction = config->direction; |
| 2501 | dev_dbg(d40c->base->dev, |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2502 | "configured channel %s for %s, data width %d/%d, " |
| 2503 | "maxburst %d/%d elements, LE, no flow control\n", |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2504 | dma_chan_name(chan), |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2505 | (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX", |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2506 | src_addr_width, dst_addr_width, |
| 2507 | src_maxburst, dst_maxburst); |
| 2508 | |
| 2509 | return 0; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2510 | } |
| 2511 | |
Linus Walleij | 0582763 | 2010-05-17 16:30:42 -0700 | [diff] [blame] | 2512 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 2513 | unsigned long arg) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2514 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2515 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2516 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2517 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2518 | chan_err(d40c, "Channel is not allocated!\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2519 | return -EINVAL; |
| 2520 | } |
| 2521 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2522 | switch (cmd) { |
| 2523 | case DMA_TERMINATE_ALL: |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 2524 | return d40_terminate_all(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2525 | case DMA_PAUSE: |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 2526 | return d40_pause(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2527 | case DMA_RESUME: |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 2528 | return d40_resume(d40c); |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2529 | case DMA_SLAVE_CONFIG: |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2530 | return d40_set_runtime_config(chan, |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2531 | (struct dma_slave_config *) arg); |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2532 | default: |
| 2533 | break; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2534 | } |
| 2535 | |
| 2536 | /* Other commands are unimplemented */ |
| 2537 | return -ENXIO; |
| 2538 | } |
| 2539 | |
| 2540 | /* Initialization functions */ |
| 2541 | |
| 2542 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, |
| 2543 | struct d40_chan *chans, int offset, |
| 2544 | int num_chans) |
| 2545 | { |
| 2546 | int i = 0; |
| 2547 | struct d40_chan *d40c; |
| 2548 | |
| 2549 | INIT_LIST_HEAD(&dma->channels); |
| 2550 | |
| 2551 | for (i = offset; i < offset + num_chans; i++) { |
| 2552 | d40c = &chans[i]; |
| 2553 | d40c->base = base; |
| 2554 | d40c->chan.device = dma; |
| 2555 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2556 | spin_lock_init(&d40c->lock); |
| 2557 | |
| 2558 | d40c->log_num = D40_PHY_CHAN; |
| 2559 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2560 | INIT_LIST_HEAD(&d40c->active); |
| 2561 | INIT_LIST_HEAD(&d40c->queue); |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 2562 | INIT_LIST_HEAD(&d40c->pending_queue); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2563 | INIT_LIST_HEAD(&d40c->client); |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 2564 | INIT_LIST_HEAD(&d40c->prepare_queue); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2565 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2566 | tasklet_init(&d40c->tasklet, dma_tasklet, |
| 2567 | (unsigned long) d40c); |
| 2568 | |
| 2569 | list_add_tail(&d40c->chan.device_node, |
| 2570 | &dma->channels); |
| 2571 | } |
| 2572 | } |
| 2573 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2574 | static void d40_ops_init(struct d40_base *base, struct dma_device *dev) |
| 2575 | { |
| 2576 | if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) |
| 2577 | dev->device_prep_slave_sg = d40_prep_slave_sg; |
| 2578 | |
| 2579 | if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { |
| 2580 | dev->device_prep_dma_memcpy = d40_prep_memcpy; |
| 2581 | |
| 2582 | /* |
| 2583 | * This controller can only access address at even |
| 2584 | * 32bit boundaries, i.e. 2^2 |
| 2585 | */ |
| 2586 | dev->copy_align = 2; |
| 2587 | } |
| 2588 | |
| 2589 | if (dma_has_cap(DMA_SG, dev->cap_mask)) |
| 2590 | dev->device_prep_dma_sg = d40_prep_memcpy_sg; |
| 2591 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2592 | if (dma_has_cap(DMA_CYCLIC, dev->cap_mask)) |
| 2593 | dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic; |
| 2594 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2595 | dev->device_alloc_chan_resources = d40_alloc_chan_resources; |
| 2596 | dev->device_free_chan_resources = d40_free_chan_resources; |
| 2597 | dev->device_issue_pending = d40_issue_pending; |
| 2598 | dev->device_tx_status = d40_tx_status; |
| 2599 | dev->device_control = d40_control; |
| 2600 | dev->dev = base->dev; |
| 2601 | } |
| 2602 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2603 | static int __init d40_dmaengine_init(struct d40_base *base, |
| 2604 | int num_reserved_chans) |
| 2605 | { |
| 2606 | int err ; |
| 2607 | |
| 2608 | d40_chan_init(base, &base->dma_slave, base->log_chans, |
| 2609 | 0, base->num_log_chans); |
| 2610 | |
| 2611 | dma_cap_zero(base->dma_slave.cap_mask); |
| 2612 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2613 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2614 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2615 | d40_ops_init(base, &base->dma_slave); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2616 | |
| 2617 | err = dma_async_device_register(&base->dma_slave); |
| 2618 | |
| 2619 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2620 | d40_err(base->dev, "Failed to register slave channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2621 | goto failure1; |
| 2622 | } |
| 2623 | |
| 2624 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, |
| 2625 | base->num_log_chans, base->plat_data->memcpy_len); |
| 2626 | |
| 2627 | dma_cap_zero(base->dma_memcpy.cap_mask); |
| 2628 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2629 | dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2630 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2631 | d40_ops_init(base, &base->dma_memcpy); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2632 | |
| 2633 | err = dma_async_device_register(&base->dma_memcpy); |
| 2634 | |
| 2635 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2636 | d40_err(base->dev, |
| 2637 | "Failed to regsiter memcpy only channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2638 | goto failure2; |
| 2639 | } |
| 2640 | |
| 2641 | d40_chan_init(base, &base->dma_both, base->phy_chans, |
| 2642 | 0, num_reserved_chans); |
| 2643 | |
| 2644 | dma_cap_zero(base->dma_both.cap_mask); |
| 2645 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); |
| 2646 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2647 | dma_cap_set(DMA_SG, base->dma_both.cap_mask); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2648 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2649 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2650 | d40_ops_init(base, &base->dma_both); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2651 | err = dma_async_device_register(&base->dma_both); |
| 2652 | |
| 2653 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2654 | d40_err(base->dev, |
| 2655 | "Failed to register logical and physical capable channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2656 | goto failure3; |
| 2657 | } |
| 2658 | return 0; |
| 2659 | failure3: |
| 2660 | dma_async_device_unregister(&base->dma_memcpy); |
| 2661 | failure2: |
| 2662 | dma_async_device_unregister(&base->dma_slave); |
| 2663 | failure1: |
| 2664 | return err; |
| 2665 | } |
| 2666 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2667 | /* Suspend resume functionality */ |
| 2668 | #ifdef CONFIG_PM |
| 2669 | static int dma40_pm_suspend(struct device *dev) |
| 2670 | { |
| 2671 | if (!pm_runtime_suspended(dev)) |
| 2672 | return -EBUSY; |
| 2673 | |
| 2674 | return 0; |
| 2675 | } |
| 2676 | |
| 2677 | static int dma40_runtime_suspend(struct device *dev) |
| 2678 | { |
| 2679 | struct platform_device *pdev = to_platform_device(dev); |
| 2680 | struct d40_base *base = platform_get_drvdata(pdev); |
| 2681 | |
| 2682 | d40_save_restore_registers(base, true); |
| 2683 | |
| 2684 | /* Don't disable/enable clocks for v1 due to HW bugs */ |
| 2685 | if (base->rev != 1) |
| 2686 | writel_relaxed(base->gcc_pwr_off_mask, |
| 2687 | base->virtbase + D40_DREG_GCC); |
| 2688 | |
| 2689 | return 0; |
| 2690 | } |
| 2691 | |
| 2692 | static int dma40_runtime_resume(struct device *dev) |
| 2693 | { |
| 2694 | struct platform_device *pdev = to_platform_device(dev); |
| 2695 | struct d40_base *base = platform_get_drvdata(pdev); |
| 2696 | |
| 2697 | if (base->initialized) |
| 2698 | d40_save_restore_registers(base, false); |
| 2699 | |
| 2700 | writel_relaxed(D40_DREG_GCC_ENABLE_ALL, |
| 2701 | base->virtbase + D40_DREG_GCC); |
| 2702 | return 0; |
| 2703 | } |
| 2704 | |
| 2705 | |
| 2706 | static const struct dev_pm_ops dma40_pm_ops = { |
| 2707 | .suspend = dma40_pm_suspend, |
| 2708 | .runtime_suspend = dma40_runtime_suspend, |
| 2709 | .runtime_resume = dma40_runtime_resume, |
| 2710 | }; |
| 2711 | #define DMA40_PM_OPS (&dma40_pm_ops) |
| 2712 | #else |
| 2713 | #define DMA40_PM_OPS NULL |
| 2714 | #endif |
| 2715 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2716 | /* Initialization functions. */ |
| 2717 | |
| 2718 | static int __init d40_phy_res_init(struct d40_base *base) |
| 2719 | { |
| 2720 | int i; |
| 2721 | int num_phy_chans_avail = 0; |
| 2722 | u32 val[2]; |
| 2723 | int odd_even_bit = -2; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2724 | int gcc = D40_DREG_GCC_ENA; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2725 | |
| 2726 | val[0] = readl(base->virtbase + D40_DREG_PRSME); |
| 2727 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); |
| 2728 | |
| 2729 | for (i = 0; i < base->num_phy_chans; i++) { |
| 2730 | base->phy_res[i].num = i; |
| 2731 | odd_even_bit += 2 * ((i % 2) == 0); |
| 2732 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { |
| 2733 | /* Mark security only channels as occupied */ |
| 2734 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; |
| 2735 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2736 | base->phy_res[i].reserved = true; |
| 2737 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), |
| 2738 | D40_DREG_GCC_SRC); |
| 2739 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), |
| 2740 | D40_DREG_GCC_DST); |
| 2741 | |
| 2742 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2743 | } else { |
| 2744 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; |
| 2745 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2746 | base->phy_res[i].reserved = false; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2747 | num_phy_chans_avail++; |
| 2748 | } |
| 2749 | spin_lock_init(&base->phy_res[i].lock); |
| 2750 | } |
Jonas Aaberg | 6b7acd8 | 2010-06-20 21:26:59 +0000 | [diff] [blame] | 2751 | |
| 2752 | /* Mark disabled channels as occupied */ |
| 2753 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { |
Rabin Vincent | f57b407 | 2010-10-06 08:20:35 +0000 | [diff] [blame] | 2754 | int chan = base->plat_data->disabled_channels[i]; |
| 2755 | |
| 2756 | base->phy_res[chan].allocated_src = D40_ALLOC_PHY; |
| 2757 | base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2758 | base->phy_res[chan].reserved = true; |
| 2759 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), |
| 2760 | D40_DREG_GCC_SRC); |
| 2761 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), |
| 2762 | D40_DREG_GCC_DST); |
Rabin Vincent | f57b407 | 2010-10-06 08:20:35 +0000 | [diff] [blame] | 2763 | num_phy_chans_avail--; |
Jonas Aaberg | 6b7acd8 | 2010-06-20 21:26:59 +0000 | [diff] [blame] | 2764 | } |
| 2765 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2766 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
| 2767 | num_phy_chans_avail, base->num_phy_chans); |
| 2768 | |
| 2769 | /* Verify settings extended vs standard */ |
| 2770 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); |
| 2771 | |
| 2772 | for (i = 0; i < base->num_phy_chans; i++) { |
| 2773 | |
| 2774 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && |
| 2775 | (val[0] & 0x3) != 1) |
| 2776 | dev_info(base->dev, |
| 2777 | "[%s] INFO: channel %d is misconfigured (%d)\n", |
| 2778 | __func__, i, val[0] & 0x3); |
| 2779 | |
| 2780 | val[0] = val[0] >> 2; |
| 2781 | } |
| 2782 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2783 | /* |
| 2784 | * To keep things simple, Enable all clocks initially. |
| 2785 | * The clocks will get managed later post channel allocation. |
| 2786 | * The clocks for the event lines on which reserved channels exists |
| 2787 | * are not managed here. |
| 2788 | */ |
| 2789 | writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); |
| 2790 | base->gcc_pwr_off_mask = gcc; |
| 2791 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2792 | return num_phy_chans_avail; |
| 2793 | } |
| 2794 | |
| 2795 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) |
| 2796 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2797 | struct stedma40_platform_data *plat_data; |
| 2798 | struct clk *clk = NULL; |
| 2799 | void __iomem *virtbase = NULL; |
| 2800 | struct resource *res = NULL; |
| 2801 | struct d40_base *base = NULL; |
| 2802 | int num_log_chans = 0; |
| 2803 | int num_phy_chans; |
| 2804 | int i; |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2805 | u32 pid; |
| 2806 | u32 cid; |
| 2807 | u8 rev; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2808 | |
| 2809 | clk = clk_get(&pdev->dev, NULL); |
| 2810 | |
| 2811 | if (IS_ERR(clk)) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2812 | d40_err(&pdev->dev, "No matching clock found\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2813 | goto failure; |
| 2814 | } |
| 2815 | |
| 2816 | clk_enable(clk); |
| 2817 | |
| 2818 | /* Get IO for DMAC base address */ |
| 2819 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); |
| 2820 | if (!res) |
| 2821 | goto failure; |
| 2822 | |
| 2823 | if (request_mem_region(res->start, resource_size(res), |
| 2824 | D40_NAME " I/O base") == NULL) |
| 2825 | goto failure; |
| 2826 | |
| 2827 | virtbase = ioremap(res->start, resource_size(res)); |
| 2828 | if (!virtbase) |
| 2829 | goto failure; |
| 2830 | |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2831 | /* This is just a regular AMBA PrimeCell ID actually */ |
| 2832 | for (pid = 0, i = 0; i < 4; i++) |
| 2833 | pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i) |
| 2834 | & 255) << (i * 8); |
| 2835 | for (cid = 0, i = 0; i < 4; i++) |
| 2836 | cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i) |
| 2837 | & 255) << (i * 8); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2838 | |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2839 | if (cid != AMBA_CID) { |
| 2840 | d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2841 | goto failure; |
| 2842 | } |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2843 | if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { |
| 2844 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
| 2845 | AMBA_MANF_BITS(pid), |
| 2846 | AMBA_VENDOR_ST); |
| 2847 | goto failure; |
| 2848 | } |
| 2849 | /* |
| 2850 | * HW revision: |
| 2851 | * DB8500ed has revision 0 |
| 2852 | * ? has revision 1 |
| 2853 | * DB8500v1 has revision 2 |
| 2854 | * DB8500v2 has revision 3 |
| 2855 | */ |
| 2856 | rev = AMBA_REV_BITS(pid); |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 2857 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2858 | /* The number of physical channels on this HW */ |
| 2859 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; |
| 2860 | |
| 2861 | dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 2862 | rev, res->start); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2863 | |
| 2864 | plat_data = pdev->dev.platform_data; |
| 2865 | |
| 2866 | /* Count the number of logical channels in use */ |
| 2867 | for (i = 0; i < plat_data->dev_len; i++) |
| 2868 | if (plat_data->dev_rx[i] != 0) |
| 2869 | num_log_chans++; |
| 2870 | |
| 2871 | for (i = 0; i < plat_data->dev_len; i++) |
| 2872 | if (plat_data->dev_tx[i] != 0) |
| 2873 | num_log_chans++; |
| 2874 | |
| 2875 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + |
| 2876 | (num_phy_chans + num_log_chans + plat_data->memcpy_len) * |
| 2877 | sizeof(struct d40_chan), GFP_KERNEL); |
| 2878 | |
| 2879 | if (base == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2880 | d40_err(&pdev->dev, "Out of memory\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2881 | goto failure; |
| 2882 | } |
| 2883 | |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 2884 | base->rev = rev; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2885 | base->clk = clk; |
| 2886 | base->num_phy_chans = num_phy_chans; |
| 2887 | base->num_log_chans = num_log_chans; |
| 2888 | base->phy_start = res->start; |
| 2889 | base->phy_size = resource_size(res); |
| 2890 | base->virtbase = virtbase; |
| 2891 | base->plat_data = plat_data; |
| 2892 | base->dev = &pdev->dev; |
| 2893 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); |
| 2894 | base->log_chans = &base->phy_chans[num_phy_chans]; |
| 2895 | |
| 2896 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), |
| 2897 | GFP_KERNEL); |
| 2898 | if (!base->phy_res) |
| 2899 | goto failure; |
| 2900 | |
| 2901 | base->lookup_phy_chans = kzalloc(num_phy_chans * |
| 2902 | sizeof(struct d40_chan *), |
| 2903 | GFP_KERNEL); |
| 2904 | if (!base->lookup_phy_chans) |
| 2905 | goto failure; |
| 2906 | |
| 2907 | if (num_log_chans + plat_data->memcpy_len) { |
| 2908 | /* |
| 2909 | * The max number of logical channels are event lines for all |
| 2910 | * src devices and dst devices |
| 2911 | */ |
| 2912 | base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * |
| 2913 | sizeof(struct d40_chan *), |
| 2914 | GFP_KERNEL); |
| 2915 | if (!base->lookup_log_chans) |
| 2916 | goto failure; |
| 2917 | } |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 2918 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2919 | base->reg_val_backup_chan = kmalloc(base->num_phy_chans * |
| 2920 | sizeof(d40_backup_regs_chan), |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2921 | GFP_KERNEL); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2922 | if (!base->reg_val_backup_chan) |
| 2923 | goto failure; |
| 2924 | |
| 2925 | base->lcla_pool.alloc_map = |
| 2926 | kzalloc(num_phy_chans * sizeof(struct d40_desc *) |
| 2927 | * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2928 | if (!base->lcla_pool.alloc_map) |
| 2929 | goto failure; |
| 2930 | |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 2931 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
| 2932 | 0, SLAB_HWCACHE_ALIGN, |
| 2933 | NULL); |
| 2934 | if (base->desc_slab == NULL) |
| 2935 | goto failure; |
| 2936 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2937 | return base; |
| 2938 | |
| 2939 | failure: |
Rabin Vincent | c6134c9 | 2010-10-06 08:20:36 +0000 | [diff] [blame] | 2940 | if (!IS_ERR(clk)) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2941 | clk_disable(clk); |
| 2942 | clk_put(clk); |
| 2943 | } |
| 2944 | if (virtbase) |
| 2945 | iounmap(virtbase); |
| 2946 | if (res) |
| 2947 | release_mem_region(res->start, |
| 2948 | resource_size(res)); |
| 2949 | if (virtbase) |
| 2950 | iounmap(virtbase); |
| 2951 | |
| 2952 | if (base) { |
| 2953 | kfree(base->lcla_pool.alloc_map); |
| 2954 | kfree(base->lookup_log_chans); |
| 2955 | kfree(base->lookup_phy_chans); |
| 2956 | kfree(base->phy_res); |
| 2957 | kfree(base); |
| 2958 | } |
| 2959 | |
| 2960 | return NULL; |
| 2961 | } |
| 2962 | |
| 2963 | static void __init d40_hw_init(struct d40_base *base) |
| 2964 | { |
| 2965 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2966 | static struct d40_reg_val dma_init_reg[] = { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2967 | /* Clock every part of the DMA block from start */ |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2968 | { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2969 | |
| 2970 | /* Interrupts on all logical channels */ |
| 2971 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, |
| 2972 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, |
| 2973 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, |
| 2974 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, |
| 2975 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, |
| 2976 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, |
| 2977 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, |
| 2978 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, |
| 2979 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, |
| 2980 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, |
| 2981 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, |
| 2982 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} |
| 2983 | }; |
| 2984 | int i; |
| 2985 | u32 prmseo[2] = {0, 0}; |
| 2986 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; |
| 2987 | u32 pcmis = 0; |
| 2988 | u32 pcicr = 0; |
| 2989 | |
| 2990 | for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++) |
| 2991 | writel(dma_init_reg[i].val, |
| 2992 | base->virtbase + dma_init_reg[i].reg); |
| 2993 | |
| 2994 | /* Configure all our dma channels to default settings */ |
| 2995 | for (i = 0; i < base->num_phy_chans; i++) { |
| 2996 | |
| 2997 | activeo[i % 2] = activeo[i % 2] << 2; |
| 2998 | |
| 2999 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src |
| 3000 | == D40_ALLOC_PHY) { |
| 3001 | activeo[i % 2] |= 3; |
| 3002 | continue; |
| 3003 | } |
| 3004 | |
| 3005 | /* Enable interrupt # */ |
| 3006 | pcmis = (pcmis << 1) | 1; |
| 3007 | |
| 3008 | /* Clear interrupt # */ |
| 3009 | pcicr = (pcicr << 1) | 1; |
| 3010 | |
| 3011 | /* Set channel to physical mode */ |
| 3012 | prmseo[i % 2] = prmseo[i % 2] << 2; |
| 3013 | prmseo[i % 2] |= 1; |
| 3014 | |
| 3015 | } |
| 3016 | |
| 3017 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); |
| 3018 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); |
| 3019 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); |
| 3020 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); |
| 3021 | |
| 3022 | /* Write which interrupt to enable */ |
| 3023 | writel(pcmis, base->virtbase + D40_DREG_PCMIS); |
| 3024 | |
| 3025 | /* Write which interrupt to clear */ |
| 3026 | writel(pcicr, base->virtbase + D40_DREG_PCICR); |
| 3027 | |
| 3028 | } |
| 3029 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3030 | static int __init d40_lcla_allocate(struct d40_base *base) |
| 3031 | { |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3032 | struct d40_lcla_pool *pool = &base->lcla_pool; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3033 | unsigned long *page_list; |
| 3034 | int i, j; |
| 3035 | int ret = 0; |
| 3036 | |
| 3037 | /* |
| 3038 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, |
| 3039 | * To full fill this hardware requirement without wasting 256 kb |
| 3040 | * we allocate pages until we get an aligned one. |
| 3041 | */ |
| 3042 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, |
| 3043 | GFP_KERNEL); |
| 3044 | |
| 3045 | if (!page_list) { |
| 3046 | ret = -ENOMEM; |
| 3047 | goto failure; |
| 3048 | } |
| 3049 | |
| 3050 | /* Calculating how many pages that are required */ |
| 3051 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; |
| 3052 | |
| 3053 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { |
| 3054 | page_list[i] = __get_free_pages(GFP_KERNEL, |
| 3055 | base->lcla_pool.pages); |
| 3056 | if (!page_list[i]) { |
| 3057 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3058 | d40_err(base->dev, "Failed to allocate %d pages.\n", |
| 3059 | base->lcla_pool.pages); |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3060 | |
| 3061 | for (j = 0; j < i; j++) |
| 3062 | free_pages(page_list[j], base->lcla_pool.pages); |
| 3063 | goto failure; |
| 3064 | } |
| 3065 | |
| 3066 | if ((virt_to_phys((void *)page_list[i]) & |
| 3067 | (LCLA_ALIGNMENT - 1)) == 0) |
| 3068 | break; |
| 3069 | } |
| 3070 | |
| 3071 | for (j = 0; j < i; j++) |
| 3072 | free_pages(page_list[j], base->lcla_pool.pages); |
| 3073 | |
| 3074 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { |
| 3075 | base->lcla_pool.base = (void *)page_list[i]; |
| 3076 | } else { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 3077 | /* |
| 3078 | * After many attempts and no succees with finding the correct |
| 3079 | * alignment, try with allocating a big buffer. |
| 3080 | */ |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3081 | dev_warn(base->dev, |
| 3082 | "[%s] Failed to get %d pages @ 18 bit align.\n", |
| 3083 | __func__, base->lcla_pool.pages); |
| 3084 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * |
| 3085 | base->num_phy_chans + |
| 3086 | LCLA_ALIGNMENT, |
| 3087 | GFP_KERNEL); |
| 3088 | if (!base->lcla_pool.base_unaligned) { |
| 3089 | ret = -ENOMEM; |
| 3090 | goto failure; |
| 3091 | } |
| 3092 | |
| 3093 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, |
| 3094 | LCLA_ALIGNMENT); |
| 3095 | } |
| 3096 | |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3097 | pool->dma_addr = dma_map_single(base->dev, pool->base, |
| 3098 | SZ_1K * base->num_phy_chans, |
| 3099 | DMA_TO_DEVICE); |
| 3100 | if (dma_mapping_error(base->dev, pool->dma_addr)) { |
| 3101 | pool->dma_addr = 0; |
| 3102 | ret = -ENOMEM; |
| 3103 | goto failure; |
| 3104 | } |
| 3105 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3106 | writel(virt_to_phys(base->lcla_pool.base), |
| 3107 | base->virtbase + D40_DREG_LCLA); |
| 3108 | failure: |
| 3109 | kfree(page_list); |
| 3110 | return ret; |
| 3111 | } |
| 3112 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3113 | static int __init d40_probe(struct platform_device *pdev) |
| 3114 | { |
| 3115 | int err; |
| 3116 | int ret = -ENOENT; |
| 3117 | struct d40_base *base; |
| 3118 | struct resource *res = NULL; |
| 3119 | int num_reserved_chans; |
| 3120 | u32 val; |
| 3121 | |
| 3122 | base = d40_hw_detect_init(pdev); |
| 3123 | |
| 3124 | if (!base) |
| 3125 | goto failure; |
| 3126 | |
| 3127 | num_reserved_chans = d40_phy_res_init(base); |
| 3128 | |
| 3129 | platform_set_drvdata(pdev, base); |
| 3130 | |
| 3131 | spin_lock_init(&base->interrupt_lock); |
| 3132 | spin_lock_init(&base->execmd_lock); |
| 3133 | |
| 3134 | /* Get IO for logical channel parameter address */ |
| 3135 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); |
| 3136 | if (!res) { |
| 3137 | ret = -ENOENT; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3138 | d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3139 | goto failure; |
| 3140 | } |
| 3141 | base->lcpa_size = resource_size(res); |
| 3142 | base->phy_lcpa = res->start; |
| 3143 | |
| 3144 | if (request_mem_region(res->start, resource_size(res), |
| 3145 | D40_NAME " I/O lcpa") == NULL) { |
| 3146 | ret = -EBUSY; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3147 | d40_err(&pdev->dev, |
| 3148 | "Failed to request LCPA region 0x%x-0x%x\n", |
| 3149 | res->start, res->end); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3150 | goto failure; |
| 3151 | } |
| 3152 | |
| 3153 | /* We make use of ESRAM memory for this. */ |
| 3154 | val = readl(base->virtbase + D40_DREG_LCPA); |
| 3155 | if (res->start != val && val != 0) { |
| 3156 | dev_warn(&pdev->dev, |
| 3157 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", |
| 3158 | __func__, val, res->start); |
| 3159 | } else |
| 3160 | writel(res->start, base->virtbase + D40_DREG_LCPA); |
| 3161 | |
| 3162 | base->lcpa_base = ioremap(res->start, resource_size(res)); |
| 3163 | if (!base->lcpa_base) { |
| 3164 | ret = -ENOMEM; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3165 | d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3166 | goto failure; |
| 3167 | } |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3168 | |
| 3169 | ret = d40_lcla_allocate(base); |
| 3170 | if (ret) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3171 | d40_err(&pdev->dev, "Failed to allocate LCLA area\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3172 | goto failure; |
| 3173 | } |
| 3174 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3175 | spin_lock_init(&base->lcla_pool.lock); |
| 3176 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3177 | base->irq = platform_get_irq(pdev, 0); |
| 3178 | |
| 3179 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3180 | if (ret) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3181 | d40_err(&pdev->dev, "No IRQ defined\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3182 | goto failure; |
| 3183 | } |
| 3184 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3185 | pm_runtime_irq_safe(base->dev); |
| 3186 | pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); |
| 3187 | pm_runtime_use_autosuspend(base->dev); |
| 3188 | pm_runtime_enable(base->dev); |
| 3189 | pm_runtime_resume(base->dev); |
| 3190 | base->initialized = true; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3191 | err = d40_dmaengine_init(base, num_reserved_chans); |
| 3192 | if (err) |
| 3193 | goto failure; |
| 3194 | |
| 3195 | d40_hw_init(base); |
| 3196 | |
| 3197 | dev_info(base->dev, "initialized\n"); |
| 3198 | return 0; |
| 3199 | |
| 3200 | failure: |
| 3201 | if (base) { |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 3202 | if (base->desc_slab) |
| 3203 | kmem_cache_destroy(base->desc_slab); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3204 | if (base->virtbase) |
| 3205 | iounmap(base->virtbase); |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3206 | |
| 3207 | if (base->lcla_pool.dma_addr) |
| 3208 | dma_unmap_single(base->dev, base->lcla_pool.dma_addr, |
| 3209 | SZ_1K * base->num_phy_chans, |
| 3210 | DMA_TO_DEVICE); |
| 3211 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3212 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
| 3213 | free_pages((unsigned long)base->lcla_pool.base, |
| 3214 | base->lcla_pool.pages); |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 3215 | |
| 3216 | kfree(base->lcla_pool.base_unaligned); |
| 3217 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3218 | if (base->phy_lcpa) |
| 3219 | release_mem_region(base->phy_lcpa, |
| 3220 | base->lcpa_size); |
| 3221 | if (base->phy_start) |
| 3222 | release_mem_region(base->phy_start, |
| 3223 | base->phy_size); |
| 3224 | if (base->clk) { |
| 3225 | clk_disable(base->clk); |
| 3226 | clk_put(base->clk); |
| 3227 | } |
| 3228 | |
| 3229 | kfree(base->lcla_pool.alloc_map); |
| 3230 | kfree(base->lookup_log_chans); |
| 3231 | kfree(base->lookup_phy_chans); |
| 3232 | kfree(base->phy_res); |
| 3233 | kfree(base); |
| 3234 | } |
| 3235 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3236 | d40_err(&pdev->dev, "probe failed\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3237 | return ret; |
| 3238 | } |
| 3239 | |
| 3240 | static struct platform_driver d40_driver = { |
| 3241 | .driver = { |
| 3242 | .owner = THIS_MODULE, |
| 3243 | .name = D40_NAME, |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3244 | .pm = DMA40_PM_OPS, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3245 | }, |
| 3246 | }; |
| 3247 | |
Rabin Vincent | cb9ab2d | 2011-01-25 11:18:04 +0100 | [diff] [blame] | 3248 | static int __init stedma40_init(void) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3249 | { |
| 3250 | return platform_driver_probe(&d40_driver, d40_probe); |
| 3251 | } |
Linus Walleij | a0eb221 | 2011-05-18 14:18:57 +0200 | [diff] [blame] | 3252 | subsys_initcall(stedma40_init); |