Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1 | #include <core/engine.h> |
| 2 | #include <core/device.h> |
| 3 | |
| 4 | #include <subdev/bios.h> |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 5 | #include <subdev/bios/bmp.h> |
| 6 | #include <subdev/bios/bit.h> |
Ben Skeggs | 1ed7316 | 2012-12-07 13:46:52 +1000 | [diff] [blame] | 7 | #include <subdev/bios/conn.h> |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 8 | #include <subdev/bios/dcb.h> |
| 9 | #include <subdev/bios/dp.h> |
Ben Skeggs | 1ed7316 | 2012-12-07 13:46:52 +1000 | [diff] [blame] | 10 | #include <subdev/bios/gpio.h> |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 11 | #include <subdev/bios/init.h> |
| 12 | #include <subdev/devinit.h> |
| 13 | #include <subdev/clock.h> |
| 14 | #include <subdev/i2c.h> |
| 15 | #include <subdev/vga.h> |
| 16 | #include <subdev/gpio.h> |
| 17 | |
| 18 | #define bioslog(lvl, fmt, args...) do { \ |
| 19 | nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \ |
| 20 | init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \ |
| 21 | } while(0) |
| 22 | #define cont(fmt, args...) do { \ |
| 23 | if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \ |
| 24 | printk(fmt, ##args); \ |
| 25 | } while(0) |
| 26 | #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) |
| 27 | #define warn(fmt, args...) bioslog(WARN, fmt, ##args) |
| 28 | #define error(fmt, args...) bioslog(ERROR, fmt, ##args) |
| 29 | |
| 30 | /****************************************************************************** |
| 31 | * init parser control flow helpers |
| 32 | *****************************************************************************/ |
| 33 | |
| 34 | static inline bool |
| 35 | init_exec(struct nvbios_init *init) |
| 36 | { |
| 37 | return (init->execute == 1) || ((init->execute & 5) == 5); |
| 38 | } |
| 39 | |
| 40 | static inline void |
| 41 | init_exec_set(struct nvbios_init *init, bool exec) |
| 42 | { |
| 43 | if (exec) init->execute &= 0xfd; |
| 44 | else init->execute |= 0x02; |
| 45 | } |
| 46 | |
| 47 | static inline void |
| 48 | init_exec_inv(struct nvbios_init *init) |
| 49 | { |
| 50 | init->execute ^= 0x02; |
| 51 | } |
| 52 | |
| 53 | static inline void |
| 54 | init_exec_force(struct nvbios_init *init, bool exec) |
| 55 | { |
| 56 | if (exec) init->execute |= 0x04; |
| 57 | else init->execute &= 0xfb; |
| 58 | } |
| 59 | |
| 60 | /****************************************************************************** |
| 61 | * init parser wrappers for normal register/i2c/whatever accessors |
| 62 | *****************************************************************************/ |
| 63 | |
| 64 | static inline int |
| 65 | init_or(struct nvbios_init *init) |
| 66 | { |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 67 | if (init_exec(init)) { |
| 68 | if (init->outp) |
| 69 | return ffs(init->outp->or) - 1; |
| 70 | error("script needs OR!!\n"); |
| 71 | } |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | static inline int |
| 76 | init_link(struct nvbios_init *init) |
| 77 | { |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 78 | if (init_exec(init)) { |
| 79 | if (init->outp) |
| 80 | return !(init->outp->sorconf.link & 1); |
| 81 | error("script needs OR link\n"); |
| 82 | } |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | static inline int |
| 87 | init_crtc(struct nvbios_init *init) |
| 88 | { |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 89 | if (init_exec(init)) { |
| 90 | if (init->crtc >= 0) |
| 91 | return init->crtc; |
| 92 | error("script needs crtc\n"); |
| 93 | } |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | static u8 |
| 98 | init_conn(struct nvbios_init *init) |
| 99 | { |
| 100 | struct nouveau_bios *bios = init->bios; |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 101 | u8 ver, len; |
| 102 | u16 conn; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 103 | |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 104 | if (init_exec(init)) { |
| 105 | if (init->outp) { |
| 106 | conn = init->outp->connector; |
| 107 | conn = dcb_conn(bios, conn, &ver, &len); |
| 108 | if (conn) |
| 109 | return nv_ro08(bios, conn); |
| 110 | } |
| 111 | |
| 112 | error("script needs connector type\n"); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 113 | } |
| 114 | |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 115 | return 0xff; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | static inline u32 |
| 119 | init_nvreg(struct nvbios_init *init, u32 reg) |
| 120 | { |
| 121 | /* C51 (at least) sometimes has the lower bits set which the VBIOS |
| 122 | * interprets to mean that access needs to go through certain IO |
| 123 | * ports instead. The NVIDIA binary driver has been seen to access |
| 124 | * these through the NV register address, so lets assume we can |
| 125 | * do the same |
| 126 | */ |
| 127 | reg &= ~0x00000003; |
| 128 | |
| 129 | /* GF8+ display scripts need register addresses mangled a bit to |
| 130 | * select a specific CRTC/OR |
| 131 | */ |
| 132 | if (nv_device(init->bios)->card_type >= NV_50) { |
| 133 | if (reg & 0x80000000) { |
| 134 | reg += init_crtc(init) * 0x800; |
| 135 | reg &= ~0x80000000; |
| 136 | } |
| 137 | |
| 138 | if (reg & 0x40000000) { |
| 139 | reg += init_or(init) * 0x800; |
| 140 | reg &= ~0x40000000; |
| 141 | if (reg & 0x20000000) { |
| 142 | reg += init_link(init) * 0x80; |
| 143 | reg &= ~0x20000000; |
| 144 | } |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | if (reg & ~0x00fffffc) |
| 149 | warn("unknown bits in register 0x%08x\n", reg); |
| 150 | return reg; |
| 151 | } |
| 152 | |
| 153 | static u32 |
| 154 | init_rd32(struct nvbios_init *init, u32 reg) |
| 155 | { |
| 156 | reg = init_nvreg(init, reg); |
| 157 | if (init_exec(init)) |
| 158 | return nv_rd32(init->subdev, reg); |
| 159 | return 0x00000000; |
| 160 | } |
| 161 | |
| 162 | static void |
| 163 | init_wr32(struct nvbios_init *init, u32 reg, u32 val) |
| 164 | { |
| 165 | reg = init_nvreg(init, reg); |
| 166 | if (init_exec(init)) |
| 167 | nv_wr32(init->subdev, reg, val); |
| 168 | } |
| 169 | |
| 170 | static u32 |
| 171 | init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) |
| 172 | { |
| 173 | reg = init_nvreg(init, reg); |
| 174 | if (init_exec(init)) { |
| 175 | u32 tmp = nv_rd32(init->subdev, reg); |
| 176 | nv_wr32(init->subdev, reg, (tmp & ~mask) | val); |
| 177 | return tmp; |
| 178 | } |
| 179 | return 0x00000000; |
| 180 | } |
| 181 | |
| 182 | static u8 |
| 183 | init_rdport(struct nvbios_init *init, u16 port) |
| 184 | { |
| 185 | if (init_exec(init)) |
| 186 | return nv_rdport(init->subdev, init->crtc, port); |
| 187 | return 0x00; |
| 188 | } |
| 189 | |
| 190 | static void |
| 191 | init_wrport(struct nvbios_init *init, u16 port, u8 value) |
| 192 | { |
| 193 | if (init_exec(init)) |
| 194 | nv_wrport(init->subdev, init->crtc, port, value); |
| 195 | } |
| 196 | |
| 197 | static u8 |
| 198 | init_rdvgai(struct nvbios_init *init, u16 port, u8 index) |
| 199 | { |
| 200 | struct nouveau_subdev *subdev = init->subdev; |
| 201 | if (init_exec(init)) { |
| 202 | int head = init->crtc < 0 ? 0 : init->crtc; |
| 203 | return nv_rdvgai(subdev, head, port, index); |
| 204 | } |
| 205 | return 0x00; |
| 206 | } |
| 207 | |
| 208 | static void |
| 209 | init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) |
| 210 | { |
| 211 | /* force head 0 for updates to cr44, it only exists on first head */ |
| 212 | if (nv_device(init->subdev)->card_type < NV_50) { |
| 213 | if (port == 0x03d4 && index == 0x44) |
| 214 | init->crtc = 0; |
| 215 | } |
| 216 | |
| 217 | if (init_exec(init)) { |
| 218 | int head = init->crtc < 0 ? 0 : init->crtc; |
| 219 | nv_wrvgai(init->subdev, head, port, index, value); |
| 220 | } |
| 221 | |
| 222 | /* select head 1 if cr44 write selected it */ |
| 223 | if (nv_device(init->subdev)->card_type < NV_50) { |
| 224 | if (port == 0x03d4 && index == 0x44 && value == 3) |
| 225 | init->crtc = 1; |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | static struct nouveau_i2c_port * |
| 230 | init_i2c(struct nvbios_init *init, int index) |
| 231 | { |
| 232 | struct nouveau_i2c *i2c = nouveau_i2c(init->bios); |
| 233 | |
| 234 | if (index == 0xff) { |
| 235 | index = NV_I2C_DEFAULT(0); |
| 236 | if (init->outp && init->outp->i2c_upper_default) |
| 237 | index = NV_I2C_DEFAULT(1); |
| 238 | } else |
| 239 | if (index < 0) { |
| 240 | if (!init->outp) { |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 241 | if (init_exec(init)) |
| 242 | error("script needs output for i2c\n"); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 243 | return NULL; |
| 244 | } |
| 245 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 246 | if (index == -2 && init->outp->location) { |
| 247 | index = NV_I2C_TYPE_EXTAUX(init->outp->extdev); |
| 248 | return i2c->find_type(i2c, index); |
| 249 | } |
| 250 | |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 251 | index = init->outp->i2c_index; |
| 252 | } |
| 253 | |
| 254 | return i2c->find(i2c, index); |
| 255 | } |
| 256 | |
| 257 | static int |
| 258 | init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) |
| 259 | { |
| 260 | struct nouveau_i2c_port *port = init_i2c(init, index); |
| 261 | if (port && init_exec(init)) |
| 262 | return nv_rdi2cr(port, addr, reg); |
| 263 | return -ENODEV; |
| 264 | } |
| 265 | |
| 266 | static int |
| 267 | init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) |
| 268 | { |
| 269 | struct nouveau_i2c_port *port = init_i2c(init, index); |
| 270 | if (port && init_exec(init)) |
| 271 | return nv_wri2cr(port, addr, reg, val); |
| 272 | return -ENODEV; |
| 273 | } |
| 274 | |
| 275 | static int |
| 276 | init_rdauxr(struct nvbios_init *init, u32 addr) |
| 277 | { |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 278 | struct nouveau_i2c_port *port = init_i2c(init, -2); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 279 | u8 data; |
| 280 | |
| 281 | if (port && init_exec(init)) { |
| 282 | int ret = nv_rdaux(port, addr, &data, 1); |
| 283 | if (ret) |
| 284 | return ret; |
| 285 | return data; |
| 286 | } |
| 287 | |
| 288 | return -ENODEV; |
| 289 | } |
| 290 | |
| 291 | static int |
| 292 | init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) |
| 293 | { |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 294 | struct nouveau_i2c_port *port = init_i2c(init, -2); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 295 | if (port && init_exec(init)) |
| 296 | return nv_wraux(port, addr, &data, 1); |
| 297 | return -ENODEV; |
| 298 | } |
| 299 | |
| 300 | static void |
| 301 | init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) |
| 302 | { |
| 303 | struct nouveau_clock *clk = nouveau_clock(init->bios); |
| 304 | if (clk && clk->pll_set && init_exec(init)) { |
| 305 | int ret = clk->pll_set(clk, id, freq); |
| 306 | if (ret) |
| 307 | warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | /****************************************************************************** |
| 312 | * parsing of bios structures that are required to execute init tables |
| 313 | *****************************************************************************/ |
| 314 | |
| 315 | static u16 |
| 316 | init_table(struct nouveau_bios *bios, u16 *len) |
| 317 | { |
| 318 | struct bit_entry bit_I; |
| 319 | |
| 320 | if (!bit_entry(bios, 'I', &bit_I)) { |
| 321 | *len = bit_I.length; |
| 322 | return bit_I.offset; |
| 323 | } |
| 324 | |
| 325 | if (bmp_version(bios) >= 0x0510) { |
| 326 | *len = 14; |
| 327 | return bios->bmp_offset + 75; |
| 328 | } |
| 329 | |
| 330 | return 0x0000; |
| 331 | } |
| 332 | |
| 333 | static u16 |
| 334 | init_table_(struct nvbios_init *init, u16 offset, const char *name) |
| 335 | { |
| 336 | struct nouveau_bios *bios = init->bios; |
| 337 | u16 len, data = init_table(bios, &len); |
| 338 | if (data) { |
| 339 | if (len >= offset + 2) { |
| 340 | data = nv_ro16(bios, data + offset); |
| 341 | if (data) |
| 342 | return data; |
| 343 | |
| 344 | warn("%s pointer invalid\n", name); |
| 345 | return 0x0000; |
| 346 | } |
| 347 | |
| 348 | warn("init data too short for %s pointer", name); |
| 349 | return 0x0000; |
| 350 | } |
| 351 | |
| 352 | warn("init data not found\n"); |
| 353 | return 0x0000; |
| 354 | } |
| 355 | |
| 356 | #define init_script_table(b) init_table_((b), 0x00, "script table") |
| 357 | #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") |
| 358 | #define init_macro_table(b) init_table_((b), 0x04, "macro table") |
| 359 | #define init_condition_table(b) init_table_((b), 0x06, "condition table") |
| 360 | #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") |
| 361 | #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") |
| 362 | #define init_function_table(b) init_table_((b), 0x0c, "function table") |
| 363 | #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); |
| 364 | |
| 365 | static u16 |
| 366 | init_script(struct nouveau_bios *bios, int index) |
| 367 | { |
| 368 | struct nvbios_init init = { .bios = bios }; |
| 369 | u16 data; |
| 370 | |
| 371 | if (bmp_version(bios) && bmp_version(bios) < 0x0510) { |
| 372 | if (index > 1) |
| 373 | return 0x0000; |
| 374 | |
| 375 | data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18); |
| 376 | return nv_ro16(bios, data + (index * 2)); |
| 377 | } |
| 378 | |
| 379 | data = init_script_table(&init); |
| 380 | if (data) |
| 381 | return nv_ro16(bios, data + (index * 2)); |
| 382 | |
| 383 | return 0x0000; |
| 384 | } |
| 385 | |
| 386 | static u16 |
| 387 | init_unknown_script(struct nouveau_bios *bios) |
| 388 | { |
| 389 | u16 len, data = init_table(bios, &len); |
| 390 | if (data && len >= 16) |
| 391 | return nv_ro16(bios, data + 14); |
| 392 | return 0x0000; |
| 393 | } |
| 394 | |
| 395 | static u16 |
| 396 | init_ram_restrict_table(struct nvbios_init *init) |
| 397 | { |
| 398 | struct nouveau_bios *bios = init->bios; |
| 399 | struct bit_entry bit_M; |
| 400 | u16 data = 0x0000; |
| 401 | |
| 402 | if (!bit_entry(bios, 'M', &bit_M)) { |
| 403 | if (bit_M.version == 1 && bit_M.length >= 5) |
| 404 | data = nv_ro16(bios, bit_M.offset + 3); |
| 405 | if (bit_M.version == 2 && bit_M.length >= 3) |
| 406 | data = nv_ro16(bios, bit_M.offset + 1); |
| 407 | } |
| 408 | |
| 409 | if (data == 0x0000) |
| 410 | warn("ram restrict table not found\n"); |
| 411 | return data; |
| 412 | } |
| 413 | |
| 414 | static u8 |
| 415 | init_ram_restrict_group_count(struct nvbios_init *init) |
| 416 | { |
| 417 | struct nouveau_bios *bios = init->bios; |
| 418 | struct bit_entry bit_M; |
| 419 | |
| 420 | if (!bit_entry(bios, 'M', &bit_M)) { |
| 421 | if (bit_M.version == 1 && bit_M.length >= 5) |
| 422 | return nv_ro08(bios, bit_M.offset + 2); |
| 423 | if (bit_M.version == 2 && bit_M.length >= 3) |
| 424 | return nv_ro08(bios, bit_M.offset + 0); |
| 425 | } |
| 426 | |
| 427 | return 0x00; |
| 428 | } |
| 429 | |
| 430 | static u8 |
Ben Skeggs | 5ddf4d4 | 2012-12-20 07:48:51 +1000 | [diff] [blame] | 431 | init_ram_restrict_strap(struct nvbios_init *init) |
| 432 | { |
| 433 | /* This appears to be the behaviour of the VBIOS parser, and *is* |
| 434 | * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to |
| 435 | * avoid fucking up the memory controller (somehow) by reading it |
| 436 | * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. |
| 437 | * |
| 438 | * Preserving the non-caching behaviour on earlier chipsets just |
| 439 | * in case *not* re-reading the strap causes similar breakage. |
| 440 | */ |
| 441 | if (!init->ramcfg || init->bios->version.major < 0x70) |
| 442 | init->ramcfg = init_rd32(init, 0x101000); |
| 443 | return (init->ramcfg & 0x00000003c) >> 2; |
| 444 | } |
| 445 | |
| 446 | static u8 |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 447 | init_ram_restrict(struct nvbios_init *init) |
| 448 | { |
Ben Skeggs | 5ddf4d4 | 2012-12-20 07:48:51 +1000 | [diff] [blame] | 449 | u8 strap = init_ram_restrict_strap(init); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 450 | u16 table = init_ram_restrict_table(init); |
| 451 | if (table) |
| 452 | return nv_ro08(init->bios, table + strap); |
| 453 | return 0x00; |
| 454 | } |
| 455 | |
| 456 | static u8 |
| 457 | init_xlat_(struct nvbios_init *init, u8 index, u8 offset) |
| 458 | { |
| 459 | struct nouveau_bios *bios = init->bios; |
| 460 | u16 table = init_xlat_table(init); |
| 461 | if (table) { |
| 462 | u16 data = nv_ro16(bios, table + (index * 2)); |
| 463 | if (data) |
| 464 | return nv_ro08(bios, data + offset); |
| 465 | warn("xlat table pointer %d invalid\n", index); |
| 466 | } |
| 467 | return 0x00; |
| 468 | } |
| 469 | |
| 470 | /****************************************************************************** |
| 471 | * utility functions used by various init opcode handlers |
| 472 | *****************************************************************************/ |
| 473 | |
| 474 | static bool |
| 475 | init_condition_met(struct nvbios_init *init, u8 cond) |
| 476 | { |
| 477 | struct nouveau_bios *bios = init->bios; |
| 478 | u16 table = init_condition_table(init); |
| 479 | if (table) { |
| 480 | u32 reg = nv_ro32(bios, table + (cond * 12) + 0); |
| 481 | u32 msk = nv_ro32(bios, table + (cond * 12) + 4); |
| 482 | u32 val = nv_ro32(bios, table + (cond * 12) + 8); |
| 483 | trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", |
| 484 | cond, reg, msk, val); |
| 485 | return (init_rd32(init, reg) & msk) == val; |
| 486 | } |
| 487 | return false; |
| 488 | } |
| 489 | |
| 490 | static bool |
| 491 | init_io_condition_met(struct nvbios_init *init, u8 cond) |
| 492 | { |
| 493 | struct nouveau_bios *bios = init->bios; |
| 494 | u16 table = init_io_condition_table(init); |
| 495 | if (table) { |
| 496 | u16 port = nv_ro16(bios, table + (cond * 5) + 0); |
| 497 | u8 index = nv_ro08(bios, table + (cond * 5) + 2); |
| 498 | u8 mask = nv_ro08(bios, table + (cond * 5) + 3); |
| 499 | u8 value = nv_ro08(bios, table + (cond * 5) + 4); |
| 500 | trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", |
| 501 | cond, port, index, mask, value); |
| 502 | return (init_rdvgai(init, port, index) & mask) == value; |
| 503 | } |
| 504 | return false; |
| 505 | } |
| 506 | |
| 507 | static bool |
| 508 | init_io_flag_condition_met(struct nvbios_init *init, u8 cond) |
| 509 | { |
| 510 | struct nouveau_bios *bios = init->bios; |
| 511 | u16 table = init_io_flag_condition_table(init); |
| 512 | if (table) { |
| 513 | u16 port = nv_ro16(bios, table + (cond * 9) + 0); |
| 514 | u8 index = nv_ro08(bios, table + (cond * 9) + 2); |
| 515 | u8 mask = nv_ro08(bios, table + (cond * 9) + 3); |
| 516 | u8 shift = nv_ro08(bios, table + (cond * 9) + 4); |
| 517 | u16 data = nv_ro16(bios, table + (cond * 9) + 5); |
| 518 | u8 dmask = nv_ro08(bios, table + (cond * 9) + 7); |
| 519 | u8 value = nv_ro08(bios, table + (cond * 9) + 8); |
| 520 | u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; |
| 521 | return (nv_ro08(bios, data + ioval) & dmask) == value; |
| 522 | } |
| 523 | return false; |
| 524 | } |
| 525 | |
| 526 | static inline u32 |
| 527 | init_shift(u32 data, u8 shift) |
| 528 | { |
| 529 | if (shift < 0x80) |
| 530 | return data >> shift; |
| 531 | return data << (0x100 - shift); |
| 532 | } |
| 533 | |
| 534 | static u32 |
| 535 | init_tmds_reg(struct nvbios_init *init, u8 tmds) |
| 536 | { |
| 537 | /* For mlv < 0x80, it is an index into a table of TMDS base addresses. |
| 538 | * For mlv == 0x80 use the "or" value of the dcb_entry indexed by |
| 539 | * CR58 for CR57 = 0 to index a table of offsets to the basic |
| 540 | * 0x6808b0 address. |
| 541 | * For mlv == 0x81 use the "or" value of the dcb_entry indexed by |
| 542 | * CR58 for CR57 = 0 to index a table of offsets to the basic |
| 543 | * 0x6808b0 address, and then flip the offset by 8. |
| 544 | */ |
| 545 | |
| 546 | const int pramdac_offset[13] = { |
| 547 | 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; |
| 548 | const u32 pramdac_table[4] = { |
| 549 | 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; |
| 550 | |
| 551 | if (tmds >= 0x80) { |
| 552 | if (init->outp) { |
| 553 | u32 dacoffset = pramdac_offset[init->outp->or]; |
| 554 | if (tmds == 0x81) |
| 555 | dacoffset ^= 8; |
| 556 | return 0x6808b0 + dacoffset; |
| 557 | } |
| 558 | |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 559 | if (init_exec(init)) |
| 560 | error("tmds opcodes need dcb\n"); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 561 | } else { |
| 562 | if (tmds < ARRAY_SIZE(pramdac_table)) |
| 563 | return pramdac_table[tmds]; |
| 564 | |
| 565 | error("tmds selector 0x%02x unknown\n", tmds); |
| 566 | } |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | /****************************************************************************** |
| 572 | * init opcode handlers |
| 573 | *****************************************************************************/ |
| 574 | |
| 575 | /** |
| 576 | * init_reserved - stub for various unknown/unused single-byte opcodes |
| 577 | * |
| 578 | */ |
| 579 | static void |
| 580 | init_reserved(struct nvbios_init *init) |
| 581 | { |
| 582 | u8 opcode = nv_ro08(init->bios, init->offset); |
| 583 | trace("RESERVED\t0x%02x\n", opcode); |
| 584 | init->offset += 1; |
| 585 | } |
| 586 | |
| 587 | /** |
| 588 | * INIT_DONE - opcode 0x71 |
| 589 | * |
| 590 | */ |
| 591 | static void |
| 592 | init_done(struct nvbios_init *init) |
| 593 | { |
| 594 | trace("DONE\n"); |
| 595 | init->offset = 0x0000; |
| 596 | } |
| 597 | |
| 598 | /** |
| 599 | * INIT_IO_RESTRICT_PROG - opcode 0x32 |
| 600 | * |
| 601 | */ |
| 602 | static void |
| 603 | init_io_restrict_prog(struct nvbios_init *init) |
| 604 | { |
| 605 | struct nouveau_bios *bios = init->bios; |
| 606 | u16 port = nv_ro16(bios, init->offset + 1); |
| 607 | u8 index = nv_ro08(bios, init->offset + 3); |
| 608 | u8 mask = nv_ro08(bios, init->offset + 4); |
| 609 | u8 shift = nv_ro08(bios, init->offset + 5); |
| 610 | u8 count = nv_ro08(bios, init->offset + 6); |
| 611 | u32 reg = nv_ro32(bios, init->offset + 7); |
| 612 | u8 conf, i; |
| 613 | |
| 614 | trace("IO_RESTRICT_PROG\tR[0x%06x] = " |
| 615 | "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", |
| 616 | reg, port, index, mask, shift); |
| 617 | init->offset += 11; |
| 618 | |
| 619 | conf = (init_rdvgai(init, port, index) & mask) >> shift; |
| 620 | for (i = 0; i < count; i++) { |
| 621 | u32 data = nv_ro32(bios, init->offset); |
| 622 | |
| 623 | if (i == conf) { |
| 624 | trace("\t0x%08x *\n", data); |
| 625 | init_wr32(init, reg, data); |
| 626 | } else { |
| 627 | trace("\t0x%08x\n", data); |
| 628 | } |
| 629 | |
| 630 | init->offset += 4; |
| 631 | } |
| 632 | trace("}]\n"); |
| 633 | } |
| 634 | |
| 635 | /** |
| 636 | * INIT_REPEAT - opcode 0x33 |
| 637 | * |
| 638 | */ |
| 639 | static void |
| 640 | init_repeat(struct nvbios_init *init) |
| 641 | { |
| 642 | struct nouveau_bios *bios = init->bios; |
| 643 | u8 count = nv_ro08(bios, init->offset + 1); |
| 644 | u16 repeat = init->repeat; |
| 645 | |
| 646 | trace("REPEAT\t0x%02x\n", count); |
| 647 | init->offset += 2; |
| 648 | |
| 649 | init->repeat = init->offset; |
| 650 | init->repend = init->offset; |
| 651 | while (count--) { |
| 652 | init->offset = init->repeat; |
| 653 | nvbios_exec(init); |
| 654 | if (count) |
| 655 | trace("REPEAT\t0x%02x\n", count); |
| 656 | } |
| 657 | init->offset = init->repend; |
| 658 | init->repeat = repeat; |
| 659 | } |
| 660 | |
| 661 | /** |
| 662 | * INIT_IO_RESTRICT_PLL - opcode 0x34 |
| 663 | * |
| 664 | */ |
| 665 | static void |
| 666 | init_io_restrict_pll(struct nvbios_init *init) |
| 667 | { |
| 668 | struct nouveau_bios *bios = init->bios; |
| 669 | u16 port = nv_ro16(bios, init->offset + 1); |
| 670 | u8 index = nv_ro08(bios, init->offset + 3); |
| 671 | u8 mask = nv_ro08(bios, init->offset + 4); |
| 672 | u8 shift = nv_ro08(bios, init->offset + 5); |
| 673 | s8 iofc = nv_ro08(bios, init->offset + 6); |
| 674 | u8 count = nv_ro08(bios, init->offset + 7); |
| 675 | u32 reg = nv_ro32(bios, init->offset + 8); |
| 676 | u8 conf, i; |
| 677 | |
| 678 | trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " |
| 679 | "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", |
| 680 | reg, port, index, mask, shift, iofc); |
| 681 | init->offset += 12; |
| 682 | |
| 683 | conf = (init_rdvgai(init, port, index) & mask) >> shift; |
| 684 | for (i = 0; i < count; i++) { |
| 685 | u32 freq = nv_ro16(bios, init->offset) * 10; |
| 686 | |
| 687 | if (i == conf) { |
| 688 | trace("\t%dkHz *\n", freq); |
| 689 | if (iofc > 0 && init_io_flag_condition_met(init, iofc)) |
| 690 | freq *= 2; |
| 691 | init_prog_pll(init, reg, freq); |
| 692 | } else { |
| 693 | trace("\t%dkHz\n", freq); |
| 694 | } |
| 695 | |
| 696 | init->offset += 2; |
| 697 | } |
| 698 | trace("}]\n"); |
| 699 | } |
| 700 | |
| 701 | /** |
| 702 | * INIT_END_REPEAT - opcode 0x36 |
| 703 | * |
| 704 | */ |
| 705 | static void |
| 706 | init_end_repeat(struct nvbios_init *init) |
| 707 | { |
| 708 | trace("END_REPEAT\n"); |
| 709 | init->offset += 1; |
| 710 | |
| 711 | if (init->repeat) { |
| 712 | init->repend = init->offset; |
| 713 | init->offset = 0; |
| 714 | } |
| 715 | } |
| 716 | |
| 717 | /** |
| 718 | * INIT_COPY - opcode 0x37 |
| 719 | * |
| 720 | */ |
| 721 | static void |
| 722 | init_copy(struct nvbios_init *init) |
| 723 | { |
| 724 | struct nouveau_bios *bios = init->bios; |
| 725 | u32 reg = nv_ro32(bios, init->offset + 1); |
| 726 | u8 shift = nv_ro08(bios, init->offset + 5); |
| 727 | u8 smask = nv_ro08(bios, init->offset + 6); |
| 728 | u16 port = nv_ro16(bios, init->offset + 7); |
| 729 | u8 index = nv_ro08(bios, init->offset + 9); |
| 730 | u8 mask = nv_ro08(bios, init->offset + 10); |
| 731 | u8 data; |
| 732 | |
| 733 | trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " |
| 734 | "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", |
| 735 | port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", |
| 736 | (shift & 0x80) ? (0x100 - shift) : shift, smask); |
| 737 | init->offset += 11; |
| 738 | |
| 739 | data = init_rdvgai(init, port, index) & mask; |
| 740 | data |= init_shift(init_rd32(init, reg), shift) & smask; |
| 741 | init_wrvgai(init, port, index, data); |
| 742 | } |
| 743 | |
| 744 | /** |
| 745 | * INIT_NOT - opcode 0x38 |
| 746 | * |
| 747 | */ |
| 748 | static void |
| 749 | init_not(struct nvbios_init *init) |
| 750 | { |
| 751 | trace("NOT\n"); |
| 752 | init->offset += 1; |
| 753 | init_exec_inv(init); |
| 754 | } |
| 755 | |
| 756 | /** |
| 757 | * INIT_IO_FLAG_CONDITION - opcode 0x39 |
| 758 | * |
| 759 | */ |
| 760 | static void |
| 761 | init_io_flag_condition(struct nvbios_init *init) |
| 762 | { |
| 763 | struct nouveau_bios *bios = init->bios; |
| 764 | u8 cond = nv_ro08(bios, init->offset + 1); |
| 765 | |
| 766 | trace("IO_FLAG_CONDITION\t0x%02x\n", cond); |
| 767 | init->offset += 2; |
| 768 | |
| 769 | if (!init_io_flag_condition_met(init, cond)) |
| 770 | init_exec_set(init, false); |
| 771 | } |
| 772 | |
| 773 | /** |
| 774 | * INIT_DP_CONDITION - opcode 0x3a |
| 775 | * |
| 776 | */ |
| 777 | static void |
| 778 | init_dp_condition(struct nvbios_init *init) |
| 779 | { |
| 780 | struct nouveau_bios *bios = init->bios; |
Ben Skeggs | 65c7866 | 2012-11-06 16:03:51 +1000 | [diff] [blame] | 781 | struct nvbios_dpout info; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 782 | u8 cond = nv_ro08(bios, init->offset + 1); |
| 783 | u8 unkn = nv_ro08(bios, init->offset + 2); |
Ben Skeggs | 65c7866 | 2012-11-06 16:03:51 +1000 | [diff] [blame] | 784 | u8 ver, hdr, cnt, len; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 785 | u16 data; |
| 786 | |
| 787 | trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn); |
| 788 | init->offset += 3; |
| 789 | |
| 790 | switch (cond) { |
| 791 | case 0: |
| 792 | if (init_conn(init) != DCB_CONNECTOR_eDP) |
| 793 | init_exec_set(init, false); |
| 794 | break; |
| 795 | case 1: |
| 796 | case 2: |
| 797 | if ( init->outp && |
Ben Skeggs | 65c7866 | 2012-11-06 16:03:51 +1000 | [diff] [blame] | 798 | (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, |
| 799 | (init->outp->or << 0) | |
| 800 | (init->outp->sorconf.link << 6), |
| 801 | &ver, &hdr, &cnt, &len, &info))) |
| 802 | { |
| 803 | if (!(info.flags & cond)) |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 804 | init_exec_set(init, false); |
| 805 | break; |
| 806 | } |
| 807 | |
Ben Skeggs | 28ec70f | 2013-04-15 14:47:05 +1000 | [diff] [blame^] | 808 | if (init_exec(init)) |
| 809 | warn("script needs dp output table data\n"); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 810 | break; |
| 811 | case 5: |
| 812 | if (!(init_rdauxr(init, 0x0d) & 1)) |
| 813 | init_exec_set(init, false); |
| 814 | break; |
| 815 | default: |
| 816 | warn("unknown dp condition 0x%02x\n", cond); |
| 817 | break; |
| 818 | } |
| 819 | } |
| 820 | |
| 821 | /** |
| 822 | * INIT_IO_MASK_OR - opcode 0x3b |
| 823 | * |
| 824 | */ |
| 825 | static void |
| 826 | init_io_mask_or(struct nvbios_init *init) |
| 827 | { |
| 828 | struct nouveau_bios *bios = init->bios; |
| 829 | u8 index = nv_ro08(bios, init->offset + 1); |
| 830 | u8 or = init_or(init); |
| 831 | u8 data; |
| 832 | |
| 833 | trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)", index, or); |
| 834 | init->offset += 2; |
| 835 | |
| 836 | data = init_rdvgai(init, 0x03d4, index); |
| 837 | init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); |
| 838 | } |
| 839 | |
| 840 | /** |
| 841 | * INIT_IO_OR - opcode 0x3c |
| 842 | * |
| 843 | */ |
| 844 | static void |
| 845 | init_io_or(struct nvbios_init *init) |
| 846 | { |
| 847 | struct nouveau_bios *bios = init->bios; |
| 848 | u8 index = nv_ro08(bios, init->offset + 1); |
| 849 | u8 or = init_or(init); |
| 850 | u8 data; |
| 851 | |
| 852 | trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)", index, or); |
| 853 | init->offset += 2; |
| 854 | |
| 855 | data = init_rdvgai(init, 0x03d4, index); |
| 856 | init_wrvgai(init, 0x03d4, index, data | (1 << or)); |
| 857 | } |
| 858 | |
| 859 | /** |
| 860 | * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 |
| 861 | * |
| 862 | */ |
| 863 | static void |
| 864 | init_idx_addr_latched(struct nvbios_init *init) |
| 865 | { |
| 866 | struct nouveau_bios *bios = init->bios; |
| 867 | u32 creg = nv_ro32(bios, init->offset + 1); |
| 868 | u32 dreg = nv_ro32(bios, init->offset + 5); |
| 869 | u32 mask = nv_ro32(bios, init->offset + 9); |
| 870 | u32 data = nv_ro32(bios, init->offset + 13); |
| 871 | u8 count = nv_ro08(bios, init->offset + 17); |
| 872 | |
| 873 | trace("INDEX_ADDRESS_LATCHED\t" |
| 874 | "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n", |
| 875 | creg, dreg, mask, data); |
| 876 | init->offset += 18; |
| 877 | |
| 878 | while (count--) { |
| 879 | u8 iaddr = nv_ro08(bios, init->offset + 0); |
| 880 | u8 idata = nv_ro08(bios, init->offset + 1); |
| 881 | |
| 882 | trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); |
| 883 | init->offset += 2; |
| 884 | |
| 885 | init_wr32(init, dreg, idata); |
Francisco Jerez | f6853fa | 2013-02-26 02:33:12 +0100 | [diff] [blame] | 886 | init_mask(init, creg, ~mask, data | iaddr); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 887 | } |
| 888 | } |
| 889 | |
| 890 | /** |
| 891 | * INIT_IO_RESTRICT_PLL2 - opcode 0x4a |
| 892 | * |
| 893 | */ |
| 894 | static void |
| 895 | init_io_restrict_pll2(struct nvbios_init *init) |
| 896 | { |
| 897 | struct nouveau_bios *bios = init->bios; |
| 898 | u16 port = nv_ro16(bios, init->offset + 1); |
| 899 | u8 index = nv_ro08(bios, init->offset + 3); |
| 900 | u8 mask = nv_ro08(bios, init->offset + 4); |
| 901 | u8 shift = nv_ro08(bios, init->offset + 5); |
| 902 | u8 count = nv_ro08(bios, init->offset + 6); |
| 903 | u32 reg = nv_ro32(bios, init->offset + 7); |
| 904 | u8 conf, i; |
| 905 | |
| 906 | trace("IO_RESTRICT_PLL2\t" |
| 907 | "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", |
| 908 | reg, port, index, mask, shift); |
| 909 | init->offset += 11; |
| 910 | |
| 911 | conf = (init_rdvgai(init, port, index) & mask) >> shift; |
| 912 | for (i = 0; i < count; i++) { |
| 913 | u32 freq = nv_ro32(bios, init->offset); |
| 914 | if (i == conf) { |
| 915 | trace("\t%dkHz *\n", freq); |
| 916 | init_prog_pll(init, reg, freq); |
| 917 | } else { |
| 918 | trace("\t%dkHz\n", freq); |
| 919 | } |
| 920 | init->offset += 4; |
| 921 | } |
| 922 | trace("}]\n"); |
| 923 | } |
| 924 | |
| 925 | /** |
| 926 | * INIT_PLL2 - opcode 0x4b |
| 927 | * |
| 928 | */ |
| 929 | static void |
| 930 | init_pll2(struct nvbios_init *init) |
| 931 | { |
| 932 | struct nouveau_bios *bios = init->bios; |
| 933 | u32 reg = nv_ro32(bios, init->offset + 1); |
| 934 | u32 freq = nv_ro32(bios, init->offset + 5); |
| 935 | |
| 936 | trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); |
| 937 | init->offset += 9; |
| 938 | |
| 939 | init_prog_pll(init, reg, freq); |
| 940 | } |
| 941 | |
| 942 | /** |
| 943 | * INIT_I2C_BYTE - opcode 0x4c |
| 944 | * |
| 945 | */ |
| 946 | static void |
| 947 | init_i2c_byte(struct nvbios_init *init) |
| 948 | { |
| 949 | struct nouveau_bios *bios = init->bios; |
| 950 | u8 index = nv_ro08(bios, init->offset + 1); |
| 951 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
| 952 | u8 count = nv_ro08(bios, init->offset + 3); |
| 953 | |
| 954 | trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); |
| 955 | init->offset += 4; |
| 956 | |
| 957 | while (count--) { |
| 958 | u8 reg = nv_ro08(bios, init->offset + 0); |
| 959 | u8 mask = nv_ro08(bios, init->offset + 1); |
| 960 | u8 data = nv_ro08(bios, init->offset + 2); |
| 961 | int val; |
| 962 | |
| 963 | trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); |
| 964 | init->offset += 3; |
| 965 | |
| 966 | val = init_rdi2cr(init, index, addr, reg); |
| 967 | if (val < 0) |
| 968 | continue; |
| 969 | init_wri2cr(init, index, addr, reg, (val & mask) | data); |
| 970 | } |
| 971 | } |
| 972 | |
| 973 | /** |
| 974 | * INIT_ZM_I2C_BYTE - opcode 0x4d |
| 975 | * |
| 976 | */ |
| 977 | static void |
| 978 | init_zm_i2c_byte(struct nvbios_init *init) |
| 979 | { |
| 980 | struct nouveau_bios *bios = init->bios; |
| 981 | u8 index = nv_ro08(bios, init->offset + 1); |
| 982 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
| 983 | u8 count = nv_ro08(bios, init->offset + 3); |
| 984 | |
| 985 | trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); |
| 986 | init->offset += 4; |
| 987 | |
| 988 | while (count--) { |
| 989 | u8 reg = nv_ro08(bios, init->offset + 0); |
| 990 | u8 data = nv_ro08(bios, init->offset + 1); |
| 991 | |
| 992 | trace("\t[0x%02x] = 0x%02x\n", reg, data); |
| 993 | init->offset += 2; |
| 994 | |
| 995 | init_wri2cr(init, index, addr, reg, data); |
| 996 | } |
| 997 | |
| 998 | } |
| 999 | |
| 1000 | /** |
| 1001 | * INIT_ZM_I2C - opcode 0x4e |
| 1002 | * |
| 1003 | */ |
| 1004 | static void |
| 1005 | init_zm_i2c(struct nvbios_init *init) |
| 1006 | { |
| 1007 | struct nouveau_bios *bios = init->bios; |
| 1008 | u8 index = nv_ro08(bios, init->offset + 1); |
| 1009 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
| 1010 | u8 count = nv_ro08(bios, init->offset + 3); |
| 1011 | u8 data[256], i; |
| 1012 | |
| 1013 | trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); |
| 1014 | init->offset += 4; |
| 1015 | |
| 1016 | for (i = 0; i < count; i++) { |
| 1017 | data[i] = nv_ro08(bios, init->offset); |
| 1018 | trace("\t0x%02x\n", data[i]); |
| 1019 | init->offset++; |
| 1020 | } |
| 1021 | |
| 1022 | if (init_exec(init)) { |
| 1023 | struct nouveau_i2c_port *port = init_i2c(init, index); |
| 1024 | struct i2c_msg msg = { |
| 1025 | .addr = addr, .flags = 0, .len = count, .buf = data, |
| 1026 | }; |
| 1027 | int ret; |
| 1028 | |
| 1029 | if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1) |
| 1030 | warn("i2c wr failed, %d\n", ret); |
| 1031 | } |
| 1032 | } |
| 1033 | |
| 1034 | /** |
| 1035 | * INIT_TMDS - opcode 0x4f |
| 1036 | * |
| 1037 | */ |
| 1038 | static void |
| 1039 | init_tmds(struct nvbios_init *init) |
| 1040 | { |
| 1041 | struct nouveau_bios *bios = init->bios; |
| 1042 | u8 tmds = nv_ro08(bios, init->offset + 1); |
| 1043 | u8 addr = nv_ro08(bios, init->offset + 2); |
| 1044 | u8 mask = nv_ro08(bios, init->offset + 3); |
| 1045 | u8 data = nv_ro08(bios, init->offset + 4); |
| 1046 | u32 reg = init_tmds_reg(init, tmds); |
| 1047 | |
| 1048 | trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", |
| 1049 | tmds, addr, mask, data); |
| 1050 | init->offset += 5; |
| 1051 | |
| 1052 | if (reg == 0) |
| 1053 | return; |
| 1054 | |
| 1055 | init_wr32(init, reg + 0, addr | 0x00010000); |
| 1056 | init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); |
| 1057 | init_wr32(init, reg + 0, addr); |
| 1058 | } |
| 1059 | |
| 1060 | /** |
| 1061 | * INIT_ZM_TMDS_GROUP - opcode 0x50 |
| 1062 | * |
| 1063 | */ |
| 1064 | static void |
| 1065 | init_zm_tmds_group(struct nvbios_init *init) |
| 1066 | { |
| 1067 | struct nouveau_bios *bios = init->bios; |
| 1068 | u8 tmds = nv_ro08(bios, init->offset + 1); |
| 1069 | u8 count = nv_ro08(bios, init->offset + 2); |
| 1070 | u32 reg = init_tmds_reg(init, tmds); |
| 1071 | |
| 1072 | trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); |
| 1073 | init->offset += 3; |
| 1074 | |
| 1075 | while (count--) { |
| 1076 | u8 addr = nv_ro08(bios, init->offset + 0); |
| 1077 | u8 data = nv_ro08(bios, init->offset + 1); |
| 1078 | |
| 1079 | trace("\t[0x%02x] = 0x%02x\n", addr, data); |
| 1080 | init->offset += 2; |
| 1081 | |
| 1082 | init_wr32(init, reg + 4, data); |
| 1083 | init_wr32(init, reg + 0, addr); |
| 1084 | } |
| 1085 | } |
| 1086 | |
| 1087 | /** |
| 1088 | * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 |
| 1089 | * |
| 1090 | */ |
| 1091 | static void |
| 1092 | init_cr_idx_adr_latch(struct nvbios_init *init) |
| 1093 | { |
| 1094 | struct nouveau_bios *bios = init->bios; |
| 1095 | u8 addr0 = nv_ro08(bios, init->offset + 1); |
| 1096 | u8 addr1 = nv_ro08(bios, init->offset + 2); |
| 1097 | u8 base = nv_ro08(bios, init->offset + 3); |
| 1098 | u8 count = nv_ro08(bios, init->offset + 4); |
| 1099 | u8 save0; |
| 1100 | |
| 1101 | trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); |
| 1102 | init->offset += 5; |
| 1103 | |
| 1104 | save0 = init_rdvgai(init, 0x03d4, addr0); |
| 1105 | while (count--) { |
| 1106 | u8 data = nv_ro08(bios, init->offset); |
| 1107 | |
| 1108 | trace("\t\t[0x%02x] = 0x%02x\n", base, data); |
| 1109 | init->offset += 1; |
| 1110 | |
| 1111 | init_wrvgai(init, 0x03d4, addr0, base++); |
| 1112 | init_wrvgai(init, 0x03d4, addr1, data); |
| 1113 | } |
| 1114 | init_wrvgai(init, 0x03d4, addr0, save0); |
| 1115 | } |
| 1116 | |
| 1117 | /** |
| 1118 | * INIT_CR - opcode 0x52 |
| 1119 | * |
| 1120 | */ |
| 1121 | static void |
| 1122 | init_cr(struct nvbios_init *init) |
| 1123 | { |
| 1124 | struct nouveau_bios *bios = init->bios; |
| 1125 | u8 addr = nv_ro08(bios, init->offset + 1); |
| 1126 | u8 mask = nv_ro08(bios, init->offset + 2); |
| 1127 | u8 data = nv_ro08(bios, init->offset + 3); |
| 1128 | u8 val; |
| 1129 | |
| 1130 | trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); |
| 1131 | init->offset += 4; |
| 1132 | |
| 1133 | val = init_rdvgai(init, 0x03d4, addr) & mask; |
| 1134 | init_wrvgai(init, 0x03d4, addr, val | data); |
| 1135 | } |
| 1136 | |
| 1137 | /** |
| 1138 | * INIT_ZM_CR - opcode 0x53 |
| 1139 | * |
| 1140 | */ |
| 1141 | static void |
| 1142 | init_zm_cr(struct nvbios_init *init) |
| 1143 | { |
| 1144 | struct nouveau_bios *bios = init->bios; |
| 1145 | u8 addr = nv_ro08(bios, init->offset + 1); |
| 1146 | u8 data = nv_ro08(bios, init->offset + 2); |
| 1147 | |
| 1148 | trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); |
| 1149 | init->offset += 3; |
| 1150 | |
| 1151 | init_wrvgai(init, 0x03d4, addr, data); |
| 1152 | } |
| 1153 | |
| 1154 | /** |
| 1155 | * INIT_ZM_CR_GROUP - opcode 0x54 |
| 1156 | * |
| 1157 | */ |
| 1158 | static void |
| 1159 | init_zm_cr_group(struct nvbios_init *init) |
| 1160 | { |
| 1161 | struct nouveau_bios *bios = init->bios; |
| 1162 | u8 count = nv_ro08(bios, init->offset + 1); |
| 1163 | |
| 1164 | trace("ZM_CR_GROUP\n"); |
| 1165 | init->offset += 2; |
| 1166 | |
| 1167 | while (count--) { |
| 1168 | u8 addr = nv_ro08(bios, init->offset + 0); |
| 1169 | u8 data = nv_ro08(bios, init->offset + 1); |
| 1170 | |
| 1171 | trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); |
| 1172 | init->offset += 2; |
| 1173 | |
| 1174 | init_wrvgai(init, 0x03d4, addr, data); |
| 1175 | } |
| 1176 | } |
| 1177 | |
| 1178 | /** |
| 1179 | * INIT_CONDITION_TIME - opcode 0x56 |
| 1180 | * |
| 1181 | */ |
| 1182 | static void |
| 1183 | init_condition_time(struct nvbios_init *init) |
| 1184 | { |
| 1185 | struct nouveau_bios *bios = init->bios; |
| 1186 | u8 cond = nv_ro08(bios, init->offset + 1); |
| 1187 | u8 retry = nv_ro08(bios, init->offset + 2); |
| 1188 | u8 wait = min((u16)retry * 50, 100); |
| 1189 | |
| 1190 | trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); |
| 1191 | init->offset += 3; |
| 1192 | |
| 1193 | if (!init_exec(init)) |
| 1194 | return; |
| 1195 | |
| 1196 | while (wait--) { |
| 1197 | if (init_condition_met(init, cond)) |
| 1198 | return; |
| 1199 | mdelay(20); |
| 1200 | } |
| 1201 | |
| 1202 | init_exec_set(init, false); |
| 1203 | } |
| 1204 | |
| 1205 | /** |
| 1206 | * INIT_LTIME - opcode 0x57 |
| 1207 | * |
| 1208 | */ |
| 1209 | static void |
| 1210 | init_ltime(struct nvbios_init *init) |
| 1211 | { |
| 1212 | struct nouveau_bios *bios = init->bios; |
| 1213 | u16 msec = nv_ro16(bios, init->offset + 1); |
| 1214 | |
| 1215 | trace("LTIME\t0x%04x\n", msec); |
| 1216 | init->offset += 3; |
| 1217 | |
| 1218 | if (init_exec(init)) |
| 1219 | mdelay(msec); |
| 1220 | } |
| 1221 | |
| 1222 | /** |
| 1223 | * INIT_ZM_REG_SEQUENCE - opcode 0x58 |
| 1224 | * |
| 1225 | */ |
| 1226 | static void |
| 1227 | init_zm_reg_sequence(struct nvbios_init *init) |
| 1228 | { |
| 1229 | struct nouveau_bios *bios = init->bios; |
| 1230 | u32 base = nv_ro32(bios, init->offset + 1); |
| 1231 | u8 count = nv_ro08(bios, init->offset + 5); |
| 1232 | |
| 1233 | trace("ZM_REG_SEQUENCE\t0x%02x\n", count); |
| 1234 | init->offset += 6; |
| 1235 | |
| 1236 | while (count--) { |
| 1237 | u32 data = nv_ro32(bios, init->offset); |
| 1238 | |
| 1239 | trace("\t\tR[0x%06x] = 0x%08x\n", base, data); |
| 1240 | init->offset += 4; |
| 1241 | |
| 1242 | init_wr32(init, base, data); |
| 1243 | base += 4; |
| 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | /** |
| 1248 | * INIT_SUB_DIRECT - opcode 0x5b |
| 1249 | * |
| 1250 | */ |
| 1251 | static void |
| 1252 | init_sub_direct(struct nvbios_init *init) |
| 1253 | { |
| 1254 | struct nouveau_bios *bios = init->bios; |
| 1255 | u16 addr = nv_ro16(bios, init->offset + 1); |
| 1256 | u16 save; |
| 1257 | |
| 1258 | trace("SUB_DIRECT\t0x%04x\n", addr); |
| 1259 | |
| 1260 | if (init_exec(init)) { |
| 1261 | save = init->offset; |
| 1262 | init->offset = addr; |
| 1263 | if (nvbios_exec(init)) { |
| 1264 | error("error parsing sub-table\n"); |
| 1265 | return; |
| 1266 | } |
| 1267 | init->offset = save; |
| 1268 | } |
| 1269 | |
| 1270 | init->offset += 3; |
| 1271 | } |
| 1272 | |
| 1273 | /** |
| 1274 | * INIT_JUMP - opcode 0x5c |
| 1275 | * |
| 1276 | */ |
| 1277 | static void |
| 1278 | init_jump(struct nvbios_init *init) |
| 1279 | { |
| 1280 | struct nouveau_bios *bios = init->bios; |
| 1281 | u16 offset = nv_ro16(bios, init->offset + 1); |
| 1282 | |
| 1283 | trace("JUMP\t0x%04x\n", offset); |
| 1284 | init->offset = offset; |
| 1285 | } |
| 1286 | |
| 1287 | /** |
| 1288 | * INIT_I2C_IF - opcode 0x5e |
| 1289 | * |
| 1290 | */ |
| 1291 | static void |
| 1292 | init_i2c_if(struct nvbios_init *init) |
| 1293 | { |
| 1294 | struct nouveau_bios *bios = init->bios; |
| 1295 | u8 index = nv_ro08(bios, init->offset + 1); |
| 1296 | u8 addr = nv_ro08(bios, init->offset + 2); |
| 1297 | u8 reg = nv_ro08(bios, init->offset + 3); |
| 1298 | u8 mask = nv_ro08(bios, init->offset + 4); |
| 1299 | u8 data = nv_ro08(bios, init->offset + 5); |
| 1300 | u8 value; |
| 1301 | |
| 1302 | trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", |
| 1303 | index, addr, reg, mask, data); |
| 1304 | init->offset += 6; |
| 1305 | init_exec_force(init, true); |
| 1306 | |
| 1307 | value = init_rdi2cr(init, index, addr, reg); |
| 1308 | if ((value & mask) != data) |
| 1309 | init_exec_set(init, false); |
| 1310 | |
| 1311 | init_exec_force(init, false); |
| 1312 | } |
| 1313 | |
| 1314 | /** |
| 1315 | * INIT_COPY_NV_REG - opcode 0x5f |
| 1316 | * |
| 1317 | */ |
| 1318 | static void |
| 1319 | init_copy_nv_reg(struct nvbios_init *init) |
| 1320 | { |
| 1321 | struct nouveau_bios *bios = init->bios; |
| 1322 | u32 sreg = nv_ro32(bios, init->offset + 1); |
| 1323 | u8 shift = nv_ro08(bios, init->offset + 5); |
| 1324 | u32 smask = nv_ro32(bios, init->offset + 6); |
| 1325 | u32 sxor = nv_ro32(bios, init->offset + 10); |
| 1326 | u32 dreg = nv_ro32(bios, init->offset + 14); |
| 1327 | u32 dmask = nv_ro32(bios, init->offset + 18); |
| 1328 | u32 data; |
| 1329 | |
| 1330 | trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " |
| 1331 | "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", |
| 1332 | dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", |
| 1333 | (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); |
| 1334 | init->offset += 22; |
| 1335 | |
| 1336 | data = init_shift(init_rd32(init, sreg), shift); |
| 1337 | init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); |
| 1338 | } |
| 1339 | |
| 1340 | /** |
| 1341 | * INIT_ZM_INDEX_IO - opcode 0x62 |
| 1342 | * |
| 1343 | */ |
| 1344 | static void |
| 1345 | init_zm_index_io(struct nvbios_init *init) |
| 1346 | { |
| 1347 | struct nouveau_bios *bios = init->bios; |
| 1348 | u16 port = nv_ro16(bios, init->offset + 1); |
| 1349 | u8 index = nv_ro08(bios, init->offset + 3); |
| 1350 | u8 data = nv_ro08(bios, init->offset + 4); |
| 1351 | |
| 1352 | trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); |
| 1353 | init->offset += 5; |
| 1354 | |
| 1355 | init_wrvgai(init, port, index, data); |
| 1356 | } |
| 1357 | |
| 1358 | /** |
| 1359 | * INIT_COMPUTE_MEM - opcode 0x63 |
| 1360 | * |
| 1361 | */ |
| 1362 | static void |
| 1363 | init_compute_mem(struct nvbios_init *init) |
| 1364 | { |
| 1365 | struct nouveau_devinit *devinit = nouveau_devinit(init->bios); |
| 1366 | |
| 1367 | trace("COMPUTE_MEM\n"); |
| 1368 | init->offset += 1; |
| 1369 | |
| 1370 | init_exec_force(init, true); |
| 1371 | if (init_exec(init) && devinit->meminit) |
| 1372 | devinit->meminit(devinit); |
| 1373 | init_exec_force(init, false); |
| 1374 | } |
| 1375 | |
| 1376 | /** |
| 1377 | * INIT_RESET - opcode 0x65 |
| 1378 | * |
| 1379 | */ |
| 1380 | static void |
| 1381 | init_reset(struct nvbios_init *init) |
| 1382 | { |
| 1383 | struct nouveau_bios *bios = init->bios; |
| 1384 | u32 reg = nv_ro32(bios, init->offset + 1); |
| 1385 | u32 data1 = nv_ro32(bios, init->offset + 5); |
| 1386 | u32 data2 = nv_ro32(bios, init->offset + 9); |
| 1387 | u32 savepci19; |
| 1388 | |
| 1389 | trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); |
| 1390 | init->offset += 13; |
| 1391 | init_exec_force(init, true); |
| 1392 | |
| 1393 | savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); |
| 1394 | init_wr32(init, reg, data1); |
| 1395 | udelay(10); |
| 1396 | init_wr32(init, reg, data2); |
| 1397 | init_wr32(init, 0x00184c, savepci19); |
| 1398 | init_mask(init, 0x001850, 0x00000001, 0x00000000); |
| 1399 | |
| 1400 | init_exec_force(init, false); |
| 1401 | } |
| 1402 | |
| 1403 | /** |
| 1404 | * INIT_CONFIGURE_MEM - opcode 0x66 |
| 1405 | * |
| 1406 | */ |
| 1407 | static u16 |
| 1408 | init_configure_mem_clk(struct nvbios_init *init) |
| 1409 | { |
| 1410 | u16 mdata = bmp_mem_init_table(init->bios); |
| 1411 | if (mdata) |
| 1412 | mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; |
| 1413 | return mdata; |
| 1414 | } |
| 1415 | |
| 1416 | static void |
| 1417 | init_configure_mem(struct nvbios_init *init) |
| 1418 | { |
| 1419 | struct nouveau_bios *bios = init->bios; |
| 1420 | u16 mdata, sdata; |
| 1421 | u32 addr, data; |
| 1422 | |
| 1423 | trace("CONFIGURE_MEM\n"); |
| 1424 | init->offset += 1; |
| 1425 | |
| 1426 | if (bios->version.major > 2) { |
| 1427 | init_done(init); |
| 1428 | return; |
| 1429 | } |
| 1430 | init_exec_force(init, true); |
| 1431 | |
| 1432 | mdata = init_configure_mem_clk(init); |
| 1433 | sdata = bmp_sdr_seq_table(bios); |
| 1434 | if (nv_ro08(bios, mdata) & 0x01) |
| 1435 | sdata = bmp_ddr_seq_table(bios); |
| 1436 | mdata += 6; /* skip to data */ |
| 1437 | |
| 1438 | data = init_rdvgai(init, 0x03c4, 0x01); |
| 1439 | init_wrvgai(init, 0x03c4, 0x01, data | 0x20); |
| 1440 | |
| 1441 | while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) { |
| 1442 | switch (addr) { |
| 1443 | case 0x10021c: /* CKE_NORMAL */ |
| 1444 | case 0x1002d0: /* CMD_REFRESH */ |
| 1445 | case 0x1002d4: /* CMD_PRECHARGE */ |
| 1446 | data = 0x00000001; |
| 1447 | break; |
| 1448 | default: |
| 1449 | data = nv_ro32(bios, mdata); |
| 1450 | mdata += 4; |
| 1451 | if (data == 0xffffffff) |
| 1452 | continue; |
| 1453 | break; |
| 1454 | } |
| 1455 | |
| 1456 | init_wr32(init, addr, data); |
| 1457 | } |
| 1458 | |
| 1459 | init_exec_force(init, false); |
| 1460 | } |
| 1461 | |
| 1462 | /** |
| 1463 | * INIT_CONFIGURE_CLK - opcode 0x67 |
| 1464 | * |
| 1465 | */ |
| 1466 | static void |
| 1467 | init_configure_clk(struct nvbios_init *init) |
| 1468 | { |
| 1469 | struct nouveau_bios *bios = init->bios; |
| 1470 | u16 mdata, clock; |
| 1471 | |
| 1472 | trace("CONFIGURE_CLK\n"); |
| 1473 | init->offset += 1; |
| 1474 | |
| 1475 | if (bios->version.major > 2) { |
| 1476 | init_done(init); |
| 1477 | return; |
| 1478 | } |
| 1479 | init_exec_force(init, true); |
| 1480 | |
| 1481 | mdata = init_configure_mem_clk(init); |
| 1482 | |
| 1483 | /* NVPLL */ |
| 1484 | clock = nv_ro16(bios, mdata + 4) * 10; |
| 1485 | init_prog_pll(init, 0x680500, clock); |
| 1486 | |
| 1487 | /* MPLL */ |
| 1488 | clock = nv_ro16(bios, mdata + 2) * 10; |
| 1489 | if (nv_ro08(bios, mdata) & 0x01) |
| 1490 | clock *= 2; |
| 1491 | init_prog_pll(init, 0x680504, clock); |
| 1492 | |
| 1493 | init_exec_force(init, false); |
| 1494 | } |
| 1495 | |
| 1496 | /** |
| 1497 | * INIT_CONFIGURE_PREINIT - opcode 0x68 |
| 1498 | * |
| 1499 | */ |
| 1500 | static void |
| 1501 | init_configure_preinit(struct nvbios_init *init) |
| 1502 | { |
| 1503 | struct nouveau_bios *bios = init->bios; |
| 1504 | u32 strap; |
| 1505 | |
| 1506 | trace("CONFIGURE_PREINIT\n"); |
| 1507 | init->offset += 1; |
| 1508 | |
| 1509 | if (bios->version.major > 2) { |
| 1510 | init_done(init); |
| 1511 | return; |
| 1512 | } |
| 1513 | init_exec_force(init, true); |
| 1514 | |
| 1515 | strap = init_rd32(init, 0x101000); |
| 1516 | strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); |
| 1517 | init_wrvgai(init, 0x03d4, 0x3c, strap); |
| 1518 | |
| 1519 | init_exec_force(init, false); |
| 1520 | } |
| 1521 | |
| 1522 | /** |
| 1523 | * INIT_IO - opcode 0x69 |
| 1524 | * |
| 1525 | */ |
| 1526 | static void |
| 1527 | init_io(struct nvbios_init *init) |
| 1528 | { |
| 1529 | struct nouveau_bios *bios = init->bios; |
| 1530 | u16 port = nv_ro16(bios, init->offset + 1); |
| 1531 | u8 mask = nv_ro16(bios, init->offset + 3); |
| 1532 | u8 data = nv_ro16(bios, init->offset + 4); |
| 1533 | u8 value; |
| 1534 | |
| 1535 | trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); |
| 1536 | init->offset += 5; |
| 1537 | |
| 1538 | /* ummm.. yes.. should really figure out wtf this is and why it's |
| 1539 | * needed some day.. it's almost certainly wrong, but, it also |
| 1540 | * somehow makes things work... |
| 1541 | */ |
| 1542 | if (nv_device(init->bios)->card_type >= NV_50 && |
| 1543 | port == 0x03c3 && data == 0x01) { |
| 1544 | init_mask(init, 0x614100, 0xf0800000, 0x00800000); |
| 1545 | init_mask(init, 0x00e18c, 0x00020000, 0x00020000); |
| 1546 | init_mask(init, 0x614900, 0xf0800000, 0x00800000); |
| 1547 | init_mask(init, 0x000200, 0x40000000, 0x00000000); |
| 1548 | mdelay(10); |
| 1549 | init_mask(init, 0x00e18c, 0x00020000, 0x00000000); |
| 1550 | init_mask(init, 0x000200, 0x40000000, 0x40000000); |
| 1551 | init_wr32(init, 0x614100, 0x00800018); |
| 1552 | init_wr32(init, 0x614900, 0x00800018); |
| 1553 | mdelay(10); |
| 1554 | init_wr32(init, 0x614100, 0x10000018); |
| 1555 | init_wr32(init, 0x614900, 0x10000018); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1556 | } |
| 1557 | |
| 1558 | value = init_rdport(init, port) & mask; |
| 1559 | init_wrport(init, port, data | value); |
| 1560 | } |
| 1561 | |
| 1562 | /** |
| 1563 | * INIT_SUB - opcode 0x6b |
| 1564 | * |
| 1565 | */ |
| 1566 | static void |
| 1567 | init_sub(struct nvbios_init *init) |
| 1568 | { |
| 1569 | struct nouveau_bios *bios = init->bios; |
| 1570 | u8 index = nv_ro08(bios, init->offset + 1); |
| 1571 | u16 addr, save; |
| 1572 | |
| 1573 | trace("SUB\t0x%02x\n", index); |
| 1574 | |
| 1575 | addr = init_script(bios, index); |
| 1576 | if (addr && init_exec(init)) { |
| 1577 | save = init->offset; |
| 1578 | init->offset = addr; |
| 1579 | if (nvbios_exec(init)) { |
| 1580 | error("error parsing sub-table\n"); |
| 1581 | return; |
| 1582 | } |
| 1583 | init->offset = save; |
| 1584 | } |
| 1585 | |
| 1586 | init->offset += 2; |
| 1587 | } |
| 1588 | |
| 1589 | /** |
| 1590 | * INIT_RAM_CONDITION - opcode 0x6d |
| 1591 | * |
| 1592 | */ |
| 1593 | static void |
| 1594 | init_ram_condition(struct nvbios_init *init) |
| 1595 | { |
| 1596 | struct nouveau_bios *bios = init->bios; |
| 1597 | u8 mask = nv_ro08(bios, init->offset + 1); |
| 1598 | u8 value = nv_ro08(bios, init->offset + 2); |
| 1599 | |
| 1600 | trace("RAM_CONDITION\t" |
| 1601 | "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); |
| 1602 | init->offset += 3; |
| 1603 | |
| 1604 | if ((init_rd32(init, 0x100000) & mask) != value) |
| 1605 | init_exec_set(init, false); |
| 1606 | } |
| 1607 | |
| 1608 | /** |
| 1609 | * INIT_NV_REG - opcode 0x6e |
| 1610 | * |
| 1611 | */ |
| 1612 | static void |
| 1613 | init_nv_reg(struct nvbios_init *init) |
| 1614 | { |
| 1615 | struct nouveau_bios *bios = init->bios; |
| 1616 | u32 reg = nv_ro32(bios, init->offset + 1); |
| 1617 | u32 mask = nv_ro32(bios, init->offset + 5); |
| 1618 | u32 data = nv_ro32(bios, init->offset + 9); |
| 1619 | |
| 1620 | trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); |
| 1621 | init->offset += 13; |
| 1622 | |
| 1623 | init_mask(init, reg, ~mask, data); |
| 1624 | } |
| 1625 | |
| 1626 | /** |
| 1627 | * INIT_MACRO - opcode 0x6f |
| 1628 | * |
| 1629 | */ |
| 1630 | static void |
| 1631 | init_macro(struct nvbios_init *init) |
| 1632 | { |
| 1633 | struct nouveau_bios *bios = init->bios; |
| 1634 | u8 macro = nv_ro08(bios, init->offset + 1); |
| 1635 | u16 table; |
| 1636 | |
| 1637 | trace("MACRO\t0x%02x\n", macro); |
| 1638 | |
| 1639 | table = init_macro_table(init); |
| 1640 | if (table) { |
| 1641 | u32 addr = nv_ro32(bios, table + (macro * 8) + 0); |
| 1642 | u32 data = nv_ro32(bios, table + (macro * 8) + 4); |
| 1643 | trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); |
| 1644 | init_wr32(init, addr, data); |
| 1645 | } |
| 1646 | |
| 1647 | init->offset += 2; |
| 1648 | } |
| 1649 | |
| 1650 | /** |
| 1651 | * INIT_RESUME - opcode 0x72 |
| 1652 | * |
| 1653 | */ |
| 1654 | static void |
| 1655 | init_resume(struct nvbios_init *init) |
| 1656 | { |
| 1657 | trace("RESUME\n"); |
| 1658 | init->offset += 1; |
| 1659 | init_exec_set(init, true); |
| 1660 | } |
| 1661 | |
| 1662 | /** |
| 1663 | * INIT_TIME - opcode 0x74 |
| 1664 | * |
| 1665 | */ |
| 1666 | static void |
| 1667 | init_time(struct nvbios_init *init) |
| 1668 | { |
| 1669 | struct nouveau_bios *bios = init->bios; |
| 1670 | u16 usec = nv_ro16(bios, init->offset + 1); |
| 1671 | |
| 1672 | trace("TIME\t0x%04x\n", usec); |
| 1673 | init->offset += 3; |
| 1674 | |
| 1675 | if (init_exec(init)) { |
| 1676 | if (usec < 1000) |
| 1677 | udelay(usec); |
| 1678 | else |
| 1679 | mdelay((usec + 900) / 1000); |
| 1680 | } |
| 1681 | } |
| 1682 | |
| 1683 | /** |
| 1684 | * INIT_CONDITION - opcode 0x75 |
| 1685 | * |
| 1686 | */ |
| 1687 | static void |
| 1688 | init_condition(struct nvbios_init *init) |
| 1689 | { |
| 1690 | struct nouveau_bios *bios = init->bios; |
| 1691 | u8 cond = nv_ro08(bios, init->offset + 1); |
| 1692 | |
| 1693 | trace("CONDITION\t0x%02x\n", cond); |
| 1694 | init->offset += 2; |
| 1695 | |
| 1696 | if (!init_condition_met(init, cond)) |
| 1697 | init_exec_set(init, false); |
| 1698 | } |
| 1699 | |
| 1700 | /** |
| 1701 | * INIT_IO_CONDITION - opcode 0x76 |
| 1702 | * |
| 1703 | */ |
| 1704 | static void |
| 1705 | init_io_condition(struct nvbios_init *init) |
| 1706 | { |
| 1707 | struct nouveau_bios *bios = init->bios; |
| 1708 | u8 cond = nv_ro08(bios, init->offset + 1); |
| 1709 | |
| 1710 | trace("IO_CONDITION\t0x%02x\n", cond); |
| 1711 | init->offset += 2; |
| 1712 | |
| 1713 | if (!init_io_condition_met(init, cond)) |
| 1714 | init_exec_set(init, false); |
| 1715 | } |
| 1716 | |
| 1717 | /** |
| 1718 | * INIT_INDEX_IO - opcode 0x78 |
| 1719 | * |
| 1720 | */ |
| 1721 | static void |
| 1722 | init_index_io(struct nvbios_init *init) |
| 1723 | { |
| 1724 | struct nouveau_bios *bios = init->bios; |
| 1725 | u16 port = nv_ro16(bios, init->offset + 1); |
| 1726 | u8 index = nv_ro16(bios, init->offset + 3); |
| 1727 | u8 mask = nv_ro08(bios, init->offset + 4); |
| 1728 | u8 data = nv_ro08(bios, init->offset + 5); |
| 1729 | u8 value; |
| 1730 | |
| 1731 | trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", |
| 1732 | port, index, mask, data); |
| 1733 | init->offset += 6; |
| 1734 | |
| 1735 | value = init_rdvgai(init, port, index) & mask; |
| 1736 | init_wrvgai(init, port, index, data | value); |
| 1737 | } |
| 1738 | |
| 1739 | /** |
| 1740 | * INIT_PLL - opcode 0x79 |
| 1741 | * |
| 1742 | */ |
| 1743 | static void |
| 1744 | init_pll(struct nvbios_init *init) |
| 1745 | { |
| 1746 | struct nouveau_bios *bios = init->bios; |
| 1747 | u32 reg = nv_ro32(bios, init->offset + 1); |
| 1748 | u32 freq = nv_ro16(bios, init->offset + 5) * 10; |
| 1749 | |
| 1750 | trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); |
| 1751 | init->offset += 7; |
| 1752 | |
| 1753 | init_prog_pll(init, reg, freq); |
| 1754 | } |
| 1755 | |
| 1756 | /** |
| 1757 | * INIT_ZM_REG - opcode 0x7a |
| 1758 | * |
| 1759 | */ |
| 1760 | static void |
| 1761 | init_zm_reg(struct nvbios_init *init) |
| 1762 | { |
| 1763 | struct nouveau_bios *bios = init->bios; |
| 1764 | u32 addr = nv_ro32(bios, init->offset + 1); |
| 1765 | u32 data = nv_ro32(bios, init->offset + 5); |
| 1766 | |
| 1767 | trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); |
| 1768 | init->offset += 9; |
| 1769 | |
| 1770 | if (addr == 0x000200) |
| 1771 | data |= 0x00000001; |
| 1772 | |
| 1773 | init_wr32(init, addr, data); |
| 1774 | } |
| 1775 | |
| 1776 | /** |
| 1777 | * INIT_RAM_RESTRICT_PLL - opcde 0x87 |
| 1778 | * |
| 1779 | */ |
| 1780 | static void |
| 1781 | init_ram_restrict_pll(struct nvbios_init *init) |
| 1782 | { |
| 1783 | struct nouveau_bios *bios = init->bios; |
| 1784 | u8 type = nv_ro08(bios, init->offset + 1); |
| 1785 | u8 count = init_ram_restrict_group_count(init); |
| 1786 | u8 strap = init_ram_restrict(init); |
| 1787 | u8 cconf; |
| 1788 | |
| 1789 | trace("RAM_RESTRICT_PLL\t0x%02x\n", type); |
| 1790 | init->offset += 2; |
| 1791 | |
| 1792 | for (cconf = 0; cconf < count; cconf++) { |
| 1793 | u32 freq = nv_ro32(bios, init->offset); |
| 1794 | |
| 1795 | if (cconf == strap) { |
| 1796 | trace("%dkHz *\n", freq); |
| 1797 | init_prog_pll(init, type, freq); |
| 1798 | } else { |
| 1799 | trace("%dkHz\n", freq); |
| 1800 | } |
| 1801 | |
| 1802 | init->offset += 4; |
| 1803 | } |
| 1804 | } |
| 1805 | |
| 1806 | /** |
| 1807 | * INIT_GPIO - opcode 0x8e |
| 1808 | * |
| 1809 | */ |
| 1810 | static void |
| 1811 | init_gpio(struct nvbios_init *init) |
| 1812 | { |
| 1813 | struct nouveau_gpio *gpio = nouveau_gpio(init->bios); |
| 1814 | |
| 1815 | trace("GPIO\n"); |
| 1816 | init->offset += 1; |
| 1817 | |
| 1818 | if (init_exec(init) && gpio && gpio->reset) |
Ben Skeggs | 1ed7316 | 2012-12-07 13:46:52 +1000 | [diff] [blame] | 1819 | gpio->reset(gpio, DCB_GPIO_UNUSED); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1820 | } |
| 1821 | |
| 1822 | /** |
| 1823 | * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f |
| 1824 | * |
| 1825 | */ |
| 1826 | static void |
| 1827 | init_ram_restrict_zm_reg_group(struct nvbios_init *init) |
| 1828 | { |
| 1829 | struct nouveau_bios *bios = init->bios; |
| 1830 | u32 addr = nv_ro32(bios, init->offset + 1); |
| 1831 | u8 incr = nv_ro08(bios, init->offset + 5); |
| 1832 | u8 num = nv_ro08(bios, init->offset + 6); |
| 1833 | u8 count = init_ram_restrict_group_count(init); |
| 1834 | u8 index = init_ram_restrict(init); |
| 1835 | u8 i, j; |
| 1836 | |
| 1837 | trace("RAM_RESTRICT_ZM_REG_GROUP\t" |
Marcin Slusarz | bfd8bd1 | 2012-12-30 16:35:24 +0100 | [diff] [blame] | 1838 | "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1839 | init->offset += 7; |
| 1840 | |
| 1841 | for (i = 0; i < num; i++) { |
| 1842 | trace("\tR[0x%06x] = {\n", addr); |
| 1843 | for (j = 0; j < count; j++) { |
| 1844 | u32 data = nv_ro32(bios, init->offset); |
| 1845 | |
| 1846 | if (j == index) { |
| 1847 | trace("\t\t0x%08x *\n", data); |
| 1848 | init_wr32(init, addr, data); |
| 1849 | } else { |
| 1850 | trace("\t\t0x%08x\n", data); |
| 1851 | } |
| 1852 | |
| 1853 | init->offset += 4; |
| 1854 | } |
| 1855 | trace("\t}\n"); |
| 1856 | addr += incr; |
| 1857 | } |
| 1858 | } |
| 1859 | |
| 1860 | /** |
| 1861 | * INIT_COPY_ZM_REG - opcode 0x90 |
| 1862 | * |
| 1863 | */ |
| 1864 | static void |
| 1865 | init_copy_zm_reg(struct nvbios_init *init) |
| 1866 | { |
| 1867 | struct nouveau_bios *bios = init->bios; |
| 1868 | u32 sreg = nv_ro32(bios, init->offset + 1); |
| 1869 | u32 dreg = nv_ro32(bios, init->offset + 5); |
| 1870 | |
Marcin Slusarz | bfd8bd1 | 2012-12-30 16:35:24 +0100 | [diff] [blame] | 1871 | trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1872 | init->offset += 9; |
| 1873 | |
| 1874 | init_wr32(init, dreg, init_rd32(init, sreg)); |
| 1875 | } |
| 1876 | |
| 1877 | /** |
| 1878 | * INIT_ZM_REG_GROUP - opcode 0x91 |
| 1879 | * |
| 1880 | */ |
| 1881 | static void |
| 1882 | init_zm_reg_group(struct nvbios_init *init) |
| 1883 | { |
| 1884 | struct nouveau_bios *bios = init->bios; |
| 1885 | u32 addr = nv_ro32(bios, init->offset + 1); |
| 1886 | u8 count = nv_ro08(bios, init->offset + 5); |
| 1887 | |
Marcin Slusarz | 950fbfa | 2012-12-29 16:24:37 +0100 | [diff] [blame] | 1888 | trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 1889 | init->offset += 6; |
| 1890 | |
| 1891 | while (count--) { |
| 1892 | u32 data = nv_ro32(bios, init->offset); |
| 1893 | trace("\t0x%08x\n", data); |
| 1894 | init_wr32(init, addr, data); |
| 1895 | init->offset += 4; |
| 1896 | } |
| 1897 | } |
| 1898 | |
| 1899 | /** |
| 1900 | * INIT_XLAT - opcode 0x96 |
| 1901 | * |
| 1902 | */ |
| 1903 | static void |
| 1904 | init_xlat(struct nvbios_init *init) |
| 1905 | { |
| 1906 | struct nouveau_bios *bios = init->bios; |
| 1907 | u32 saddr = nv_ro32(bios, init->offset + 1); |
| 1908 | u8 sshift = nv_ro08(bios, init->offset + 5); |
| 1909 | u8 smask = nv_ro08(bios, init->offset + 6); |
| 1910 | u8 index = nv_ro08(bios, init->offset + 7); |
| 1911 | u32 daddr = nv_ro32(bios, init->offset + 8); |
| 1912 | u32 dmask = nv_ro32(bios, init->offset + 12); |
| 1913 | u8 shift = nv_ro08(bios, init->offset + 16); |
| 1914 | u32 data; |
| 1915 | |
| 1916 | trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " |
| 1917 | "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", |
| 1918 | daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", |
| 1919 | (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); |
| 1920 | init->offset += 17; |
| 1921 | |
| 1922 | data = init_shift(init_rd32(init, saddr), sshift) & smask; |
| 1923 | data = init_xlat_(init, index, data) << shift; |
| 1924 | init_mask(init, daddr, ~dmask, data); |
| 1925 | } |
| 1926 | |
| 1927 | /** |
| 1928 | * INIT_ZM_MASK_ADD - opcode 0x97 |
| 1929 | * |
| 1930 | */ |
| 1931 | static void |
| 1932 | init_zm_mask_add(struct nvbios_init *init) |
| 1933 | { |
| 1934 | struct nouveau_bios *bios = init->bios; |
| 1935 | u32 addr = nv_ro32(bios, init->offset + 1); |
| 1936 | u32 mask = nv_ro32(bios, init->offset + 5); |
| 1937 | u32 add = nv_ro32(bios, init->offset + 9); |
| 1938 | u32 data; |
| 1939 | |
| 1940 | trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); |
| 1941 | init->offset += 13; |
| 1942 | |
| 1943 | data = init_rd32(init, addr) & mask; |
| 1944 | data |= ((data + add) & ~mask); |
| 1945 | init_wr32(init, addr, data); |
| 1946 | } |
| 1947 | |
| 1948 | /** |
| 1949 | * INIT_AUXCH - opcode 0x98 |
| 1950 | * |
| 1951 | */ |
| 1952 | static void |
| 1953 | init_auxch(struct nvbios_init *init) |
| 1954 | { |
| 1955 | struct nouveau_bios *bios = init->bios; |
| 1956 | u32 addr = nv_ro32(bios, init->offset + 1); |
| 1957 | u8 count = nv_ro08(bios, init->offset + 5); |
| 1958 | |
| 1959 | trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); |
| 1960 | init->offset += 6; |
| 1961 | |
| 1962 | while (count--) { |
| 1963 | u8 mask = nv_ro08(bios, init->offset + 0); |
| 1964 | u8 data = nv_ro08(bios, init->offset + 1); |
| 1965 | trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); |
| 1966 | mask = init_rdauxr(init, addr) & mask; |
| 1967 | init_wrauxr(init, addr, mask | data); |
| 1968 | init->offset += 2; |
| 1969 | } |
| 1970 | } |
| 1971 | |
| 1972 | /** |
| 1973 | * INIT_AUXCH - opcode 0x99 |
| 1974 | * |
| 1975 | */ |
| 1976 | static void |
| 1977 | init_zm_auxch(struct nvbios_init *init) |
| 1978 | { |
| 1979 | struct nouveau_bios *bios = init->bios; |
| 1980 | u32 addr = nv_ro32(bios, init->offset + 1); |
| 1981 | u8 count = nv_ro08(bios, init->offset + 5); |
| 1982 | |
| 1983 | trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); |
| 1984 | init->offset += 6; |
| 1985 | |
| 1986 | while (count--) { |
| 1987 | u8 data = nv_ro08(bios, init->offset + 0); |
| 1988 | trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); |
| 1989 | init_wrauxr(init, addr, data); |
| 1990 | init->offset += 1; |
| 1991 | } |
| 1992 | } |
| 1993 | |
| 1994 | /** |
| 1995 | * INIT_I2C_LONG_IF - opcode 0x9a |
| 1996 | * |
| 1997 | */ |
| 1998 | static void |
| 1999 | init_i2c_long_if(struct nvbios_init *init) |
| 2000 | { |
| 2001 | struct nouveau_bios *bios = init->bios; |
| 2002 | u8 index = nv_ro08(bios, init->offset + 1); |
| 2003 | u8 addr = nv_ro08(bios, init->offset + 2) >> 1; |
| 2004 | u8 reglo = nv_ro08(bios, init->offset + 3); |
| 2005 | u8 reghi = nv_ro08(bios, init->offset + 4); |
| 2006 | u8 mask = nv_ro08(bios, init->offset + 5); |
| 2007 | u8 data = nv_ro08(bios, init->offset + 6); |
| 2008 | struct nouveau_i2c_port *port; |
| 2009 | |
| 2010 | trace("I2C_LONG_IF\t" |
| 2011 | "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", |
| 2012 | index, addr, reglo, reghi, mask, data); |
| 2013 | init->offset += 7; |
| 2014 | |
| 2015 | port = init_i2c(init, index); |
| 2016 | if (port) { |
| 2017 | u8 i[2] = { reghi, reglo }; |
| 2018 | u8 o[1] = {}; |
| 2019 | struct i2c_msg msg[] = { |
| 2020 | { .addr = addr, .flags = 0, .len = 2, .buf = i }, |
| 2021 | { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } |
| 2022 | }; |
| 2023 | int ret; |
| 2024 | |
| 2025 | ret = i2c_transfer(&port->adapter, msg, 2); |
| 2026 | if (ret == 2 && ((o[0] & mask) == data)) |
| 2027 | return; |
| 2028 | } |
| 2029 | |
| 2030 | init_exec_set(init, false); |
| 2031 | } |
| 2032 | |
Ben Skeggs | 1ed7316 | 2012-12-07 13:46:52 +1000 | [diff] [blame] | 2033 | /** |
| 2034 | * INIT_GPIO_NE - opcode 0xa9 |
| 2035 | * |
| 2036 | */ |
| 2037 | static void |
| 2038 | init_gpio_ne(struct nvbios_init *init) |
| 2039 | { |
| 2040 | struct nouveau_bios *bios = init->bios; |
| 2041 | struct nouveau_gpio *gpio = nouveau_gpio(bios); |
| 2042 | struct dcb_gpio_func func; |
| 2043 | u8 count = nv_ro08(bios, init->offset + 1); |
| 2044 | u8 idx = 0, ver, len; |
| 2045 | u16 data, i; |
| 2046 | |
| 2047 | trace("GPIO_NE\t"); |
| 2048 | init->offset += 2; |
| 2049 | |
| 2050 | for (i = init->offset; i < init->offset + count; i++) |
| 2051 | cont("0x%02x ", nv_ro08(bios, i)); |
| 2052 | cont("\n"); |
| 2053 | |
| 2054 | while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { |
| 2055 | if (func.func != DCB_GPIO_UNUSED) { |
| 2056 | for (i = init->offset; i < init->offset + count; i++) { |
| 2057 | if (func.func == nv_ro08(bios, i)) |
| 2058 | break; |
| 2059 | } |
| 2060 | |
| 2061 | trace("\tFUNC[0x%02x]", func.func); |
| 2062 | if (i == (init->offset + count)) { |
| 2063 | cont(" *"); |
| 2064 | if (init_exec(init) && gpio && gpio->reset) |
| 2065 | gpio->reset(gpio, func.func); |
| 2066 | } |
| 2067 | cont("\n"); |
| 2068 | } |
| 2069 | } |
| 2070 | |
| 2071 | init->offset += count; |
| 2072 | } |
| 2073 | |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 2074 | static struct nvbios_init_opcode { |
| 2075 | void (*exec)(struct nvbios_init *); |
| 2076 | } init_opcode[] = { |
| 2077 | [0x32] = { init_io_restrict_prog }, |
| 2078 | [0x33] = { init_repeat }, |
| 2079 | [0x34] = { init_io_restrict_pll }, |
| 2080 | [0x36] = { init_end_repeat }, |
| 2081 | [0x37] = { init_copy }, |
| 2082 | [0x38] = { init_not }, |
| 2083 | [0x39] = { init_io_flag_condition }, |
| 2084 | [0x3a] = { init_dp_condition }, |
| 2085 | [0x3b] = { init_io_mask_or }, |
| 2086 | [0x3c] = { init_io_or }, |
| 2087 | [0x49] = { init_idx_addr_latched }, |
| 2088 | [0x4a] = { init_io_restrict_pll2 }, |
| 2089 | [0x4b] = { init_pll2 }, |
| 2090 | [0x4c] = { init_i2c_byte }, |
| 2091 | [0x4d] = { init_zm_i2c_byte }, |
| 2092 | [0x4e] = { init_zm_i2c }, |
| 2093 | [0x4f] = { init_tmds }, |
| 2094 | [0x50] = { init_zm_tmds_group }, |
| 2095 | [0x51] = { init_cr_idx_adr_latch }, |
| 2096 | [0x52] = { init_cr }, |
| 2097 | [0x53] = { init_zm_cr }, |
| 2098 | [0x54] = { init_zm_cr_group }, |
| 2099 | [0x56] = { init_condition_time }, |
| 2100 | [0x57] = { init_ltime }, |
| 2101 | [0x58] = { init_zm_reg_sequence }, |
| 2102 | [0x5b] = { init_sub_direct }, |
| 2103 | [0x5c] = { init_jump }, |
| 2104 | [0x5e] = { init_i2c_if }, |
| 2105 | [0x5f] = { init_copy_nv_reg }, |
| 2106 | [0x62] = { init_zm_index_io }, |
| 2107 | [0x63] = { init_compute_mem }, |
| 2108 | [0x65] = { init_reset }, |
| 2109 | [0x66] = { init_configure_mem }, |
| 2110 | [0x67] = { init_configure_clk }, |
| 2111 | [0x68] = { init_configure_preinit }, |
| 2112 | [0x69] = { init_io }, |
| 2113 | [0x6b] = { init_sub }, |
| 2114 | [0x6d] = { init_ram_condition }, |
| 2115 | [0x6e] = { init_nv_reg }, |
| 2116 | [0x6f] = { init_macro }, |
| 2117 | [0x71] = { init_done }, |
| 2118 | [0x72] = { init_resume }, |
| 2119 | [0x74] = { init_time }, |
| 2120 | [0x75] = { init_condition }, |
| 2121 | [0x76] = { init_io_condition }, |
| 2122 | [0x78] = { init_index_io }, |
| 2123 | [0x79] = { init_pll }, |
| 2124 | [0x7a] = { init_zm_reg }, |
| 2125 | [0x87] = { init_ram_restrict_pll }, |
| 2126 | [0x8c] = { init_reserved }, |
| 2127 | [0x8d] = { init_reserved }, |
| 2128 | [0x8e] = { init_gpio }, |
| 2129 | [0x8f] = { init_ram_restrict_zm_reg_group }, |
| 2130 | [0x90] = { init_copy_zm_reg }, |
| 2131 | [0x91] = { init_zm_reg_group }, |
| 2132 | [0x92] = { init_reserved }, |
| 2133 | [0x96] = { init_xlat }, |
| 2134 | [0x97] = { init_zm_mask_add }, |
| 2135 | [0x98] = { init_auxch }, |
| 2136 | [0x99] = { init_zm_auxch }, |
| 2137 | [0x9a] = { init_i2c_long_if }, |
Ben Skeggs | 1ed7316 | 2012-12-07 13:46:52 +1000 | [diff] [blame] | 2138 | [0xa9] = { init_gpio_ne }, |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 2139 | }; |
| 2140 | |
| 2141 | #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) |
| 2142 | |
| 2143 | int |
| 2144 | nvbios_exec(struct nvbios_init *init) |
| 2145 | { |
| 2146 | init->nested++; |
| 2147 | while (init->offset) { |
| 2148 | u8 opcode = nv_ro08(init->bios, init->offset); |
| 2149 | if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { |
| 2150 | error("unknown opcode 0x%02x\n", opcode); |
| 2151 | return -EINVAL; |
| 2152 | } |
| 2153 | |
| 2154 | init_opcode[opcode].exec(init); |
| 2155 | } |
| 2156 | init->nested--; |
| 2157 | return 0; |
| 2158 | } |
| 2159 | |
| 2160 | int |
| 2161 | nvbios_init(struct nouveau_subdev *subdev, bool execute) |
| 2162 | { |
| 2163 | struct nouveau_bios *bios = nouveau_bios(subdev); |
| 2164 | int ret = 0; |
| 2165 | int i = -1; |
| 2166 | u16 data; |
| 2167 | |
| 2168 | if (execute) |
| 2169 | nv_info(bios, "running init tables\n"); |
| 2170 | while (!ret && (data = (init_script(bios, ++i)))) { |
| 2171 | struct nvbios_init init = { |
| 2172 | .subdev = subdev, |
| 2173 | .bios = bios, |
| 2174 | .offset = data, |
| 2175 | .outp = NULL, |
| 2176 | .crtc = -1, |
| 2177 | .execute = execute ? 1 : 0, |
| 2178 | }; |
| 2179 | |
| 2180 | ret = nvbios_exec(&init); |
| 2181 | } |
| 2182 | |
| 2183 | /* the vbios parser will run this right after the normal init |
| 2184 | * tables, whereas the binary driver appears to run it later. |
| 2185 | */ |
| 2186 | if (!ret && (data = init_unknown_script(bios))) { |
| 2187 | struct nvbios_init init = { |
| 2188 | .subdev = subdev, |
| 2189 | .bios = bios, |
| 2190 | .offset = data, |
| 2191 | .outp = NULL, |
| 2192 | .crtc = -1, |
| 2193 | .execute = execute ? 1 : 0, |
| 2194 | }; |
| 2195 | |
| 2196 | ret = nvbios_exec(&init); |
| 2197 | } |
| 2198 | |
| 2199 | return 0; |
| 2200 | } |