blob: b723622fe94a2407c733edaf67abfe3d81082aff [file] [log] [blame]
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001/*
2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
3 *
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +010021#include <linux/string.h>
22#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/tcp.h>
28#include <linux/skbuff.h>
29#include <linux/delay.h>
30#include <linux/spi/spi.h>
31
32#include "enc28j60_hw.h"
33
34#define DRV_NAME "enc28j60"
35#define DRV_VERSION "1.01"
36
37#define SPI_OPLEN 1
38
39#define ENC28J60_MSG_DEFAULT \
40 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
41
42/* Buffer size required for the largest SPI transfer (i.e., reading a
43 * frame). */
44#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
45
46#define TX_TIMEOUT (4 * HZ)
47
48/* Max TX retries in case of collision as suggested by errata datasheet */
49#define MAX_TX_RETRYCOUNT 16
50
51enum {
52 RXFILTER_NORMAL,
53 RXFILTER_MULTI,
54 RXFILTER_PROMISC
55};
56
57/* Driver local data */
58struct enc28j60_net {
59 struct net_device *netdev;
60 struct spi_device *spi;
61 struct mutex lock;
62 struct sk_buff *tx_skb;
63 struct work_struct tx_work;
64 struct work_struct irq_work;
65 struct work_struct setrx_work;
66 struct work_struct restart_work;
67 u8 bank; /* current register bank selected */
68 u16 next_pk_ptr; /* next packet pointer within FIFO */
69 u16 max_pk_counter; /* statistics: max packet counter */
70 u16 tx_retry_count;
71 bool hw_enable;
72 bool full_duplex;
73 int rxfilter;
74 u32 msg_enable;
75 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
76};
77
78/* use ethtool to change the level for any given device */
79static struct {
80 u32 msg_enable;
81} debug = { -1 };
82
83/*
84 * SPI read buffer
85 * wait for the SPI transfer and copy received data to destination
86 */
87static int
88spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
89{
90 u8 *rx_buf = priv->spi_transfer_buf + 4;
91 u8 *tx_buf = priv->spi_transfer_buf;
Michael Heimpold2957a282016-04-28 22:06:14 +020092 struct spi_transfer tx = {
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +010093 .tx_buf = tx_buf,
Michael Heimpold2957a282016-04-28 22:06:14 +020094 .len = SPI_OPLEN,
95 };
96 struct spi_transfer rx = {
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +010097 .rx_buf = rx_buf,
Michael Heimpold2957a282016-04-28 22:06:14 +020098 .len = len,
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +010099 };
100 struct spi_message msg;
101 int ret;
102
103 tx_buf[0] = ENC28J60_READ_BUF_MEM;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100104
105 spi_message_init(&msg);
Michael Heimpold2957a282016-04-28 22:06:14 +0200106 spi_message_add_tail(&tx, &msg);
107 spi_message_add_tail(&rx, &msg);
108
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100109 ret = spi_sync(priv->spi, &msg);
110 if (ret == 0) {
Michael Heimpold2957a282016-04-28 22:06:14 +0200111 memcpy(data, rx_buf, len);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100112 ret = msg.status;
113 }
114 if (ret && netif_msg_drv(priv))
115 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700116 __func__, ret);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100117
118 return ret;
119}
120
121/*
122 * SPI write buffer
123 */
124static int spi_write_buf(struct enc28j60_net *priv, int len,
125 const u8 *data)
126{
127 int ret;
128
129 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
130 ret = -EINVAL;
131 else {
132 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
133 memcpy(&priv->spi_transfer_buf[1], data, len);
134 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
135 if (ret && netif_msg_drv(priv))
136 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700137 __func__, ret);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100138 }
139 return ret;
140}
141
142/*
143 * basic SPI read operation
144 */
145static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
146 u8 addr)
147{
148 u8 tx_buf[2];
149 u8 rx_buf[4];
150 u8 val = 0;
151 int ret;
152 int slen = SPI_OPLEN;
153
154 /* do dummy read if needed */
155 if (addr & SPRD_MASK)
156 slen++;
157
158 tx_buf[0] = op | (addr & ADDR_MASK);
159 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
160 if (ret)
161 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700162 __func__, ret);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100163 else
164 val = rx_buf[slen - 1];
165
166 return val;
167}
168
169/*
170 * basic SPI write operation
171 */
172static int spi_write_op(struct enc28j60_net *priv, u8 op,
173 u8 addr, u8 val)
174{
175 int ret;
176
177 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
178 priv->spi_transfer_buf[1] = val;
179 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
180 if (ret && netif_msg_drv(priv))
181 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700182 __func__, ret);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100183 return ret;
184}
185
186static void enc28j60_soft_reset(struct enc28j60_net *priv)
187{
188 if (netif_msg_hw(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700189 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100190
191 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
192 /* Errata workaround #1, CLKRDY check is unreliable,
193 * delay at least 1 mS instead */
194 udelay(2000);
195}
196
197/*
198 * select the current register bank if necessary
199 */
200static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
201{
Baruch Siach5664dd52008-12-18 19:39:14 -0800202 u8 b = (addr & BANK_MASK) >> 5;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100203
Baruch Siach5664dd52008-12-18 19:39:14 -0800204 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
205 * are present in all banks, no need to switch bank
206 */
207 if (addr >= EIE && addr <= ECON1)
208 return;
209
210 /* Clear or set each bank selection bit as needed */
211 if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
212 if (b & ECON1_BSEL0)
213 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
214 ECON1_BSEL0);
215 else
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100216 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
Baruch Siach5664dd52008-12-18 19:39:14 -0800217 ECON1_BSEL0);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100218 }
Baruch Siach5664dd52008-12-18 19:39:14 -0800219 if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
220 if (b & ECON1_BSEL1)
221 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
222 ECON1_BSEL1);
223 else
224 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
225 ECON1_BSEL1);
226 }
227 priv->bank = b;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100228}
229
230/*
231 * Register access routines through the SPI bus.
232 * Every register access comes in two flavours:
233 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
234 * atomically more than one register
235 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
236 *
237 * Some registers can be accessed through the bit field clear and
238 * bit field set to avoid a read modify write cycle.
239 */
240
241/*
242 * Register bit field Set
243 */
244static void nolock_reg_bfset(struct enc28j60_net *priv,
245 u8 addr, u8 mask)
246{
247 enc28j60_set_bank(priv, addr);
248 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
249}
250
251static void locked_reg_bfset(struct enc28j60_net *priv,
252 u8 addr, u8 mask)
253{
254 mutex_lock(&priv->lock);
255 nolock_reg_bfset(priv, addr, mask);
256 mutex_unlock(&priv->lock);
257}
258
259/*
260 * Register bit field Clear
261 */
262static void nolock_reg_bfclr(struct enc28j60_net *priv,
263 u8 addr, u8 mask)
264{
265 enc28j60_set_bank(priv, addr);
266 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
267}
268
269static void locked_reg_bfclr(struct enc28j60_net *priv,
270 u8 addr, u8 mask)
271{
272 mutex_lock(&priv->lock);
273 nolock_reg_bfclr(priv, addr, mask);
274 mutex_unlock(&priv->lock);
275}
276
277/*
278 * Register byte read
279 */
280static int nolock_regb_read(struct enc28j60_net *priv,
281 u8 address)
282{
283 enc28j60_set_bank(priv, address);
284 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
285}
286
287static int locked_regb_read(struct enc28j60_net *priv,
288 u8 address)
289{
290 int ret;
291
292 mutex_lock(&priv->lock);
293 ret = nolock_regb_read(priv, address);
294 mutex_unlock(&priv->lock);
295
296 return ret;
297}
298
299/*
300 * Register word read
301 */
302static int nolock_regw_read(struct enc28j60_net *priv,
303 u8 address)
304{
305 int rl, rh;
306
307 enc28j60_set_bank(priv, address);
308 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
309 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
310
311 return (rh << 8) | rl;
312}
313
314static int locked_regw_read(struct enc28j60_net *priv,
315 u8 address)
316{
317 int ret;
318
319 mutex_lock(&priv->lock);
320 ret = nolock_regw_read(priv, address);
321 mutex_unlock(&priv->lock);
322
323 return ret;
324}
325
326/*
327 * Register byte write
328 */
329static void nolock_regb_write(struct enc28j60_net *priv,
330 u8 address, u8 data)
331{
332 enc28j60_set_bank(priv, address);
333 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
334}
335
336static void locked_regb_write(struct enc28j60_net *priv,
337 u8 address, u8 data)
338{
339 mutex_lock(&priv->lock);
340 nolock_regb_write(priv, address, data);
341 mutex_unlock(&priv->lock);
342}
343
344/*
345 * Register word write
346 */
347static void nolock_regw_write(struct enc28j60_net *priv,
348 u8 address, u16 data)
349{
350 enc28j60_set_bank(priv, address);
351 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
352 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
353 (u8) (data >> 8));
354}
355
356static void locked_regw_write(struct enc28j60_net *priv,
357 u8 address, u16 data)
358{
359 mutex_lock(&priv->lock);
360 nolock_regw_write(priv, address, data);
361 mutex_unlock(&priv->lock);
362}
363
364/*
365 * Buffer memory read
366 * Select the starting address and execute a SPI buffer read
367 */
368static void enc28j60_mem_read(struct enc28j60_net *priv,
369 u16 addr, int len, u8 *data)
370{
371 mutex_lock(&priv->lock);
372 nolock_regw_write(priv, ERDPTL, addr);
373#ifdef CONFIG_ENC28J60_WRITEVERIFY
374 if (netif_msg_drv(priv)) {
375 u16 reg;
376 reg = nolock_regw_read(priv, ERDPTL);
377 if (reg != addr)
378 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700379 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100380 }
381#endif
382 spi_read_buf(priv, len, data);
383 mutex_unlock(&priv->lock);
384}
385
386/*
387 * Write packet to enc28j60 TX buffer memory
388 */
389static void
390enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
391{
392 mutex_lock(&priv->lock);
393 /* Set the write pointer to start of transmit buffer area */
394 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
395#ifdef CONFIG_ENC28J60_WRITEVERIFY
396 if (netif_msg_drv(priv)) {
397 u16 reg;
398 reg = nolock_regw_read(priv, EWRPTL);
399 if (reg != TXSTART_INIT)
400 printk(KERN_DEBUG DRV_NAME
401 ": %s() ERWPT:0x%04x != 0x%04x\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700402 __func__, reg, TXSTART_INIT);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100403 }
404#endif
405 /* Set the TXND pointer to correspond to the packet size given */
406 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
407 /* write per-packet control byte */
408 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
409 if (netif_msg_hw(priv))
410 printk(KERN_DEBUG DRV_NAME
411 ": %s() after control byte ERWPT:0x%04x\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700412 __func__, nolock_regw_read(priv, EWRPTL));
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100413 /* copy the packet into the transmit buffer */
414 spi_write_buf(priv, len, data);
415 if (netif_msg_hw(priv))
416 printk(KERN_DEBUG DRV_NAME
417 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700418 __func__, nolock_regw_read(priv, EWRPTL), len);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100419 mutex_unlock(&priv->lock);
420}
421
David Brownell7dac6f82008-06-12 21:38:06 -0700422static unsigned long msec20_to_jiffies;
423
424static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
425{
426 unsigned long timeout = jiffies + msec20_to_jiffies;
427
428 /* 20 msec timeout read */
429 while ((nolock_regb_read(priv, reg) & mask) != val) {
430 if (time_after(jiffies, timeout)) {
431 if (netif_msg_drv(priv))
432 dev_dbg(&priv->spi->dev,
433 "reg %02x ready timeout!\n", reg);
434 return -ETIMEDOUT;
435 }
436 cpu_relax();
437 }
438 return 0;
439}
440
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100441/*
442 * Wait until the PHY operation is complete.
443 */
444static int wait_phy_ready(struct enc28j60_net *priv)
445{
David Brownell7dac6f82008-06-12 21:38:06 -0700446 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100447}
448
449/*
450 * PHY register read
451 * PHY registers are not accessed directly, but through the MII
452 */
453static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
454{
455 u16 ret;
456
457 mutex_lock(&priv->lock);
458 /* set the PHY register address */
459 nolock_regb_write(priv, MIREGADR, address);
460 /* start the register read operation */
461 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
462 /* wait until the PHY read completes */
463 wait_phy_ready(priv);
464 /* quit reading */
465 nolock_regb_write(priv, MICMD, 0x00);
466 /* return the data */
467 ret = nolock_regw_read(priv, MIRDL);
468 mutex_unlock(&priv->lock);
469
470 return ret;
471}
472
473static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
474{
475 int ret;
476
477 mutex_lock(&priv->lock);
478 /* set the PHY register address */
479 nolock_regb_write(priv, MIREGADR, address);
480 /* write the PHY data */
481 nolock_regw_write(priv, MIWRL, data);
482 /* wait until the PHY write completes and return */
483 ret = wait_phy_ready(priv);
484 mutex_unlock(&priv->lock);
485
486 return ret;
487}
488
489/*
490 * Program the hardware MAC address from dev->dev_addr.
491 */
492static int enc28j60_set_hw_macaddr(struct net_device *ndev)
493{
494 int ret;
495 struct enc28j60_net *priv = netdev_priv(ndev);
496
497 mutex_lock(&priv->lock);
498 if (!priv->hw_enable) {
Johannes Berge1749612008-10-27 15:59:26 -0700499 if (netif_msg_drv(priv))
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100500 printk(KERN_INFO DRV_NAME
Johannes Berge1749612008-10-27 15:59:26 -0700501 ": %s: Setting MAC address to %pM\n",
502 ndev->name, ndev->dev_addr);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100503 /* NOTE: MAC address in ENC28J60 is byte-backward */
504 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
505 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
506 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
507 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
508 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
509 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
510 ret = 0;
511 } else {
512 if (netif_msg_drv(priv))
513 printk(KERN_DEBUG DRV_NAME
514 ": %s() Hardware must be disabled to set "
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700515 "Mac address\n", __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100516 ret = -EBUSY;
517 }
518 mutex_unlock(&priv->lock);
519 return ret;
520}
521
522/*
523 * Store the new hardware address in dev->dev_addr, and update the MAC.
524 */
525static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
526{
527 struct sockaddr *address = addr;
528
529 if (netif_running(dev))
530 return -EBUSY;
531 if (!is_valid_ether_addr(address->sa_data))
532 return -EADDRNOTAVAIL;
533
534 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
535 return enc28j60_set_hw_macaddr(dev);
536}
537
538/*
539 * Debug routine to dump useful register contents
540 */
541static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
542{
543 mutex_lock(&priv->lock);
544 printk(KERN_DEBUG DRV_NAME " %s\n"
545 "HwRevID: 0x%02x\n"
546 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
547 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
548 "MAC : MACON1 MACON3 MACON4\n"
549 " 0x%02x 0x%02x 0x%02x\n"
550 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
551 " 0x%04x 0x%04x 0x%04x 0x%04x "
552 "0x%02x 0x%02x 0x%04x\n"
553 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
554 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
555 msg, nolock_regb_read(priv, EREVID),
556 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
557 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
558 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
559 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
560 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
561 nolock_regw_read(priv, ERXWRPTL),
562 nolock_regw_read(priv, ERXRDPTL),
563 nolock_regb_read(priv, ERXFCON),
564 nolock_regb_read(priv, EPKTCNT),
565 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
566 nolock_regw_read(priv, ETXNDL),
567 nolock_regb_read(priv, MACLCON1),
568 nolock_regb_read(priv, MACLCON2),
569 nolock_regb_read(priv, MAPHSUP));
570 mutex_unlock(&priv->lock);
571}
572
573/*
574 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
575 */
576static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
577{
578 u16 erxrdpt;
579
580 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
581 erxrdpt = end;
582 else
583 erxrdpt = next_packet_ptr - 1;
584
585 return erxrdpt;
586}
587
Baruch Siach5176da72008-12-02 05:07:01 +0000588/*
589 * Calculate wrap around when reading beyond the end of the RX buffer
590 */
591static u16 rx_packet_start(u16 ptr)
592{
593 if (ptr + RSV_SIZE > RXEND_INIT)
594 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
595 else
596 return ptr + RSV_SIZE;
597}
598
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100599static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
600{
601 u16 erxrdpt;
602
603 if (start > 0x1FFF || end > 0x1FFF || start > end) {
604 if (netif_msg_drv(priv))
605 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700606 "bad parameters!\n", __func__, start, end);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100607 return;
608 }
609 /* set receive buffer start + end */
610 priv->next_pk_ptr = start;
611 nolock_regw_write(priv, ERXSTL, start);
612 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
613 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
614 nolock_regw_write(priv, ERXNDL, end);
615}
616
617static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
618{
619 if (start > 0x1FFF || end > 0x1FFF || start > end) {
620 if (netif_msg_drv(priv))
621 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700622 "bad parameters!\n", __func__, start, end);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100623 return;
624 }
625 /* set transmit buffer start + end */
626 nolock_regw_write(priv, ETXSTL, start);
627 nolock_regw_write(priv, ETXNDL, end);
628}
629
David Brownell7dac6f82008-06-12 21:38:06 -0700630/*
631 * Low power mode shrinks power consumption about 100x, so we'd like
632 * the chip to be in that mode whenever it's inactive. (However, we
633 * can't stay in lowpower mode during suspend with WOL active.)
634 */
635static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
636{
637 if (netif_msg_drv(priv))
638 dev_dbg(&priv->spi->dev, "%s power...\n",
639 is_low ? "low" : "high");
640
641 mutex_lock(&priv->lock);
642 if (is_low) {
643 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
644 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
645 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
646 /* ECON2_VRPS was set during initialization */
647 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
648 } else {
649 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
650 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
651 /* caller sets ECON1_RXEN */
652 }
653 mutex_unlock(&priv->lock);
654}
655
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100656static int enc28j60_hw_init(struct enc28j60_net *priv)
657{
658 u8 reg;
659
660 if (netif_msg_drv(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700661 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100662 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
663
664 mutex_lock(&priv->lock);
665 /* first reset the chip */
666 enc28j60_soft_reset(priv);
667 /* Clear ECON1 */
668 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
669 priv->bank = 0;
670 priv->hw_enable = false;
671 priv->tx_retry_count = 0;
672 priv->max_pk_counter = 0;
673 priv->rxfilter = RXFILTER_NORMAL;
David Brownell7dac6f82008-06-12 21:38:06 -0700674 /* enable address auto increment and voltage regulator powersave */
675 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100676
677 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
678 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
679 mutex_unlock(&priv->lock);
680
681 /*
682 * Check the RevID.
683 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
684 * damaged
685 */
686 reg = locked_regb_read(priv, EREVID);
687 if (netif_msg_drv(priv))
688 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
689 if (reg == 0x00 || reg == 0xff) {
690 if (netif_msg_drv(priv))
691 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700692 __func__, reg);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100693 return 0;
694 }
695
696 /* default filter mode: (unicast OR broadcast) AND crc valid */
697 locked_regb_write(priv, ERXFCON,
698 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
699
700 /* enable MAC receive */
701 locked_regb_write(priv, MACON1,
702 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
703 /* enable automatic padding and CRC operations */
704 if (priv->full_duplex) {
705 locked_regb_write(priv, MACON3,
706 MACON3_PADCFG0 | MACON3_TXCRCEN |
707 MACON3_FRMLNEN | MACON3_FULDPX);
708 /* set inter-frame gap (non-back-to-back) */
709 locked_regb_write(priv, MAIPGL, 0x12);
710 /* set inter-frame gap (back-to-back) */
711 locked_regb_write(priv, MABBIPG, 0x15);
712 } else {
713 locked_regb_write(priv, MACON3,
714 MACON3_PADCFG0 | MACON3_TXCRCEN |
715 MACON3_FRMLNEN);
716 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
717 /* set inter-frame gap (non-back-to-back) */
718 locked_regw_write(priv, MAIPGL, 0x0C12);
719 /* set inter-frame gap (back-to-back) */
720 locked_regb_write(priv, MABBIPG, 0x12);
721 }
722 /*
723 * MACLCON1 (default)
724 * MACLCON2 (default)
725 * Set the maximum packet size which the controller will accept
726 */
727 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
728
729 /* Configure LEDs */
730 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
731 return 0;
732
733 if (priv->full_duplex) {
734 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
735 return 0;
736 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
737 return 0;
738 } else {
739 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
740 return 0;
741 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
742 return 0;
743 }
744 if (netif_msg_hw(priv))
745 enc28j60_dump_regs(priv, "Hw initialized.");
746
747 return 1;
748}
749
750static void enc28j60_hw_enable(struct enc28j60_net *priv)
751{
David Brownell7dac6f82008-06-12 21:38:06 -0700752 /* enable interrupts */
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100753 if (netif_msg_hw(priv))
754 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700755 __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100756
757 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
758
759 mutex_lock(&priv->lock);
760 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
761 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
762 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
763 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
764
765 /* enable receive logic */
766 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
767 priv->hw_enable = true;
768 mutex_unlock(&priv->lock);
769}
770
771static void enc28j60_hw_disable(struct enc28j60_net *priv)
772{
773 mutex_lock(&priv->lock);
774 /* disable interrutps and packet reception */
775 nolock_regb_write(priv, EIE, 0x00);
776 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
777 priv->hw_enable = false;
778 mutex_unlock(&priv->lock);
779}
780
781static int
782enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
783{
784 struct enc28j60_net *priv = netdev_priv(ndev);
785 int ret = 0;
786
787 if (!priv->hw_enable) {
David Brownell7dac6f82008-06-12 21:38:06 -0700788 /* link is in low power mode now; duplex setting
789 * will take effect on next enc28j60_hw_init().
790 */
791 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100792 priv->full_duplex = (duplex == DUPLEX_FULL);
David Brownell7dac6f82008-06-12 21:38:06 -0700793 else {
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100794 if (netif_msg_link(priv))
795 dev_warn(&ndev->dev,
796 "unsupported link setting\n");
797 ret = -EOPNOTSUPP;
798 }
799 } else {
800 if (netif_msg_link(priv))
801 dev_warn(&ndev->dev, "Warning: hw must be disabled "
802 "to set link mode\n");
803 ret = -EBUSY;
804 }
805 return ret;
806}
807
808/*
809 * Read the Transmit Status Vector
810 */
811static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
812{
813 int endptr;
814
815 endptr = locked_regw_read(priv, ETXNDL);
816 if (netif_msg_hw(priv))
817 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
818 endptr + 1);
Stefan Weilfca540a2011-01-31 20:56:54 -0800819 enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100820}
821
822static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
823 u8 tsv[TSV_SIZE])
824{
825 u16 tmp1, tmp2;
826
827 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
828 tmp1 = tsv[1];
829 tmp1 <<= 8;
830 tmp1 |= tsv[0];
831
832 tmp2 = tsv[5];
833 tmp2 <<= 8;
834 tmp2 |= tsv[4];
835
836 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
837 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
838 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
839 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
840 TSV_GETBIT(tsv, TSV_TXCRCERROR),
841 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
842 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
843 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
844 "PacketDefer: %d, ExDefer: %d\n",
845 TSV_GETBIT(tsv, TSV_TXMULTICAST),
846 TSV_GETBIT(tsv, TSV_TXBROADCAST),
847 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
848 TSV_GETBIT(tsv, TSV_TXEXDEFER));
849 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
850 "Giant: %d, Underrun: %d\n",
851 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
852 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
853 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
854 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
855 "BackPressApp: %d, VLanTagFrame: %d\n",
856 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
857 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
858 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
859 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
860}
861
862/*
863 * Receive Status vector
864 */
865static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
866 u16 pk_ptr, int len, u16 sts)
867{
868 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
869 msg, pk_ptr);
870 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
871 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
872 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
873 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
874 RSV_GETBIT(sts, RSV_CRCERROR),
875 RSV_GETBIT(sts, RSV_LENCHECKERR),
876 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
877 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
878 "LongDropEvent: %d, CarrierEvent: %d\n",
879 RSV_GETBIT(sts, RSV_RXMULTICAST),
880 RSV_GETBIT(sts, RSV_RXBROADCAST),
881 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
882 RSV_GETBIT(sts, RSV_CARRIEREV));
883 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
884 " UnknownOp: %d, VLanTagFrame: %d\n",
885 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
886 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
887 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
888 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
889}
890
891static void dump_packet(const char *msg, int len, const char *data)
892{
893 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
894 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
895 data, len, true);
896}
897
898/*
899 * Hardware receive function.
900 * Read the buffer memory, update the FIFO pointer to free the buffer,
901 * check the status vector and decrement the packet counter.
902 */
903static void enc28j60_hw_rx(struct net_device *ndev)
904{
905 struct enc28j60_net *priv = netdev_priv(ndev);
906 struct sk_buff *skb = NULL;
907 u16 erxrdpt, next_packet, rxstat;
908 u8 rsv[RSV_SIZE];
909 int len;
910
911 if (netif_msg_rx_status(priv))
912 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
913 priv->next_pk_ptr);
914
915 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
916 if (netif_msg_rx_err(priv))
917 dev_err(&ndev->dev,
918 "%s() Invalid packet address!! 0x%04x\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700919 __func__, priv->next_pk_ptr);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100920 /* packet address corrupted: reset RX logic */
921 mutex_lock(&priv->lock);
922 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
923 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
924 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
925 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
926 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
927 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
928 mutex_unlock(&priv->lock);
929 ndev->stats.rx_errors++;
930 return;
931 }
932 /* Read next packet pointer and rx status vector */
933 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
934
935 next_packet = rsv[1];
936 next_packet <<= 8;
937 next_packet |= rsv[0];
938
939 len = rsv[3];
940 len <<= 8;
941 len |= rsv[2];
942
943 rxstat = rsv[5];
944 rxstat <<= 8;
945 rxstat |= rsv[4];
946
947 if (netif_msg_rx_status(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700948 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100949
Baruch Siach22692012009-01-04 16:23:01 -0800950 if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100951 if (netif_msg_rx_err(priv))
952 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
953 ndev->stats.rx_errors++;
954 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
955 ndev->stats.rx_crc_errors++;
956 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
957 ndev->stats.rx_frame_errors++;
Baruch Siach22692012009-01-04 16:23:01 -0800958 if (len > MAX_FRAMELEN)
959 ndev->stats.rx_over_errors++;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100960 } else {
Pradeep A Dalvic056b732012-02-05 02:50:38 +0000961 skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100962 if (!skb) {
963 if (netif_msg_rx_err(priv))
964 dev_err(&ndev->dev,
965 "out of memory for Rx'd frame\n");
966 ndev->stats.rx_dropped++;
967 } else {
David Brownell02ff05c2008-03-05 18:51:19 -0800968 skb_reserve(skb, NET_IP_ALIGN);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100969 /* copy the packet from the receive buffer */
Baruch Siach5176da72008-12-02 05:07:01 +0000970 enc28j60_mem_read(priv,
971 rx_packet_start(priv->next_pk_ptr),
972 len, skb_put(skb, len));
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100973 if (netif_msg_pktdata(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700974 dump_packet(__func__, skb->len, skb->data);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100975 skb->protocol = eth_type_trans(skb, ndev);
976 /* update statistics */
977 ndev->stats.rx_packets++;
978 ndev->stats.rx_bytes += len;
Baruch Siach2c413a62008-12-15 20:18:52 +0000979 netif_rx_ni(skb);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100980 }
981 }
982 /*
983 * Move the RX read pointer to the start of the next
984 * received packet.
985 * This frees the memory we just read out
986 */
987 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
988 if (netif_msg_hw(priv))
989 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -0700990 __func__, erxrdpt);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +0100991
992 mutex_lock(&priv->lock);
993 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
994#ifdef CONFIG_ENC28J60_WRITEVERIFY
995 if (netif_msg_drv(priv)) {
996 u16 reg;
997 reg = nolock_regw_read(priv, ERXRDPTL);
998 if (reg != erxrdpt)
999 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001000 "error (0x%04x - 0x%04x)\n", __func__,
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001001 reg, erxrdpt);
1002 }
1003#endif
1004 priv->next_pk_ptr = next_packet;
1005 /* we are done with this packet, decrement the packet counter */
1006 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1007 mutex_unlock(&priv->lock);
1008}
1009
1010/*
1011 * Calculate free space in RxFIFO
1012 */
1013static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1014{
1015 int epkcnt, erxst, erxnd, erxwr, erxrd;
1016 int free_space;
1017
1018 mutex_lock(&priv->lock);
1019 epkcnt = nolock_regb_read(priv, EPKTCNT);
1020 if (epkcnt >= 255)
1021 free_space = -1;
1022 else {
1023 erxst = nolock_regw_read(priv, ERXSTL);
1024 erxnd = nolock_regw_read(priv, ERXNDL);
1025 erxwr = nolock_regw_read(priv, ERXWRPTL);
1026 erxrd = nolock_regw_read(priv, ERXRDPTL);
1027
1028 if (erxwr > erxrd)
1029 free_space = (erxnd - erxst) - (erxwr - erxrd);
1030 else if (erxwr == erxrd)
1031 free_space = (erxnd - erxst);
1032 else
1033 free_space = erxrd - erxwr - 1;
1034 }
1035 mutex_unlock(&priv->lock);
1036 if (netif_msg_rx_status(priv))
1037 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001038 __func__, free_space);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001039 return free_space;
1040}
1041
1042/*
1043 * Access the PHY to determine link status
1044 */
1045static void enc28j60_check_link_status(struct net_device *ndev)
1046{
1047 struct enc28j60_net *priv = netdev_priv(ndev);
1048 u16 reg;
1049 int duplex;
1050
1051 reg = enc28j60_phy_read(priv, PHSTAT2);
1052 if (netif_msg_hw(priv))
1053 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001054 "PHSTAT2: %04x\n", __func__,
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001055 enc28j60_phy_read(priv, PHSTAT1), reg);
1056 duplex = reg & PHSTAT2_DPXSTAT;
1057
1058 if (reg & PHSTAT2_LSTAT) {
1059 netif_carrier_on(ndev);
1060 if (netif_msg_ifup(priv))
1061 dev_info(&ndev->dev, "link up - %s\n",
1062 duplex ? "Full duplex" : "Half duplex");
1063 } else {
1064 if (netif_msg_ifdown(priv))
1065 dev_info(&ndev->dev, "link down\n");
1066 netif_carrier_off(ndev);
1067 }
1068}
1069
1070static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1071{
1072 struct enc28j60_net *priv = netdev_priv(ndev);
1073
1074 if (err)
1075 ndev->stats.tx_errors++;
1076 else
1077 ndev->stats.tx_packets++;
1078
1079 if (priv->tx_skb) {
1080 if (!err)
1081 ndev->stats.tx_bytes += priv->tx_skb->len;
1082 dev_kfree_skb(priv->tx_skb);
1083 priv->tx_skb = NULL;
1084 }
1085 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1086 netif_wake_queue(ndev);
1087}
1088
1089/*
1090 * RX handler
1091 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1092 * check EPKTCNT is the suggested workaround.
1093 * We don't need to clear interrupt flag, automatically done when
1094 * enc28j60_hw_rx() decrements the packet counter.
1095 * Returns how many packet processed.
1096 */
1097static int enc28j60_rx_interrupt(struct net_device *ndev)
1098{
1099 struct enc28j60_net *priv = netdev_priv(ndev);
1100 int pk_counter, ret;
1101
1102 pk_counter = locked_regb_read(priv, EPKTCNT);
1103 if (pk_counter && netif_msg_intr(priv))
1104 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1105 if (pk_counter > priv->max_pk_counter) {
1106 /* update statistics */
1107 priv->max_pk_counter = pk_counter;
1108 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1109 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1110 priv->max_pk_counter);
1111 }
1112 ret = pk_counter;
1113 while (pk_counter-- > 0)
1114 enc28j60_hw_rx(ndev);
1115
1116 return ret;
1117}
1118
1119static void enc28j60_irq_work_handler(struct work_struct *work)
1120{
1121 struct enc28j60_net *priv =
1122 container_of(work, struct enc28j60_net, irq_work);
1123 struct net_device *ndev = priv->netdev;
1124 int intflags, loop;
1125
1126 if (netif_msg_intr(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001127 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001128 /* disable further interrupts */
1129 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1130
1131 do {
1132 loop = 0;
1133 intflags = locked_regb_read(priv, EIR);
1134 /* DMA interrupt handler (not currently used) */
1135 if ((intflags & EIR_DMAIF) != 0) {
1136 loop++;
1137 if (netif_msg_intr(priv))
1138 printk(KERN_DEBUG DRV_NAME
1139 ": intDMA(%d)\n", loop);
1140 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1141 }
1142 /* LINK changed handler */
1143 if ((intflags & EIR_LINKIF) != 0) {
1144 loop++;
1145 if (netif_msg_intr(priv))
1146 printk(KERN_DEBUG DRV_NAME
1147 ": intLINK(%d)\n", loop);
1148 enc28j60_check_link_status(ndev);
1149 /* read PHIR to clear the flag */
1150 enc28j60_phy_read(priv, PHIR);
1151 }
1152 /* TX complete handler */
1153 if ((intflags & EIR_TXIF) != 0) {
1154 bool err = false;
1155 loop++;
1156 if (netif_msg_intr(priv))
1157 printk(KERN_DEBUG DRV_NAME
1158 ": intTX(%d)\n", loop);
1159 priv->tx_retry_count = 0;
1160 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1161 if (netif_msg_tx_err(priv))
1162 dev_err(&ndev->dev,
1163 "Tx Error (aborted)\n");
1164 err = true;
1165 }
1166 if (netif_msg_tx_done(priv)) {
1167 u8 tsv[TSV_SIZE];
1168 enc28j60_read_tsv(priv, tsv);
1169 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1170 }
1171 enc28j60_tx_clear(ndev, err);
1172 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1173 }
1174 /* TX Error handler */
1175 if ((intflags & EIR_TXERIF) != 0) {
1176 u8 tsv[TSV_SIZE];
1177
1178 loop++;
1179 if (netif_msg_intr(priv))
1180 printk(KERN_DEBUG DRV_NAME
1181 ": intTXErr(%d)\n", loop);
1182 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1183 enc28j60_read_tsv(priv, tsv);
1184 if (netif_msg_tx_err(priv))
1185 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1186 /* Reset TX logic */
1187 mutex_lock(&priv->lock);
1188 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1189 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1190 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1191 mutex_unlock(&priv->lock);
1192 /* Transmit Late collision check for retransmit */
1193 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1194 if (netif_msg_tx_err(priv))
1195 printk(KERN_DEBUG DRV_NAME
1196 ": LateCollision TXErr (%d)\n",
1197 priv->tx_retry_count);
1198 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1199 locked_reg_bfset(priv, ECON1,
1200 ECON1_TXRTS);
1201 else
1202 enc28j60_tx_clear(ndev, true);
1203 } else
1204 enc28j60_tx_clear(ndev, true);
1205 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1206 }
1207 /* RX Error handler */
1208 if ((intflags & EIR_RXERIF) != 0) {
1209 loop++;
1210 if (netif_msg_intr(priv))
1211 printk(KERN_DEBUG DRV_NAME
1212 ": intRXErr(%d)\n", loop);
1213 /* Check free FIFO space to flag RX overrun */
1214 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1215 if (netif_msg_rx_err(priv))
1216 printk(KERN_DEBUG DRV_NAME
1217 ": RX Overrun\n");
1218 ndev->stats.rx_dropped++;
1219 }
1220 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1221 }
1222 /* RX handler */
1223 if (enc28j60_rx_interrupt(ndev))
1224 loop++;
1225 } while (loop);
1226
1227 /* re-enable interrupts */
1228 locked_reg_bfset(priv, EIE, EIE_INTIE);
1229 if (netif_msg_intr(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001230 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001231}
1232
1233/*
1234 * Hardware transmit function.
1235 * Fill the buffer memory and send the contents of the transmit buffer
1236 * onto the network
1237 */
1238static void enc28j60_hw_tx(struct enc28j60_net *priv)
1239{
1240 if (netif_msg_tx_queued(priv))
1241 printk(KERN_DEBUG DRV_NAME
1242 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1243
1244 if (netif_msg_pktdata(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001245 dump_packet(__func__,
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001246 priv->tx_skb->len, priv->tx_skb->data);
1247 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1248
1249#ifdef CONFIG_ENC28J60_WRITEVERIFY
1250 /* readback and verify written data */
1251 if (netif_msg_drv(priv)) {
1252 int test_len, k;
1253 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1254 int okflag;
1255
1256 test_len = priv->tx_skb->len;
1257 if (test_len > sizeof(test_buf))
1258 test_len = sizeof(test_buf);
1259
1260 /* + 1 to skip control byte */
1261 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1262 okflag = 1;
1263 for (k = 0; k < test_len; k++) {
1264 if (priv->tx_skb->data[k] != test_buf[k]) {
1265 printk(KERN_DEBUG DRV_NAME
1266 ": Error, %d location differ: "
1267 "0x%02x-0x%02x\n", k,
1268 priv->tx_skb->data[k], test_buf[k]);
1269 okflag = 0;
1270 }
1271 }
1272 if (!okflag)
1273 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1274 "verify ERROR!\n");
1275 }
1276#endif
1277 /* set TX request flag */
1278 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1279}
1280
Stephen Hemminger613573252009-08-31 19:50:58 +00001281static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1282 struct net_device *dev)
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001283{
1284 struct enc28j60_net *priv = netdev_priv(dev);
1285
1286 if (netif_msg_tx_queued(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001287 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001288
1289 /* If some error occurs while trying to transmit this
1290 * packet, you should return '1' from this function.
1291 * In such a case you _may not_ do anything to the
1292 * SKB, it is still owned by the network queueing
1293 * layer when an error is returned. This means you
1294 * may not modify any SKB fields, you may not free
1295 * the SKB, etc.
1296 */
1297 netif_stop_queue(dev);
1298
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001299 /* Remember the skb for deferred processing */
1300 priv->tx_skb = skb;
1301 schedule_work(&priv->tx_work);
1302
Patrick McHardy6ed10652009-06-23 06:03:08 +00001303 return NETDEV_TX_OK;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001304}
1305
1306static void enc28j60_tx_work_handler(struct work_struct *work)
1307{
1308 struct enc28j60_net *priv =
1309 container_of(work, struct enc28j60_net, tx_work);
1310
1311 /* actual delivery of data */
1312 enc28j60_hw_tx(priv);
1313}
1314
1315static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1316{
1317 struct enc28j60_net *priv = dev_id;
1318
1319 /*
1320 * Can't do anything in interrupt context because we need to
1321 * block (spi_sync() is blocking) so fire of the interrupt
1322 * handling workqueue.
1323 * Remember that we access enc28j60 registers through SPI bus
1324 * via spi_sync() call.
1325 */
1326 schedule_work(&priv->irq_work);
1327
1328 return IRQ_HANDLED;
1329}
1330
1331static void enc28j60_tx_timeout(struct net_device *ndev)
1332{
1333 struct enc28j60_net *priv = netdev_priv(ndev);
1334
1335 if (netif_msg_timer(priv))
1336 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1337
1338 ndev->stats.tx_errors++;
1339 /* can't restart safely under softirq */
1340 schedule_work(&priv->restart_work);
1341}
1342
1343/*
1344 * Open/initialize the board. This is called (in the current kernel)
1345 * sometime after booting when the 'ifconfig' program is run.
1346 *
1347 * This routine should set everything up anew at each open, even
1348 * registers that "should" only need to be set once at boot, so that
1349 * there is non-reboot way to recover if something goes wrong.
1350 */
1351static int enc28j60_net_open(struct net_device *dev)
1352{
1353 struct enc28j60_net *priv = netdev_priv(dev);
1354
1355 if (netif_msg_drv(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001356 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001357
1358 if (!is_valid_ether_addr(dev->dev_addr)) {
Johannes Berge1749612008-10-27 15:59:26 -07001359 if (netif_msg_ifup(priv))
1360 dev_err(&dev->dev, "invalid MAC address %pM\n",
1361 dev->dev_addr);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001362 return -EADDRNOTAVAIL;
1363 }
David Brownell7dac6f82008-06-12 21:38:06 -07001364 /* Reset the hardware here (and take it out of low power mode) */
1365 enc28j60_lowpower(priv, false);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001366 enc28j60_hw_disable(priv);
1367 if (!enc28j60_hw_init(priv)) {
1368 if (netif_msg_ifup(priv))
1369 dev_err(&dev->dev, "hw_reset() failed\n");
1370 return -EINVAL;
1371 }
1372 /* Update the MAC address (in case user has changed it) */
1373 enc28j60_set_hw_macaddr(dev);
1374 /* Enable interrupts */
1375 enc28j60_hw_enable(priv);
1376 /* check link status */
1377 enc28j60_check_link_status(dev);
1378 /* We are now ready to accept transmit requests from
1379 * the queueing layer of the networking.
1380 */
1381 netif_start_queue(dev);
1382
1383 return 0;
1384}
1385
1386/* The inverse routine to net_open(). */
1387static int enc28j60_net_close(struct net_device *dev)
1388{
1389 struct enc28j60_net *priv = netdev_priv(dev);
1390
1391 if (netif_msg_drv(priv))
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001392 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001393
1394 enc28j60_hw_disable(priv);
David Brownell7dac6f82008-06-12 21:38:06 -07001395 enc28j60_lowpower(priv, true);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001396 netif_stop_queue(dev);
1397
1398 return 0;
1399}
1400
1401/*
1402 * Set or clear the multicast filter for this adapter
1403 * num_addrs == -1 Promiscuous mode, receive all packets
1404 * num_addrs == 0 Normal mode, filter out multicast packets
1405 * num_addrs > 0 Multicast mode, receive normal and MC packets
1406 */
1407static void enc28j60_set_multicast_list(struct net_device *dev)
1408{
1409 struct enc28j60_net *priv = netdev_priv(dev);
1410 int oldfilter = priv->rxfilter;
1411
1412 if (dev->flags & IFF_PROMISC) {
1413 if (netif_msg_link(priv))
1414 dev_info(&dev->dev, "promiscuous mode\n");
1415 priv->rxfilter = RXFILTER_PROMISC;
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00001416 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001417 if (netif_msg_link(priv))
1418 dev_info(&dev->dev, "%smulticast mode\n",
1419 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1420 priv->rxfilter = RXFILTER_MULTI;
1421 } else {
1422 if (netif_msg_link(priv))
1423 dev_info(&dev->dev, "normal mode\n");
1424 priv->rxfilter = RXFILTER_NORMAL;
1425 }
1426
1427 if (oldfilter != priv->rxfilter)
1428 schedule_work(&priv->setrx_work);
1429}
1430
1431static void enc28j60_setrx_work_handler(struct work_struct *work)
1432{
1433 struct enc28j60_net *priv =
1434 container_of(work, struct enc28j60_net, setrx_work);
1435
1436 if (priv->rxfilter == RXFILTER_PROMISC) {
1437 if (netif_msg_drv(priv))
1438 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1439 locked_regb_write(priv, ERXFCON, 0x00);
1440 } else if (priv->rxfilter == RXFILTER_MULTI) {
1441 if (netif_msg_drv(priv))
1442 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1443 locked_regb_write(priv, ERXFCON,
1444 ERXFCON_UCEN | ERXFCON_CRCEN |
1445 ERXFCON_BCEN | ERXFCON_MCEN);
1446 } else {
1447 if (netif_msg_drv(priv))
1448 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1449 locked_regb_write(priv, ERXFCON,
1450 ERXFCON_UCEN | ERXFCON_CRCEN |
1451 ERXFCON_BCEN);
1452 }
1453}
1454
1455static void enc28j60_restart_work_handler(struct work_struct *work)
1456{
1457 struct enc28j60_net *priv =
1458 container_of(work, struct enc28j60_net, restart_work);
1459 struct net_device *ndev = priv->netdev;
1460 int ret;
1461
1462 rtnl_lock();
1463 if (netif_running(ndev)) {
1464 enc28j60_net_close(ndev);
1465 ret = enc28j60_net_open(ndev);
1466 if (unlikely(ret)) {
1467 dev_info(&ndev->dev, " could not restart %d\n", ret);
1468 dev_close(ndev);
1469 }
1470 }
1471 rtnl_unlock();
1472}
1473
1474/* ......................... ETHTOOL SUPPORT ........................... */
1475
1476static void
1477enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1478{
1479 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1480 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1481 strlcpy(info->bus_info,
Kay Sieversfb28ad32008-11-10 13:55:14 -08001482 dev_name(dev->dev.parent), sizeof(info->bus_info));
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001483}
1484
1485static int
1486enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1487{
1488 struct enc28j60_net *priv = netdev_priv(dev);
1489
1490 cmd->transceiver = XCVR_INTERNAL;
1491 cmd->supported = SUPPORTED_10baseT_Half
1492 | SUPPORTED_10baseT_Full
1493 | SUPPORTED_TP;
David Decotigny70739492011-04-27 18:32:40 +00001494 ethtool_cmd_speed_set(cmd, SPEED_10);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001495 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1496 cmd->port = PORT_TP;
1497 cmd->autoneg = AUTONEG_DISABLE;
1498
1499 return 0;
1500}
1501
1502static int
1503enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1504{
David Decotigny25db0332011-04-27 18:32:39 +00001505 return enc28j60_setlink(dev, cmd->autoneg,
1506 ethtool_cmd_speed(cmd), cmd->duplex);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001507}
1508
1509static u32 enc28j60_get_msglevel(struct net_device *dev)
1510{
1511 struct enc28j60_net *priv = netdev_priv(dev);
1512 return priv->msg_enable;
1513}
1514
1515static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1516{
1517 struct enc28j60_net *priv = netdev_priv(dev);
1518 priv->msg_enable = val;
1519}
1520
1521static const struct ethtool_ops enc28j60_ethtool_ops = {
1522 .get_settings = enc28j60_get_settings,
1523 .set_settings = enc28j60_set_settings,
1524 .get_drvinfo = enc28j60_get_drvinfo,
1525 .get_msglevel = enc28j60_get_msglevel,
1526 .set_msglevel = enc28j60_set_msglevel,
1527};
1528
1529static int enc28j60_chipset_init(struct net_device *dev)
1530{
1531 struct enc28j60_net *priv = netdev_priv(dev);
1532
1533 return enc28j60_hw_init(priv);
1534}
1535
Stephen Hemminger1f5ec792009-01-07 17:30:09 -08001536static const struct net_device_ops enc28j60_netdev_ops = {
1537 .ndo_open = enc28j60_net_open,
1538 .ndo_stop = enc28j60_net_close,
1539 .ndo_start_xmit = enc28j60_send_packet,
Jiri Pirkoafc4b132011-08-16 06:29:01 +00001540 .ndo_set_rx_mode = enc28j60_set_multicast_list,
Stephen Hemminger1f5ec792009-01-07 17:30:09 -08001541 .ndo_set_mac_address = enc28j60_set_mac_address,
1542 .ndo_tx_timeout = enc28j60_tx_timeout,
1543 .ndo_change_mtu = eth_change_mtu,
1544 .ndo_validate_addr = eth_validate_addr,
1545};
1546
Bill Pemberton19d1b442012-12-03 09:23:16 -05001547static int enc28j60_probe(struct spi_device *spi)
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001548{
1549 struct net_device *dev;
1550 struct enc28j60_net *priv;
1551 int ret = 0;
1552
1553 if (netif_msg_drv(&debug))
1554 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1555 DRV_VERSION);
1556
1557 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1558 if (!dev) {
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001559 ret = -ENOMEM;
1560 goto error_alloc;
1561 }
1562 priv = netdev_priv(dev);
1563
1564 priv->netdev = dev; /* priv to netdev reference */
1565 priv->spi = spi; /* priv to spi reference */
1566 priv->msg_enable = netif_msg_init(debug.msg_enable,
1567 ENC28J60_MSG_DEFAULT);
1568 mutex_init(&priv->lock);
1569 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1570 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1571 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1572 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
Jingoo Han57437562013-04-05 20:36:11 +00001573 spi_set_drvdata(spi, priv); /* spi to priv reference */
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001574 SET_NETDEV_DEV(dev, &spi->dev);
1575
1576 if (!enc28j60_chipset_init(dev)) {
1577 if (netif_msg_probe(priv))
1578 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1579 ret = -EIO;
1580 goto error_irq;
1581 }
Danny Kukawka7ce5d222012-02-15 06:45:40 +00001582 eth_hw_addr_random(dev);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001583 enc28j60_set_hw_macaddr(dev);
1584
David Brownellc7b7b042008-07-24 17:47:56 -07001585 /* Board setup must set the relevant edge trigger type;
1586 * level triggers won't currently work.
1587 */
1588 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001589 if (ret < 0) {
1590 if (netif_msg_probe(priv))
1591 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1592 "(ret = %d)\n", spi->irq, ret);
1593 goto error_irq;
1594 }
1595
1596 dev->if_port = IF_PORT_10BASET;
1597 dev->irq = spi->irq;
Stephen Hemminger1f5ec792009-01-07 17:30:09 -08001598 dev->netdev_ops = &enc28j60_netdev_ops;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001599 dev->watchdog_timeo = TX_TIMEOUT;
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00001600 dev->ethtool_ops = &enc28j60_ethtool_ops;
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001601
David Brownell7dac6f82008-06-12 21:38:06 -07001602 enc28j60_lowpower(priv, true);
1603
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001604 ret = register_netdev(dev);
1605 if (ret) {
1606 if (netif_msg_probe(priv))
1607 dev_err(&spi->dev, "register netdev " DRV_NAME
1608 " failed (ret = %d)\n", ret);
1609 goto error_register;
1610 }
1611 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1612
1613 return 0;
1614
1615error_register:
1616 free_irq(spi->irq, priv);
1617error_irq:
1618 free_netdev(dev);
1619error_alloc:
1620 return ret;
1621}
1622
Bill Pemberton19d1b442012-12-03 09:23:16 -05001623static int enc28j60_remove(struct spi_device *spi)
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001624{
Jingoo Han57437562013-04-05 20:36:11 +00001625 struct enc28j60_net *priv = spi_get_drvdata(spi);
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001626
1627 if (netif_msg_drv(priv))
1628 printk(KERN_DEBUG DRV_NAME ": remove\n");
1629
1630 unregister_netdev(priv->netdev);
1631 free_irq(spi->irq, priv);
1632 free_netdev(priv->netdev);
1633
1634 return 0;
1635}
1636
1637static struct spi_driver enc28j60_driver = {
1638 .driver = {
1639 .name = DRV_NAME,
David Brownell6fd65882008-06-12 21:36:24 -07001640 },
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001641 .probe = enc28j60_probe,
Bill Pemberton19d1b442012-12-03 09:23:16 -05001642 .remove = enc28j60_remove,
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001643};
1644
1645static int __init enc28j60_init(void)
1646{
David Brownell7dac6f82008-06-12 21:38:06 -07001647 msec20_to_jiffies = msecs_to_jiffies(20);
1648
Claudio Lanconelli3ec9c112008-01-14 11:00:28 +01001649 return spi_register_driver(&enc28j60_driver);
1650}
1651
1652module_init(enc28j60_init);
1653
1654static void __exit enc28j60_exit(void)
1655{
1656 spi_unregister_driver(&enc28j60_driver);
1657}
1658
1659module_exit(enc28j60_exit);
1660
1661MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1662MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1663MODULE_LICENSE("GPL");
1664module_param_named(debug, debug.msg_enable, int, 0);
1665MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
Anton Vorontsove0626e32009-09-22 16:46:08 -07001666MODULE_ALIAS("spi:" DRV_NAME);