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gerrit-public.fairphone.software / kernel / msm-4.9 / 297295ae6653af1356dd35a8edc411e2715aec57 / . / drivers / scsi / ips.h
blob: b726dcc424b190f214d571a828339c125f28c6c4 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*****************************************************************************/
2/* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 1999 IBM Corporation */
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]9/* Copyright (C) 2003 Adaptec, Inc. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/*****************************************************************************/
49
50#ifndef _IPS_H_
51 #define _IPS_H_
52
Olaf Hering733482e2005-11-08 21:34:55 -0800[diff] [blame]53#include <linux/version.h>
Andrew Morton297295a2006-11-08 19:56:26 -0800[diff] [blame^]54#include <linux/nmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]55 #include <asm/uaccess.h>
56 #include <asm/io.h>
57
58 /*
59 * Some handy macros
60 */
61 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) || defined CONFIG_HIGHIO
62 #define IPS_HIGHIO
63 #endif
64
65 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
66 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
67 #define IPS_IS_TROMBONE(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
68 (ha->revision_id >= IPS_REVID_TROMBONE32) && \
69 (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
70 #define IPS_IS_CLARINET(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
71 (ha->revision_id >= IPS_REVID_CLARINETP1) && \
72 (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
73 #define IPS_IS_MORPHEUS(ha) (ha->device_id == IPS_DEVICEID_MORPHEUS)
74 #define IPS_IS_MARCO(ha) (ha->device_id == IPS_DEVICEID_MARCO)
75 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
76 (IPS_IS_TROMBONE(ha) && \
77 (ips_force_i2o))) ? 1 : 0)
78 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
79 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
80 (ips_force_memio))) ? 1 : 0)
81
82 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
83 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
84 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
85 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
86
87 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,4)
88 #define pci_set_dma_mask(dev,mask) ( mask > 0xffffffff ? 1:0 )
89 #define scsi_set_pci_device(sh,dev) (0)
90 #endif
91
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]92 #ifndef IRQ_NONE
93 typedef void irqreturn_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]94 #define IRQ_NONE
95 #define IRQ_HANDLED
96 #define IRQ_RETVAL(x)
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]97 #endif
98
99 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]100 #define IPS_REGISTER_HOSTS(SHT) scsi_register_module(MODULE_SCSI_HA,SHT)
101 #define IPS_UNREGISTER_HOSTS(SHT) scsi_unregister_module(MODULE_SCSI_HA,SHT)
102 #define IPS_ADD_HOST(shost,device)
103 #define IPS_REMOVE_HOST(shost)
104 #define IPS_SCSI_SET_DEVICE(sh,ha) scsi_set_pci_device(sh, (ha)->pcidev)
105 #define IPS_PRINTK(level, pcidev, format, arg...) \
106 printk(level "%s %s:" format , "ips" , \
107 (pcidev)->slot_name , ## arg)
108 #define scsi_host_alloc(sh,size) scsi_register(sh,size)
109 #define scsi_host_put(sh) scsi_unregister(sh)
110 #else
111 #define IPS_REGISTER_HOSTS(SHT) (!ips_detect(SHT))
112 #define IPS_UNREGISTER_HOSTS(SHT)
113 #define IPS_ADD_HOST(shost,device) do { scsi_add_host(shost,device); scsi_scan_host(shost); } while (0)
114 #define IPS_REMOVE_HOST(shost) scsi_remove_host(shost)
Christoph Hellwig12413192005-06-11 01:05:01 +0200[diff] [blame]115 #define IPS_SCSI_SET_DEVICE(sh,ha) do { } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]116 #define IPS_PRINTK(level, pcidev, format, arg...) \
117 dev_printk(level , &((pcidev)->dev) , format , ## arg)
118 #endif
119
Andrew Morton297295a2006-11-08 19:56:26 -0800[diff] [blame^]120 #define MDELAY(n) \
121 do { \
122 mdelay(n); \
123 touch_nmi_watchdog(); \
124 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]125
126 #ifndef min
127 #define min(x,y) ((x) < (y) ? x : y)
128 #endif
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]129
130 #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */
131 #define __iomem
132 #endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]133
134 #define pci_dma_hi32(a) ((a >> 16) >> 16)
135 #define pci_dma_lo32(a) (a & 0xffffffff)
136
137 #if (BITS_PER_LONG > 32) || (defined CONFIG_HIGHMEM64G && defined IPS_HIGHIO)
138 #define IPS_ENABLE_DMA64 (1)
139 #else
140 #define IPS_ENABLE_DMA64 (0)
141 #endif
142
143 /*
144 * Adapter address map equates
145 */
146 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
147 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
148 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
149 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
150 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
151 #define IPS_REG_SQER 0x28 /* Status Q End Reg */
152 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
153 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
154 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
155 #define IPS_REG_CBSP 0x07 /* CBSP register */
156 #define IPS_REG_FLAP 0x18 /* Flash address port */
157 #define IPS_REG_FLDP 0x1C /* Flash data port */
158 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
159 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
160 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
161 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
162 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
163 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
164 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
165 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
166
167 /*
168 * Adapter register bit equates
169 */
170 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
171 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
172 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
173 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
174 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
175 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
176 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
177 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
178 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
179 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
180 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
181 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
182 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
183 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
184
185 /*
186 * Adapter Command ID Equates
187 */
188 #define IPS_CMD_GET_LD_INFO 0x19
189 #define IPS_CMD_GET_SUBSYS 0x40
190 #define IPS_CMD_READ_CONF 0x38
191 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
192 #define IPS_CMD_READ 0x02
193 #define IPS_CMD_WRITE 0x03
194 #define IPS_CMD_FFDC 0xD7
195 #define IPS_CMD_ENQUIRY 0x05
196 #define IPS_CMD_FLUSH 0x0A
197 #define IPS_CMD_READ_SG 0x82
198 #define IPS_CMD_WRITE_SG 0x83
199 #define IPS_CMD_DCDB 0x04
200 #define IPS_CMD_DCDB_SG 0x84
201 #define IPS_CMD_EXTENDED_DCDB 0x95
202 #define IPS_CMD_EXTENDED_DCDB_SG 0x96
203 #define IPS_CMD_CONFIG_SYNC 0x58
204 #define IPS_CMD_ERROR_TABLE 0x17
205 #define IPS_CMD_DOWNLOAD 0x20
206 #define IPS_CMD_RW_BIOSFW 0x22
207 #define IPS_CMD_GET_VERSION_INFO 0xC6
208 #define IPS_CMD_RESET_CHANNEL 0x1A
209
210 /*
211 * Adapter Equates
212 */
213 #define IPS_CSL 0xFF
214 #define IPS_POCL 0x30
215 #define IPS_NORM_STATE 0x00
216 #define IPS_MAX_ADAPTER_TYPES 3
217 #define IPS_MAX_ADAPTERS 16
218 #define IPS_MAX_IOCTL 1
219 #define IPS_MAX_IOCTL_QUEUE 8
220 #define IPS_MAX_QUEUE 128
221 #define IPS_BLKSIZE 512
222 #define IPS_MAX_SG 17
223 #define IPS_MAX_LD 8
224 #define IPS_MAX_CHANNELS 4
225 #define IPS_MAX_TARGETS 15
226 #define IPS_MAX_CHUNKS 16
227 #define IPS_MAX_CMDS 128
228 #define IPS_MAX_XFER 0x10000
229 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
230 #define IPS_MAX_POST_BYTES 0x02
231 #define IPS_MAX_CONFIG_BYTES 0x02
232 #define IPS_GOOD_POST_STATUS 0x80
233 #define IPS_SEM_TIMEOUT 2000
234 #define IPS_IOCTL_COMMAND 0x0D
235 #define IPS_INTR_ON 0
236 #define IPS_INTR_IORL 1
237 #define IPS_FFDC 99
238 #define IPS_ADAPTER_ID 0xF
239 #define IPS_VENDORID_IBM 0x1014
240 #define IPS_VENDORID_ADAPTEC 0x9005
241 #define IPS_DEVICEID_COPPERHEAD 0x002E
242 #define IPS_DEVICEID_MORPHEUS 0x01BD
243 #define IPS_DEVICEID_MARCO 0x0250
244 #define IPS_SUBDEVICEID_4M 0x01BE
245 #define IPS_SUBDEVICEID_4L 0x01BF
246 #define IPS_SUBDEVICEID_4MX 0x0208
247 #define IPS_SUBDEVICEID_4LX 0x020E
248 #define IPS_SUBDEVICEID_5I2 0x0259
249 #define IPS_SUBDEVICEID_5I1 0x0258
250 #define IPS_SUBDEVICEID_6M 0x0279
251 #define IPS_SUBDEVICEID_6I 0x028C
252 #define IPS_SUBDEVICEID_7k 0x028E
253 #define IPS_SUBDEVICEID_7M 0x028F
254 #define IPS_IOCTL_SIZE 8192
255 #define IPS_STATUS_SIZE 4
256 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
257 #define IPS_IMAGE_SIZE 500 * 1024
258 #define IPS_MEMMAP_SIZE 128
259 #define IPS_ONE_MSEC 1
260 #define IPS_ONE_SEC 1000
261
262 /*
263 * Geometry Settings
264 */
265 #define IPS_COMP_HEADS 128
266 #define IPS_COMP_SECTORS 32
267 #define IPS_NORM_HEADS 254
268 #define IPS_NORM_SECTORS 63
269
270 /*
271 * Adapter Basic Status Codes
272 */
273 #define IPS_BASIC_STATUS_MASK 0xFF
274 #define IPS_GSC_STATUS_MASK 0x0F
275 #define IPS_CMD_SUCCESS 0x00
276 #define IPS_CMD_RECOVERED_ERROR 0x01
277 #define IPS_INVAL_OPCO 0x03
278 #define IPS_INVAL_CMD_BLK 0x04
279 #define IPS_INVAL_PARM_BLK 0x05
280 #define IPS_BUSY 0x08
281 #define IPS_CMD_CMPLT_WERROR 0x0C
282 #define IPS_LD_ERROR 0x0D
283 #define IPS_CMD_TIMEOUT 0x0E
284 #define IPS_PHYS_DRV_ERROR 0x0F
285
286 /*
287 * Adapter Extended Status Equates
288 */
289 #define IPS_ERR_SEL_TO 0xF0
290 #define IPS_ERR_OU_RUN 0xF2
291 #define IPS_ERR_HOST_RESET 0xF7
292 #define IPS_ERR_DEV_RESET 0xF8
293 #define IPS_ERR_RECOVERY 0xFC
294 #define IPS_ERR_CKCOND 0xFF
295
296 /*
297 * Operating System Defines
298 */
299 #define IPS_OS_WINDOWS_NT 0x01
300 #define IPS_OS_NETWARE 0x02
301 #define IPS_OS_OPENSERVER 0x03
302 #define IPS_OS_UNIXWARE 0x04
303 #define IPS_OS_SOLARIS 0x05
304 #define IPS_OS_OS2 0x06
305 #define IPS_OS_LINUX 0x07
306 #define IPS_OS_FREEBSD 0x08
307
308 /*
309 * Adapter Revision ID's
310 */
311 #define IPS_REVID_SERVERAID 0x02
312 #define IPS_REVID_NAVAJO 0x03
313 #define IPS_REVID_SERVERAID2 0x04
314 #define IPS_REVID_CLARINETP1 0x05
315 #define IPS_REVID_CLARINETP2 0x07
316 #define IPS_REVID_CLARINETP3 0x0D
317 #define IPS_REVID_TROMBONE32 0x0F
318 #define IPS_REVID_TROMBONE64 0x10
319
320 /*
321 * NVRAM Page 5 Adapter Defines
322 */
323 #define IPS_ADTYPE_SERVERAID 0x01
324 #define IPS_ADTYPE_SERVERAID2 0x02
325 #define IPS_ADTYPE_NAVAJO 0x03
326 #define IPS_ADTYPE_KIOWA 0x04
327 #define IPS_ADTYPE_SERVERAID3 0x05
328 #define IPS_ADTYPE_SERVERAID3L 0x06
329 #define IPS_ADTYPE_SERVERAID4H 0x07
330 #define IPS_ADTYPE_SERVERAID4M 0x08
331 #define IPS_ADTYPE_SERVERAID4L 0x09
332 #define IPS_ADTYPE_SERVERAID4MX 0x0A
333 #define IPS_ADTYPE_SERVERAID4LX 0x0B
334 #define IPS_ADTYPE_SERVERAID5I2 0x0C
335 #define IPS_ADTYPE_SERVERAID5I1 0x0D
336 #define IPS_ADTYPE_SERVERAID6M 0x0E
337 #define IPS_ADTYPE_SERVERAID6I 0x0F
338 #define IPS_ADTYPE_SERVERAID7t 0x10
339 #define IPS_ADTYPE_SERVERAID7k 0x11
340 #define IPS_ADTYPE_SERVERAID7M 0x12
341
342 /*
343 * Adapter Command/Status Packet Definitions
344 */
345 #define IPS_SUCCESS 0x01 /* Successfully completed */
346 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
347 #define IPS_FAILURE 0x04 /* Completed with Error */
348
349 /*
350 * Logical Drive Equates
351 */
352 #define IPS_LD_OFFLINE 0x02
353 #define IPS_LD_OKAY 0x03
354 #define IPS_LD_FREE 0x00
355 #define IPS_LD_SYS 0x06
356 #define IPS_LD_CRS 0x24
357
358 /*
359 * DCDB Table Equates
360 */
361 #define IPS_NO_DISCONNECT 0x00
362 #define IPS_DISCONNECT_ALLOWED 0x80
363 #define IPS_NO_AUTO_REQSEN 0x40
364 #define IPS_DATA_NONE 0x00
365 #define IPS_DATA_UNK 0x00
366 #define IPS_DATA_IN 0x01
367 #define IPS_DATA_OUT 0x02
368 #define IPS_TRANSFER64K 0x08
369 #define IPS_NOTIMEOUT 0x00
370 #define IPS_TIMEOUT10 0x10
371 #define IPS_TIMEOUT60 0x20
372 #define IPS_TIMEOUT20M 0x30
373
374 /*
375 * SCSI Inquiry Data Flags
376 */
377 #define IPS_SCSI_INQ_TYPE_DASD 0x00
378 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
379 #define IPS_SCSI_INQ_LU_CONNECTED 0x00
380 #define IPS_SCSI_INQ_RD_REV2 0x02
381 #define IPS_SCSI_INQ_REV2 0x02
382 #define IPS_SCSI_INQ_REV3 0x03
383 #define IPS_SCSI_INQ_Address16 0x01
384 #define IPS_SCSI_INQ_Address32 0x02
385 #define IPS_SCSI_INQ_MedChanger 0x08
386 #define IPS_SCSI_INQ_MultiPort 0x10
387 #define IPS_SCSI_INQ_EncServ 0x40
388 #define IPS_SCSI_INQ_SoftReset 0x01
389 #define IPS_SCSI_INQ_CmdQue 0x02
390 #define IPS_SCSI_INQ_Linked 0x08
391 #define IPS_SCSI_INQ_Sync 0x10
392 #define IPS_SCSI_INQ_WBus16 0x20
393 #define IPS_SCSI_INQ_WBus32 0x40
394 #define IPS_SCSI_INQ_RelAdr 0x80
395
396 /*
397 * SCSI Request Sense Data Flags
398 */
399 #define IPS_SCSI_REQSEN_VALID 0x80
400 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
401 #define IPS_SCSI_REQSEN_NO_SENSE 0x00
402
403 /*
404 * SCSI Mode Page Equates
405 */
406 #define IPS_SCSI_MP3_SoftSector 0x01
407 #define IPS_SCSI_MP3_HardSector 0x02
408 #define IPS_SCSI_MP3_Removeable 0x04
409 #define IPS_SCSI_MP3_AllocateSurface 0x08
410
411 /*
412 * HA Flags
413 */
414
415 #define IPS_HA_ENH_SG 0x1
416
417 /*
418 * SCB Flags
419 */
420 #define IPS_SCB_MAP_SG 0x00008
421 #define IPS_SCB_MAP_SINGLE 0X00010
422
423 /*
424 * Passthru stuff
425 */
426 #define IPS_COPPUSRCMD (('C'<<8) | 65)
427 #define IPS_COPPIOCCMD (('C'<<8) | 66)
428 #define IPS_NUMCTRLS (('C'<<8) | 68)
429 #define IPS_CTRLINFO (('C'<<8) | 69)
430
431 /* flashing defines */
432 #define IPS_FW_IMAGE 0x00
433 #define IPS_BIOS_IMAGE 0x01
434 #define IPS_WRITE_FW 0x01
435 #define IPS_WRITE_BIOS 0x02
436 #define IPS_ERASE_BIOS 0x03
437 #define IPS_BIOS_HEADER 0xC0
438
439 /* time oriented stuff */
440 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
441 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
442
443 #define IPS_SECS_MIN 60
444 #define IPS_SECS_HOUR 3600
445 #define IPS_SECS_8HOURS 28800
446 #define IPS_SECS_DAY 86400
447 #define IPS_DAYS_NORMAL_YEAR 365
448 #define IPS_DAYS_LEAP_YEAR 366
449 #define IPS_EPOCH_YEAR 1970
450
451 /*
452 * Scsi_Host Template
453 */
454#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
455 static int ips_proc24_info(char *, char **, off_t, int, int, int);
Christoph Hellwigf64a1812005-10-31 18:32:08 +0100[diff] [blame]456 static void ips_select_queue_depth(struct Scsi_Host *, struct scsi_device *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]457 static int ips_biosparam(Disk *disk, kdev_t dev, int geom[]);
458#else
459 static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
460 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
461 sector_t capacity, int geom[]);
Christoph Hellwigf64a1812005-10-31 18:32:08 +0100[diff] [blame]462 static int ips_slave_configure(struct scsi_device *SDptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]463#endif
464
465/*
466 * Raid Command Formats
467 */
468typedef struct {
469 uint8_t op_code;
470 uint8_t command_id;
471 uint8_t log_drv;
472 uint8_t sg_count;
473 uint32_t lba;
474 uint32_t sg_addr;
475 uint16_t sector_count;
476 uint8_t segment_4G;
477 uint8_t enhanced_sg;
478 uint32_t ccsar;
479 uint32_t cccr;
480} IPS_IO_CMD, *PIPS_IO_CMD;
481
482typedef struct {
483 uint8_t op_code;
484 uint8_t command_id;
485 uint16_t reserved;
486 uint32_t reserved2;
487 uint32_t buffer_addr;
488 uint32_t reserved3;
489 uint32_t ccsar;
490 uint32_t cccr;
491} IPS_LD_CMD, *PIPS_LD_CMD;
492
493typedef struct {
494 uint8_t op_code;
495 uint8_t command_id;
496 uint8_t reserved;
497 uint8_t reserved2;
498 uint32_t reserved3;
499 uint32_t buffer_addr;
500 uint32_t reserved4;
501} IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
502
503typedef struct {
504 uint8_t op_code;
505 uint8_t command_id;
506 uint8_t channel;
507 uint8_t reserved3;
508 uint8_t reserved4;
509 uint8_t reserved5;
510 uint8_t reserved6;
511 uint8_t reserved7;
512 uint8_t reserved8;
513 uint8_t reserved9;
514 uint8_t reserved10;
515 uint8_t reserved11;
516 uint8_t reserved12;
517 uint8_t reserved13;
518 uint8_t reserved14;
519 uint8_t adapter_flag;
520} IPS_RESET_CMD, *PIPS_RESET_CMD;
521
522typedef struct {
523 uint8_t op_code;
524 uint8_t command_id;
525 uint16_t reserved;
526 uint32_t reserved2;
527 uint32_t dcdb_address;
528 uint16_t reserved3;
529 uint8_t segment_4G;
530 uint8_t enhanced_sg;
531 uint32_t ccsar;
532 uint32_t cccr;
533} IPS_DCDB_CMD, *PIPS_DCDB_CMD;
534
535typedef struct {
536 uint8_t op_code;
537 uint8_t command_id;
538 uint8_t channel;
539 uint8_t source_target;
540 uint32_t reserved;
541 uint32_t reserved2;
542 uint32_t reserved3;
543 uint32_t ccsar;
544 uint32_t cccr;
545} IPS_CS_CMD, *PIPS_CS_CMD;
546
547typedef struct {
548 uint8_t op_code;
549 uint8_t command_id;
550 uint8_t log_drv;
551 uint8_t control;
552 uint32_t reserved;
553 uint32_t reserved2;
554 uint32_t reserved3;
555 uint32_t ccsar;
556 uint32_t cccr;
557} IPS_US_CMD, *PIPS_US_CMD;
558
559typedef struct {
560 uint8_t op_code;
561 uint8_t command_id;
562 uint8_t reserved;
563 uint8_t state;
564 uint32_t reserved2;
565 uint32_t reserved3;
566 uint32_t reserved4;
567 uint32_t ccsar;
568 uint32_t cccr;
569} IPS_FC_CMD, *PIPS_FC_CMD;
570
571typedef struct {
572 uint8_t op_code;
573 uint8_t command_id;
574 uint8_t reserved;
575 uint8_t desc;
576 uint32_t reserved2;
577 uint32_t buffer_addr;
578 uint32_t reserved3;
579 uint32_t ccsar;
580 uint32_t cccr;
581} IPS_STATUS_CMD, *PIPS_STATUS_CMD;
582
583typedef struct {
584 uint8_t op_code;
585 uint8_t command_id;
586 uint8_t page;
587 uint8_t write;
588 uint32_t reserved;
589 uint32_t buffer_addr;
590 uint32_t reserved2;
591 uint32_t ccsar;
592 uint32_t cccr;
593} IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
594
595typedef struct
596{
597 uint8_t op_code;
598 uint8_t command_id;
599 uint16_t reserved;
600 uint32_t count;
601 uint32_t buffer_addr;
602 uint32_t reserved2;
603} IPS_VERSION_INFO, *PIPS_VERSION_INFO;
604
605typedef struct {
606 uint8_t op_code;
607 uint8_t command_id;
608 uint8_t reset_count;
609 uint8_t reset_type;
610 uint8_t second;
611 uint8_t minute;
612 uint8_t hour;
613 uint8_t day;
614 uint8_t reserved1[4];
615 uint8_t month;
616 uint8_t yearH;
617 uint8_t yearL;
618 uint8_t reserved2;
619} IPS_FFDC_CMD, *PIPS_FFDC_CMD;
620
621typedef struct {
622 uint8_t op_code;
623 uint8_t command_id;
624 uint8_t type;
625 uint8_t direction;
626 uint32_t count;
627 uint32_t buffer_addr;
628 uint8_t total_packets;
629 uint8_t packet_num;
630 uint16_t reserved;
631} IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
632
633typedef struct {
634 uint8_t op_code;
635 uint8_t command_id;
636 uint8_t type;
637 uint8_t direction;
638 uint32_t count;
639 uint32_t buffer_addr;
640 uint32_t offset;
641} IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
642
643typedef union {
644 IPS_IO_CMD basic_io;
645 IPS_LD_CMD logical_info;
646 IPS_IOCTL_CMD ioctl_info;
647 IPS_DCDB_CMD dcdb;
648 IPS_CS_CMD config_sync;
649 IPS_US_CMD unlock_stripe;
650 IPS_FC_CMD flush_cache;
651 IPS_STATUS_CMD status;
652 IPS_NVRAM_CMD nvram;
653 IPS_FFDC_CMD ffdc;
654 IPS_FLASHFW_CMD flashfw;
655 IPS_FLASHBIOS_CMD flashbios;
656 IPS_VERSION_INFO version_info;
657 IPS_RESET_CMD reset;
658} IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
659
660typedef struct {
661 uint8_t logical_id;
662 uint8_t reserved;
663 uint8_t raid_level;
664 uint8_t state;
665 uint32_t sector_count;
666} IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
667
668typedef struct {
669 uint8_t no_of_log_drive;
670 uint8_t reserved[3];
671 IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
672} IPS_LD_INFO, *PIPS_LD_INFO;
673
674typedef struct {
675 uint8_t device_address;
676 uint8_t cmd_attribute;
677 uint16_t transfer_length;
678 uint32_t buffer_pointer;
679 uint8_t cdb_length;
680 uint8_t sense_length;
681 uint8_t sg_count;
682 uint8_t reserved;
683 uint8_t scsi_cdb[12];
684 uint8_t sense_info[64];
685 uint8_t scsi_status;
686 uint8_t reserved2[3];
687} IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
688
689typedef struct {
690 uint8_t device_address;
691 uint8_t cmd_attribute;
692 uint8_t cdb_length;
693 uint8_t reserved_for_LUN;
694 uint32_t transfer_length;
695 uint32_t buffer_pointer;
696 uint16_t sg_count;
697 uint8_t sense_length;
698 uint8_t scsi_status;
699 uint32_t reserved;
700 uint8_t scsi_cdb[16];
701 uint8_t sense_info[56];
702} IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
703
704typedef union {
705 struct {
706 volatile uint8_t reserved;
707 volatile uint8_t command_id;
708 volatile uint8_t basic_status;
709 volatile uint8_t extended_status;
710 } fields;
711
712 volatile uint32_t value;
713} IPS_STATUS, *PIPS_STATUS;
714
715typedef struct {
716 IPS_STATUS status[IPS_MAX_CMDS + 1];
717 volatile PIPS_STATUS p_status_start;
718 volatile PIPS_STATUS p_status_end;
719 volatile PIPS_STATUS p_status_tail;
720 volatile uint32_t hw_status_start;
721 volatile uint32_t hw_status_tail;
722} IPS_ADAPTER, *PIPS_ADAPTER;
723
724typedef struct {
725 uint8_t ucLogDriveCount;
726 uint8_t ucMiscFlag;
727 uint8_t ucSLTFlag;
728 uint8_t ucBSTFlag;
729 uint8_t ucPwrChgCnt;
730 uint8_t ucWrongAdrCnt;
731 uint8_t ucUnidentCnt;
732 uint8_t ucNVramDevChgCnt;
733 uint8_t CodeBlkVersion[8];
734 uint8_t BootBlkVersion[8];
735 uint32_t ulDriveSize[IPS_MAX_LD];
736 uint8_t ucConcurrentCmdCount;
737 uint8_t ucMaxPhysicalDevices;
738 uint16_t usFlashRepgmCount;
739 uint8_t ucDefunctDiskCount;
740 uint8_t ucRebuildFlag;
741 uint8_t ucOfflineLogDrvCount;
742 uint8_t ucCriticalDrvCount;
743 uint16_t usConfigUpdateCount;
744 uint8_t ucBlkFlag;
745 uint8_t reserved;
746 uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
747} IPS_ENQ, *PIPS_ENQ;
748
749typedef struct {
750 uint8_t ucInitiator;
751 uint8_t ucParameters;
752 uint8_t ucMiscFlag;
753 uint8_t ucState;
754 uint32_t ulBlockCount;
755 uint8_t ucDeviceId[28];
756} IPS_DEVSTATE, *PIPS_DEVSTATE;
757
758typedef struct {
759 uint8_t ucChn;
760 uint8_t ucTgt;
761 uint16_t ucReserved;
762 uint32_t ulStartSect;
763 uint32_t ulNoOfSects;
764} IPS_CHUNK, *PIPS_CHUNK;
765
766typedef struct {
767 uint16_t ucUserField;
768 uint8_t ucState;
769 uint8_t ucRaidCacheParam;
770 uint8_t ucNoOfChunkUnits;
771 uint8_t ucStripeSize;
772 uint8_t ucParams;
773 uint8_t ucReserved;
774 uint32_t ulLogDrvSize;
775 IPS_CHUNK chunk[IPS_MAX_CHUNKS];
776} IPS_LD, *PIPS_LD;
777
778typedef struct {
779 uint8_t board_disc[8];
780 uint8_t processor[8];
781 uint8_t ucNoChanType;
782 uint8_t ucNoHostIntType;
783 uint8_t ucCompression;
784 uint8_t ucNvramType;
785 uint32_t ulNvramSize;
786} IPS_HARDWARE, *PIPS_HARDWARE;
787
788typedef struct {
789 uint8_t ucLogDriveCount;
790 uint8_t ucDateD;
791 uint8_t ucDateM;
792 uint8_t ucDateY;
793 uint8_t init_id[4];
794 uint8_t host_id[12];
795 uint8_t time_sign[8];
796 uint32_t UserOpt;
797 uint16_t user_field;
798 uint8_t ucRebuildRate;
799 uint8_t ucReserve;
800 IPS_HARDWARE hardware_disc;
801 IPS_LD logical_drive[IPS_MAX_LD];
802 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
803 uint8_t reserved[512];
804} IPS_CONF, *PIPS_CONF;
805
806typedef struct {
807 uint32_t signature;
808 uint8_t reserved1;
809 uint8_t adapter_slot;
810 uint16_t adapter_type;
811 uint8_t ctrl_bios[8];
812 uint8_t versioning; /* 1 = Versioning Supported, else 0 */
813 uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */
814 uint8_t reserved2;
815 uint8_t operating_system;
816 uint8_t driver_high[4];
817 uint8_t driver_low[4];
818 uint8_t BiosCompatibilityID[8];
819 uint8_t ReservedForOS2[8];
820 uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */
821 uint8_t bios_low[4];
822 uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */
823 uint8_t Filler[60];
824} IPS_NVRAM_P5, *PIPS_NVRAM_P5;
825
826/*--------------------------------------------------------------------------*/
827/* Data returned from a GetVersion Command */
828/*--------------------------------------------------------------------------*/
829
830 /* SubSystem Parameter[4] */
831#define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
832
833typedef struct
834{
835 uint32_t revision;
836 uint8_t bootBlkVersion[32];
837 uint8_t bootBlkAttributes[4];
838 uint8_t codeBlkVersion[32];
839 uint8_t biosVersion[32];
840 uint8_t biosAttributes[4];
841 uint8_t compatibilityId[32];
842 uint8_t reserved[4];
843} IPS_VERSION_DATA;
844
845
846typedef struct _IPS_SUBSYS {
847 uint32_t param[128];
848} IPS_SUBSYS, *PIPS_SUBSYS;
849
850/**
851 ** SCSI Structures
852 **/
853
854/*
855 * Inquiry Data Format
856 */
857typedef struct {
858 uint8_t DeviceType;
859 uint8_t DeviceTypeQualifier;
860 uint8_t Version;
861 uint8_t ResponseDataFormat;
862 uint8_t AdditionalLength;
863 uint8_t Reserved;
864 uint8_t Flags[2];
865 uint8_t VendorId[8];
866 uint8_t ProductId[16];
867 uint8_t ProductRevisionLevel[4];
868 uint8_t Reserved2; /* Provides NULL terminator to name */
869} IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
870
871/*
872 * Read Capacity Data Format
873 */
874typedef struct {
875 uint32_t lba;
876 uint32_t len;
877} IPS_SCSI_CAPACITY;
878
879/*
880 * Request Sense Data Format
881 */
882typedef struct {
883 uint8_t ResponseCode;
884 uint8_t SegmentNumber;
885 uint8_t Flags;
886 uint8_t Information[4];
887 uint8_t AdditionalLength;
888 uint8_t CommandSpecific[4];
889 uint8_t AdditionalSenseCode;
890 uint8_t AdditionalSenseCodeQual;
891 uint8_t FRUCode;
892 uint8_t SenseKeySpecific[3];
893} IPS_SCSI_REQSEN;
894
895/*
896 * Sense Data Format - Page 3
897 */
898typedef struct {
899 uint8_t PageCode;
900 uint8_t PageLength;
901 uint16_t TracksPerZone;
902 uint16_t AltSectorsPerZone;
903 uint16_t AltTracksPerZone;
904 uint16_t AltTracksPerVolume;
905 uint16_t SectorsPerTrack;
906 uint16_t BytesPerSector;
907 uint16_t Interleave;
908 uint16_t TrackSkew;
909 uint16_t CylinderSkew;
910 uint8_t flags;
911 uint8_t reserved[3];
912} IPS_SCSI_MODE_PAGE3;
913
914/*
915 * Sense Data Format - Page 4
916 */
917typedef struct {
918 uint8_t PageCode;
919 uint8_t PageLength;
920 uint16_t CylindersHigh;
921 uint8_t CylindersLow;
922 uint8_t Heads;
923 uint16_t WritePrecompHigh;
924 uint8_t WritePrecompLow;
925 uint16_t ReducedWriteCurrentHigh;
926 uint8_t ReducedWriteCurrentLow;
927 uint16_t StepRate;
928 uint16_t LandingZoneHigh;
929 uint8_t LandingZoneLow;
930 uint8_t flags;
931 uint8_t RotationalOffset;
932 uint8_t Reserved;
933 uint16_t MediumRotationRate;
934 uint8_t Reserved2[2];
935} IPS_SCSI_MODE_PAGE4;
936
937/*
938 * Sense Data Format - Page 8
939 */
940typedef struct {
941 uint8_t PageCode;
942 uint8_t PageLength;
943 uint8_t flags;
944 uint8_t RetentPrio;
945 uint16_t DisPrefetchLen;
946 uint16_t MinPrefetchLen;
947 uint16_t MaxPrefetchLen;
948 uint16_t MaxPrefetchCeiling;
949} IPS_SCSI_MODE_PAGE8;
950
951/*
952 * Sense Data Format - Block Descriptor (DASD)
953 */
954typedef struct {
955 uint32_t NumberOfBlocks;
956 uint8_t DensityCode;
957 uint16_t BlockLengthHigh;
958 uint8_t BlockLengthLow;
959} IPS_SCSI_MODE_PAGE_BLKDESC;
960
961/*
962 * Sense Data Format - Mode Page Header
963 */
964typedef struct {
965 uint8_t DataLength;
966 uint8_t MediumType;
967 uint8_t Reserved;
968 uint8_t BlockDescLength;
969} IPS_SCSI_MODE_PAGE_HEADER;
970
971typedef struct {
972 IPS_SCSI_MODE_PAGE_HEADER hdr;
973 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
974
975 union {
976 IPS_SCSI_MODE_PAGE3 pg3;
977 IPS_SCSI_MODE_PAGE4 pg4;
978 IPS_SCSI_MODE_PAGE8 pg8;
979 } pdata;
980} IPS_SCSI_MODE_PAGE_DATA;
981
982/*
983 * Scatter Gather list format
984 */
985typedef struct ips_sglist {
986 uint32_t address;
987 uint32_t length;
988} IPS_STD_SG_LIST;
989
990typedef struct ips_enh_sglist {
991 uint32_t address_lo;
992 uint32_t address_hi;
993 uint32_t length;
994 uint32_t reserved;
995} IPS_ENH_SG_LIST;
996
997typedef union {
998 void *list;
999 IPS_STD_SG_LIST *std_list;
1000 IPS_ENH_SG_LIST *enh_list;
1001} IPS_SG_LIST;
1002
1003typedef struct _IPS_INFOSTR {
1004 char *buffer;
1005 int length;
1006 int offset;
1007 int pos;
1008 int localpos;
1009} IPS_INFOSTR;
1010
1011typedef struct {
1012 char *option_name;
1013 int *option_flag;
1014 int option_value;
1015} IPS_OPTION;
1016
1017/*
1018 * Status Info
1019 */
1020typedef struct ips_stat {
1021 uint32_t residue_len;
1022 void *scb_addr;
1023 uint8_t padding[12 - sizeof(void *)];
1024} ips_stat_t;
1025
1026/*
1027 * SCB Queue Format
1028 */
1029typedef struct ips_scb_queue {
1030 struct ips_scb *head;
1031 struct ips_scb *tail;
1032 int count;
1033} ips_scb_queue_t;
1034
1035/*
1036 * Wait queue_format
1037 */
1038typedef struct ips_wait_queue {
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]1039 struct scsi_cmnd *head;
1040 struct scsi_cmnd *tail;
1041 int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1042} ips_wait_queue_t;
1043
1044typedef struct ips_copp_wait_item {
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]1045 struct scsi_cmnd *scsi_cmd;
1046 struct ips_copp_wait_item *next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1047} ips_copp_wait_item_t;
1048
1049typedef struct ips_copp_queue {
1050 struct ips_copp_wait_item *head;
1051 struct ips_copp_wait_item *tail;
1052 int count;
1053} ips_copp_queue_t;
1054
1055/* forward decl for host structure */
1056struct ips_ha;
1057
1058typedef struct {
1059 int (*reset)(struct ips_ha *);
1060 int (*issue)(struct ips_ha *, struct ips_scb *);
1061 int (*isinit)(struct ips_ha *);
1062 int (*isintr)(struct ips_ha *);
1063 int (*init)(struct ips_ha *);
1064 int (*erasebios)(struct ips_ha *);
1065 int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
1066 int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
1067 void (*statinit)(struct ips_ha *);
1068 int (*intr)(struct ips_ha *);
1069 void (*enableint)(struct ips_ha *);
1070 uint32_t (*statupd)(struct ips_ha *);
1071} ips_hw_func_t;
1072
1073typedef struct ips_ha {
1074 uint8_t ha_id[IPS_MAX_CHANNELS+1];
1075 uint32_t dcdb_active[IPS_MAX_CHANNELS];
1076 uint32_t io_addr; /* Base I/O address */
1077 uint8_t irq; /* IRQ for adapter */
1078 uint8_t ntargets; /* Number of targets */
1079 uint8_t nbus; /* Number of buses */
1080 uint8_t nlun; /* Number of Luns */
1081 uint16_t ad_type; /* Adapter type */
1082 uint16_t host_num; /* Adapter number */
1083 uint32_t max_xfer; /* Maximum Xfer size */
1084 uint32_t max_cmds; /* Max concurrent commands */
1085 uint32_t num_ioctl; /* Number of Ioctls */
1086 ips_stat_t sp; /* Status packer pointer */
1087 struct ips_scb *scbs; /* Array of all CCBS */
1088 struct ips_scb *scb_freelist; /* SCB free list */
1089 ips_wait_queue_t scb_waitlist; /* Pending SCB list */
1090 ips_copp_queue_t copp_waitlist; /* Pending PT list */
1091 ips_scb_queue_t scb_activelist; /* Active SCB list */
1092 IPS_IO_CMD *dummy; /* dummy command */
1093 IPS_ADAPTER *adapt; /* Adapter status area */
1094 IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */
1095 dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
1096 IPS_ENQ *enq; /* Adapter Enquiry data */
1097 IPS_CONF *conf; /* Adapter config data */
1098 IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */
1099 IPS_SUBSYS *subsys; /* Subsystem parameters */
1100 char *ioctl_data; /* IOCTL data area */
1101 uint32_t ioctl_datasize; /* IOCTL data size */
1102 uint32_t cmd_in_progress; /* Current command in progress*/
1103 int flags; /* */
1104 uint8_t waitflag; /* are we waiting for cmd */
1105 uint8_t active;
1106 int ioctl_reset; /* IOCTL Requested Reset Flag */
1107 uint16_t reset_count; /* number of resets */
1108 time_t last_ffdc; /* last time we sent ffdc info*/
1109 uint8_t revision_id; /* Revision level */
1110 uint16_t device_id; /* PCI device ID */
1111 uint8_t slot_num; /* PCI Slot Number */
1112 uint16_t subdevice_id; /* Subsystem device ID */
1113 int ioctl_len; /* size of ioctl buffer */
1114 dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/
1115 uint8_t bios_version[8]; /* BIOS Revision */
1116 uint32_t mem_addr; /* Memory mapped address */
1117 uint32_t io_len; /* Size of IO Address */
1118 uint32_t mem_len; /* Size of memory address */
1119 char __iomem *mem_ptr; /* Memory mapped Ptr */
1120 char __iomem *ioremap_ptr;/* ioremapped memory pointer */
1121 ips_hw_func_t func; /* hw function pointers */
1122 struct pci_dev *pcidev; /* PCI device handle */
1123 char *flash_data; /* Save Area for flash data */
1124 int flash_len; /* length of flash buffer */
1125 u32 flash_datasize; /* Save Area for flash data size */
1126 dma_addr_t flash_busaddr; /* dma address of flash buffer*/
1127 dma_addr_t enq_busaddr; /* dma address of enq struct */
1128 uint8_t requires_esl; /* Requires an EraseStripeLock */
1129} ips_ha_t;
1130
1131typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1132
1133/*
1134 * SCB Format
1135 */
1136typedef struct ips_scb {
1137 IPS_HOST_COMMAND cmd;
1138 IPS_DCDB_TABLE dcdb;
1139 uint8_t target_id;
1140 uint8_t bus;
1141 uint8_t lun;
1142 uint8_t cdb[12];
1143 uint32_t scb_busaddr;
1144 uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility
1145 uint32_t timeout;
1146 uint8_t basic_status;
1147 uint8_t extended_status;
1148 uint8_t breakup;
1149 uint8_t sg_break;
1150 uint32_t data_len;
1151 uint32_t sg_len;
1152 uint32_t flags;
1153 uint32_t op_code;
1154 IPS_SG_LIST sg_list;
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]1155 struct scsi_cmnd *scsi_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1156 struct ips_scb *q_next;
1157 ips_scb_callback callback;
1158 uint32_t sg_busaddr;
1159 int sg_count;
1160 dma_addr_t data_busaddr;
1161} ips_scb_t;
1162
1163typedef struct ips_scb_pt {
1164 IPS_HOST_COMMAND cmd;
1165 IPS_DCDB_TABLE dcdb;
1166 uint8_t target_id;
1167 uint8_t bus;
1168 uint8_t lun;
1169 uint8_t cdb[12];
1170 uint32_t scb_busaddr;
1171 uint32_t data_busaddr;
1172 uint32_t timeout;
1173 uint8_t basic_status;
1174 uint8_t extended_status;
1175 uint16_t breakup;
1176 uint32_t data_len;
1177 uint32_t sg_len;
1178 uint32_t flags;
1179 uint32_t op_code;
1180 IPS_SG_LIST *sg_list;
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]1181 struct scsi_cmnd *scsi_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1182 struct ips_scb *q_next;
1183 ips_scb_callback callback;
1184} ips_scb_pt_t;
1185
1186/*
1187 * Passthru Command Format
1188 */
1189typedef struct {
1190 uint8_t CoppID[4];
1191 uint32_t CoppCmd;
1192 uint32_t PtBuffer;
1193 uint8_t *CmdBuffer;
1194 uint32_t CmdBSize;
1195 ips_scb_pt_t CoppCP;
1196 uint32_t TimeOut;
1197 uint8_t BasicStatus;
1198 uint8_t ExtendedStatus;
1199 uint8_t AdapterType;
1200 uint8_t reserved;
1201} ips_passthru_t;
1202
1203#endif
1204
1205/* The Version Information below gets created by SED during the build process. */
1206/* Do not modify the next line; it's what SED is looking for to do the insert. */
1207/* Version Info */
1208/*************************************************************************
1209*
1210* VERSION.H -- version numbers and copyright notices in various formats
1211*
1212*************************************************************************/
1213
1214#define IPS_VER_MAJOR 7
1215#define IPS_VER_MAJOR_STRING "7"
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]1216#define IPS_VER_MINOR 12
1217#define IPS_VER_MINOR_STRING "12"
1218#define IPS_VER_BUILD 02
1219#define IPS_VER_BUILD_STRING "02"
1220#define IPS_VER_STRING "7.12.02"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1221#define IPS_RELEASE_ID 0x00020000
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]1222#define IPS_BUILD_IDENT 761
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1223#define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1224#define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1225#define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1226#define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1227
1228/* Version numbers for various adapters */
1229#define IPS_VER_SERVERAID1 "2.25.01"
1230#define IPS_VER_SERVERAID2 "2.88.13"
1231#define IPS_VER_NAVAJO "2.88.13"
1232#define IPS_VER_SERVERAID3 "6.10.24"
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]1233#define IPS_VER_SERVERAID4H "7.12.02"
1234#define IPS_VER_SERVERAID4MLx "7.12.02"
1235#define IPS_VER_SARASOTA "7.12.02"
1236#define IPS_VER_MARCO "7.12.02"
1237#define IPS_VER_SEBRING "7.12.02"
1238#define IPS_VER_KEYWEST "7.12.02"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1239
1240/* Compatability IDs for various adapters */
1241#define IPS_COMPAT_UNKNOWN ""
1242#define IPS_COMPAT_CURRENT "KW710"
1243#define IPS_COMPAT_SERVERAID1 "2.25.01"
1244#define IPS_COMPAT_SERVERAID2 "2.88.13"
1245#define IPS_COMPAT_NAVAJO "2.88.13"
1246#define IPS_COMPAT_KIOWA "2.88.13"
1247#define IPS_COMPAT_SERVERAID3H "SB610"
1248#define IPS_COMPAT_SERVERAID3L "SB610"
1249#define IPS_COMPAT_SERVERAID4H "KW710"
1250#define IPS_COMPAT_SERVERAID4M "KW710"
1251#define IPS_COMPAT_SERVERAID4L "KW710"
1252#define IPS_COMPAT_SERVERAID4Mx "KW710"
1253#define IPS_COMPAT_SERVERAID4Lx "KW710"
1254#define IPS_COMPAT_SARASOTA "KW710"
1255#define IPS_COMPAT_MARCO "KW710"
1256#define IPS_COMPAT_SEBRING "KW710"
1257#define IPS_COMPAT_TAMPA "KW710"
1258#define IPS_COMPAT_KEYWEST "KW710"
1259#define IPS_COMPAT_BIOS "KW710"
1260
1261#define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1262#define IPS_COMPAT_ID_LENGTH 8
1263
1264#define IPS_DEFINE_COMPAT_TABLE(tablename) \
1265 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1266 IPS_COMPAT_UNKNOWN, \
1267 IPS_COMPAT_SERVERAID1, \
1268 IPS_COMPAT_SERVERAID2, \
1269 IPS_COMPAT_NAVAJO, \
1270 IPS_COMPAT_KIOWA, \
1271 IPS_COMPAT_SERVERAID3H, \
1272 IPS_COMPAT_SERVERAID3L, \
1273 IPS_COMPAT_SERVERAID4H, \
1274 IPS_COMPAT_SERVERAID4M, \
1275 IPS_COMPAT_SERVERAID4L, \
1276 IPS_COMPAT_SERVERAID4Mx, \
1277 IPS_COMPAT_SERVERAID4Lx, \
1278 IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
1279 IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
1280 IPS_COMPAT_MARCO, \
1281 IPS_COMPAT_SEBRING, \
1282 IPS_COMPAT_TAMPA, \
1283 IPS_COMPAT_KEYWEST \
1284 }
1285
1286
1287/*
1288 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1289 * Emacs will notice this stuff at the end of the file and automatically
1290 * adjust the settings for this buffer only. This must remain at the end
1291 * of the file.
1292 * ---------------------------------------------------------------------------
1293 * Local variables:
1294 * c-indent-level: 2
1295 * c-brace-imaginary-offset: 0
1296 * c-brace-offset: -2
1297 * c-argdecl-indent: 2
1298 * c-label-offset: -2
1299 * c-continued-statement-offset: 2
1300 * c-continued-brace-offset: 0
1301 * indent-tabs-mode: nil
1302 * tab-width: 8
1303 * End:
1304 */