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Srikanth Thokala8961def2014-08-20 21:56:02 +05301/*
2 * PCIe host controller driver for Xilinx AXI PCIe Bridge
3 *
4 * Copyright (c) 2012 - 2014 Xilinx, Inc.
5 *
6 * Based on the Tegra PCIe driver
7 *
8 * Bits taken from Synopsys Designware Host controller driver and
9 * ARM PCI Host generic driver.
10 *
11 * This program is free software: you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/msi.h>
23#include <linux/of_address.h>
24#include <linux/of_pci.h>
25#include <linux/of_platform.h>
26#include <linux/of_irq.h>
27#include <linux/pci.h>
28#include <linux/platform_device.h>
29
30/* Register definitions */
31#define XILINX_PCIE_REG_BIR 0x00000130
32#define XILINX_PCIE_REG_IDR 0x00000138
33#define XILINX_PCIE_REG_IMR 0x0000013c
34#define XILINX_PCIE_REG_PSCR 0x00000144
35#define XILINX_PCIE_REG_RPSC 0x00000148
36#define XILINX_PCIE_REG_MSIBASE1 0x0000014c
37#define XILINX_PCIE_REG_MSIBASE2 0x00000150
38#define XILINX_PCIE_REG_RPEFR 0x00000154
39#define XILINX_PCIE_REG_RPIFR1 0x00000158
40#define XILINX_PCIE_REG_RPIFR2 0x0000015c
41
42/* Interrupt registers definitions */
43#define XILINX_PCIE_INTR_LINK_DOWN BIT(0)
44#define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
45#define XILINX_PCIE_INTR_STR_ERR BIT(2)
46#define XILINX_PCIE_INTR_HOT_RESET BIT(3)
47#define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8)
48#define XILINX_PCIE_INTR_CORRECTABLE BIT(9)
49#define XILINX_PCIE_INTR_NONFATAL BIT(10)
50#define XILINX_PCIE_INTR_FATAL BIT(11)
51#define XILINX_PCIE_INTR_INTX BIT(16)
52#define XILINX_PCIE_INTR_MSI BIT(17)
53#define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20)
54#define XILINX_PCIE_INTR_SLV_UNEXP BIT(21)
55#define XILINX_PCIE_INTR_SLV_COMPL BIT(22)
56#define XILINX_PCIE_INTR_SLV_ERRP BIT(23)
57#define XILINX_PCIE_INTR_SLV_CMPABT BIT(24)
58#define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25)
59#define XILINX_PCIE_INTR_MST_DECERR BIT(26)
60#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)
61#define XILINX_PCIE_INTR_MST_ERRP BIT(28)
62#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED
63#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF
64
65/* Root Port Error FIFO Read Register definitions */
66#define XILINX_PCIE_RPEFR_ERR_VALID BIT(18)
67#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
68#define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
69
70/* Root Port Interrupt FIFO Read Register 1 definitions */
71#define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31)
72#define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30)
73#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)
74#define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF
75#define XILINX_PCIE_RPIFR1_INTR_SHIFT 27
76
77/* Bridge Info Register definitions */
78#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)
79#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16
80
81/* Root Port Interrupt FIFO Read Register 2 definitions */
82#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)
83
84/* Root Port Status/control Register definitions */
85#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
86
87/* Phy Status/Control Register definitions */
88#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
89
90/* ECAM definitions */
91#define ECAM_BUS_NUM_SHIFT 20
92#define ECAM_DEV_NUM_SHIFT 12
93
94/* Number of MSI IRQs */
95#define XILINX_NUM_MSI_IRQS 128
96
Srikanth Thokala8961def2014-08-20 21:56:02 +053097/**
98 * struct xilinx_pcie_port - PCIe port information
99 * @reg_base: IO Mapped Register Base
100 * @irq: Interrupt number
101 * @msi_pages: MSI pages
102 * @root_busno: Root Bus number
103 * @dev: Device pointer
104 * @irq_domain: IRQ domain pointer
Srikanth Thokala8961def2014-08-20 21:56:02 +0530105 * @resources: Bus Resources
106 */
107struct xilinx_pcie_port {
108 void __iomem *reg_base;
109 u32 irq;
110 unsigned long msi_pages;
111 u8 root_busno;
112 struct device *dev;
113 struct irq_domain *irq_domain;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530114 struct list_head resources;
115};
116
117static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
118
Srikanth Thokala8961def2014-08-20 21:56:02 +0530119static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
120{
121 return readl(port->reg_base + reg);
122}
123
124static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
125{
126 writel(val, port->reg_base + reg);
127}
128
129static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
130{
131 return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
132 XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
133}
134
135/**
136 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
137 * @port: PCIe port information
138 */
139static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
140{
Arnd Bergmannabc596b2015-01-13 15:20:05 +0100141 unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530142
143 if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
Arnd Bergmannabc596b2015-01-13 15:20:05 +0100144 dev_dbg(port->dev, "Requester ID %lu\n",
Srikanth Thokala8961def2014-08-20 21:56:02 +0530145 val & XILINX_PCIE_RPEFR_REQ_ID);
146 pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
147 XILINX_PCIE_REG_RPEFR);
148 }
149}
150
151/**
152 * xilinx_pcie_valid_device - Check if a valid device is present on bus
153 * @bus: PCI Bus structure
154 * @devfn: device/function
155 *
156 * Return: 'true' on success and 'false' if invalid device is found
157 */
158static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
159{
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530160 struct xilinx_pcie_port *port = bus->sysdata;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530161
162 /* Check if link is up when trying to access downstream ports */
163 if (bus->number != port->root_busno)
164 if (!xilinx_pcie_link_is_up(port))
165 return false;
166
167 /* Only one device down on each root port */
168 if (bus->number == port->root_busno && devfn > 0)
169 return false;
170
171 /*
172 * Do not read more than one device on the bus directly attached
173 * to RC.
174 */
175 if (bus->primary == port->root_busno && devfn > 0)
176 return false;
177
178 return true;
179}
180
181/**
Rob Herring029e2152015-01-09 20:34:50 -0600182 * xilinx_pcie_map_bus - Get configuration base
Srikanth Thokala8961def2014-08-20 21:56:02 +0530183 * @bus: PCI Bus structure
184 * @devfn: Device/function
185 * @where: Offset from base
186 *
187 * Return: Base address of the configuration space needed to be
188 * accessed.
189 */
Rob Herring029e2152015-01-09 20:34:50 -0600190static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
191 unsigned int devfn, int where)
Srikanth Thokala8961def2014-08-20 21:56:02 +0530192{
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530193 struct xilinx_pcie_port *port = bus->sysdata;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530194 int relbus;
195
Rob Herring029e2152015-01-09 20:34:50 -0600196 if (!xilinx_pcie_valid_device(bus, devfn))
197 return NULL;
198
Srikanth Thokala8961def2014-08-20 21:56:02 +0530199 relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
200 (devfn << ECAM_DEV_NUM_SHIFT);
201
202 return port->reg_base + relbus + where;
203}
204
Srikanth Thokala8961def2014-08-20 21:56:02 +0530205/* PCIe operations */
206static struct pci_ops xilinx_pcie_ops = {
Rob Herring029e2152015-01-09 20:34:50 -0600207 .map_bus = xilinx_pcie_map_bus,
208 .read = pci_generic_config_read,
209 .write = pci_generic_config_write,
Srikanth Thokala8961def2014-08-20 21:56:02 +0530210};
211
212/* MSI functions */
213
214/**
215 * xilinx_pcie_destroy_msi - Free MSI number
216 * @irq: IRQ to be freed
217 */
218static void xilinx_pcie_destroy_msi(unsigned int irq)
219{
Srikanth Thokala8961def2014-08-20 21:56:02 +0530220 struct msi_desc *msi;
221 struct xilinx_pcie_port *port;
222
Jiang Liue39758e2015-07-09 16:00:43 +0800223 if (!test_bit(irq, msi_irq_in_use)) {
224 msi = irq_get_msi_desc(irq);
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530225 port = msi_desc_to_pci_sysdata(msi);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530226 dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
Jiang Liue39758e2015-07-09 16:00:43 +0800227 } else {
Srikanth Thokala8961def2014-08-20 21:56:02 +0530228 clear_bit(irq, msi_irq_in_use);
Jiang Liue39758e2015-07-09 16:00:43 +0800229 }
Srikanth Thokala8961def2014-08-20 21:56:02 +0530230}
231
232/**
233 * xilinx_pcie_assign_msi - Allocate MSI number
234 * @port: PCIe port structure
235 *
236 * Return: A valid IRQ on success and error value on failure.
237 */
238static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
239{
240 int pos;
241
242 pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
243 if (pos < XILINX_NUM_MSI_IRQS)
244 set_bit(pos, msi_irq_in_use);
245 else
246 return -ENOSPC;
247
248 return pos;
249}
250
251/**
252 * xilinx_msi_teardown_irq - Destroy the MSI
253 * @chip: MSI Chip descriptor
254 * @irq: MSI IRQ to destroy
255 */
Yijing Wangc2791b82014-11-11 17:45:45 -0700256static void xilinx_msi_teardown_irq(struct msi_controller *chip,
257 unsigned int irq)
Srikanth Thokala8961def2014-08-20 21:56:02 +0530258{
259 xilinx_pcie_destroy_msi(irq);
260}
261
262/**
263 * xilinx_pcie_msi_setup_irq - Setup MSI request
264 * @chip: MSI chip pointer
265 * @pdev: PCIe device pointer
266 * @desc: MSI descriptor pointer
267 *
268 * Return: '0' on success and error value on failure
269 */
Yijing Wangc2791b82014-11-11 17:45:45 -0700270static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
Srikanth Thokala8961def2014-08-20 21:56:02 +0530271 struct pci_dev *pdev,
272 struct msi_desc *desc)
273{
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530274 struct xilinx_pcie_port *port = pdev->bus->sysdata;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530275 unsigned int irq;
276 int hwirq;
277 struct msi_msg msg;
278 phys_addr_t msg_addr;
279
280 hwirq = xilinx_pcie_assign_msi(port);
Dan Carpenterf9dd0ce2014-09-09 15:11:50 +0300281 if (hwirq < 0)
282 return hwirq;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530283
284 irq = irq_create_mapping(port->irq_domain, hwirq);
285 if (!irq)
286 return -EINVAL;
287
288 irq_set_msi_desc(irq, desc);
289
290 msg_addr = virt_to_phys((void *)port->msi_pages);
291
292 msg.address_hi = 0;
293 msg.address_lo = msg_addr;
294 msg.data = irq;
295
Jiang Liu83a18912014-11-09 23:10:34 +0800296 pci_write_msi_msg(irq, &msg);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530297
298 return 0;
299}
300
301/* MSI Chip Descriptor */
Yijing Wangc2791b82014-11-11 17:45:45 -0700302static struct msi_controller xilinx_pcie_msi_chip = {
Srikanth Thokala8961def2014-08-20 21:56:02 +0530303 .setup_irq = xilinx_pcie_msi_setup_irq,
304 .teardown_irq = xilinx_msi_teardown_irq,
305};
306
307/* HW Interrupt Chip Descriptor */
308static struct irq_chip xilinx_msi_irq_chip = {
309 .name = "Xilinx PCIe MSI",
Thomas Gleixner280510f2014-11-23 12:23:20 +0100310 .irq_enable = pci_msi_unmask_irq,
311 .irq_disable = pci_msi_mask_irq,
312 .irq_mask = pci_msi_mask_irq,
313 .irq_unmask = pci_msi_unmask_irq,
Srikanth Thokala8961def2014-08-20 21:56:02 +0530314};
315
316/**
317 * xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
318 * @domain: IRQ domain
319 * @irq: Virtual IRQ number
320 * @hwirq: HW interrupt number
321 *
322 * Return: Always returns 0.
323 */
324static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
325 irq_hw_number_t hwirq)
326{
327 irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
328 irq_set_chip_data(irq, domain->host_data);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530329
330 return 0;
331}
332
333/* IRQ Domain operations */
334static const struct irq_domain_ops msi_domain_ops = {
335 .map = xilinx_pcie_msi_map,
336};
337
338/**
339 * xilinx_pcie_enable_msi - Enable MSI support
340 * @port: PCIe port information
341 */
342static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
343{
344 phys_addr_t msg_addr;
345
346 port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
347 msg_addr = virt_to_phys((void *)port->msi_pages);
348 pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
349 pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
350}
351
Srikanth Thokala8961def2014-08-20 21:56:02 +0530352/* INTx Functions */
353
354/**
355 * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
356 * @domain: IRQ domain
357 * @irq: Virtual IRQ number
358 * @hwirq: HW interrupt number
359 *
360 * Return: Always returns 0.
361 */
362static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
363 irq_hw_number_t hwirq)
364{
365 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
366 irq_set_chip_data(irq, domain->host_data);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530367
368 return 0;
369}
370
371/* INTx IRQ Domain operations */
372static const struct irq_domain_ops intx_domain_ops = {
373 .map = xilinx_pcie_intx_map,
374};
375
376/* PCIe HW Functions */
377
378/**
379 * xilinx_pcie_intr_handler - Interrupt Service Handler
380 * @irq: IRQ number
381 * @data: PCIe port information
382 *
383 * Return: IRQ_HANDLED on success and IRQ_NONE on failure
384 */
385static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
386{
387 struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
388 u32 val, mask, status, msi_data;
389
390 /* Read interrupt decode and mask registers */
391 val = pcie_read(port, XILINX_PCIE_REG_IDR);
392 mask = pcie_read(port, XILINX_PCIE_REG_IMR);
393
394 status = val & mask;
395 if (!status)
396 return IRQ_NONE;
397
398 if (status & XILINX_PCIE_INTR_LINK_DOWN)
399 dev_warn(port->dev, "Link Down\n");
400
401 if (status & XILINX_PCIE_INTR_ECRC_ERR)
402 dev_warn(port->dev, "ECRC failed\n");
403
404 if (status & XILINX_PCIE_INTR_STR_ERR)
405 dev_warn(port->dev, "Streaming error\n");
406
407 if (status & XILINX_PCIE_INTR_HOT_RESET)
408 dev_info(port->dev, "Hot reset\n");
409
410 if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
411 dev_warn(port->dev, "ECAM access timeout\n");
412
413 if (status & XILINX_PCIE_INTR_CORRECTABLE) {
414 dev_warn(port->dev, "Correctable error message\n");
415 xilinx_pcie_clear_err_interrupts(port);
416 }
417
418 if (status & XILINX_PCIE_INTR_NONFATAL) {
419 dev_warn(port->dev, "Non fatal error message\n");
420 xilinx_pcie_clear_err_interrupts(port);
421 }
422
423 if (status & XILINX_PCIE_INTR_FATAL) {
424 dev_warn(port->dev, "Fatal error message\n");
425 xilinx_pcie_clear_err_interrupts(port);
426 }
427
428 if (status & XILINX_PCIE_INTR_INTX) {
429 /* INTx interrupt received */
430 val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
431
432 /* Check whether interrupt valid */
433 if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
434 dev_warn(port->dev, "RP Intr FIFO1 read error\n");
435 return IRQ_HANDLED;
436 }
437
Russell Joycee4a8f8e2015-07-07 17:54:19 +0100438 if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
439 /* Clear interrupt FIFO register 1 */
440 pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
441 XILINX_PCIE_REG_RPIFR1);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530442
Russell Joycee4a8f8e2015-07-07 17:54:19 +0100443 /* Handle INTx Interrupt */
444 val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
445 XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
446 generic_handle_irq(irq_find_mapping(port->irq_domain,
447 val));
448 }
Srikanth Thokala8961def2014-08-20 21:56:02 +0530449 }
450
451 if (status & XILINX_PCIE_INTR_MSI) {
452 /* MSI Interrupt */
453 val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
454
455 if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
456 dev_warn(port->dev, "RP Intr FIFO1 read error\n");
457 return IRQ_HANDLED;
458 }
459
460 if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
461 msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
462 XILINX_PCIE_RPIFR2_MSG_DATA;
463
464 /* Clear interrupt FIFO register 1 */
465 pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
466 XILINX_PCIE_REG_RPIFR1);
467
468 if (IS_ENABLED(CONFIG_PCI_MSI)) {
469 /* Handle MSI Interrupt */
470 generic_handle_irq(msi_data);
471 }
472 }
473 }
474
475 if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
476 dev_warn(port->dev, "Slave unsupported request\n");
477
478 if (status & XILINX_PCIE_INTR_SLV_UNEXP)
479 dev_warn(port->dev, "Slave unexpected completion\n");
480
481 if (status & XILINX_PCIE_INTR_SLV_COMPL)
482 dev_warn(port->dev, "Slave completion timeout\n");
483
484 if (status & XILINX_PCIE_INTR_SLV_ERRP)
485 dev_warn(port->dev, "Slave Error Poison\n");
486
487 if (status & XILINX_PCIE_INTR_SLV_CMPABT)
488 dev_warn(port->dev, "Slave Completer Abort\n");
489
490 if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
491 dev_warn(port->dev, "Slave Illegal Burst\n");
492
493 if (status & XILINX_PCIE_INTR_MST_DECERR)
494 dev_warn(port->dev, "Master decode error\n");
495
496 if (status & XILINX_PCIE_INTR_MST_SLVERR)
497 dev_warn(port->dev, "Master slave error\n");
498
499 if (status & XILINX_PCIE_INTR_MST_ERRP)
500 dev_warn(port->dev, "Master error poison\n");
501
502 /* Clear the Interrupt Decode register */
503 pcie_write(port, status, XILINX_PCIE_REG_IDR);
504
505 return IRQ_HANDLED;
506}
507
508/**
509 * xilinx_pcie_free_irq_domain - Free IRQ domain
510 * @port: PCIe port information
511 */
512static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
513{
514 int i;
515 u32 irq, num_irqs;
516
517 /* Free IRQ Domain */
518 if (IS_ENABLED(CONFIG_PCI_MSI)) {
519
520 free_pages(port->msi_pages, 0);
521
522 num_irqs = XILINX_NUM_MSI_IRQS;
523 } else {
524 /* INTx */
525 num_irqs = 4;
526 }
527
528 for (i = 0; i < num_irqs; i++) {
529 irq = irq_find_mapping(port->irq_domain, i);
530 if (irq > 0)
531 irq_dispose_mapping(irq);
532 }
533
534 irq_domain_remove(port->irq_domain);
535}
536
537/**
538 * xilinx_pcie_init_irq_domain - Initialize IRQ domain
539 * @port: PCIe port information
540 *
541 * Return: '0' on success and error value on failure
542 */
543static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
544{
545 struct device *dev = port->dev;
546 struct device_node *node = dev->of_node;
547 struct device_node *pcie_intc_node;
548
549 /* Setup INTx */
550 pcie_intc_node = of_get_next_child(node, NULL);
551 if (!pcie_intc_node) {
552 dev_err(dev, "No PCIe Intc node found\n");
Christophe JAILLETcec6dba2016-07-14 12:10:46 +0200553 return -ENODEV;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530554 }
555
556 port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
557 &intx_domain_ops,
558 port);
559 if (!port->irq_domain) {
560 dev_err(dev, "Failed to get a INTx IRQ domain\n");
Christophe JAILLETcec6dba2016-07-14 12:10:46 +0200561 return -ENODEV;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530562 }
563
564 /* Setup MSI */
565 if (IS_ENABLED(CONFIG_PCI_MSI)) {
566 port->irq_domain = irq_domain_add_linear(node,
567 XILINX_NUM_MSI_IRQS,
568 &msi_domain_ops,
569 &xilinx_pcie_msi_chip);
570 if (!port->irq_domain) {
571 dev_err(dev, "Failed to get a MSI IRQ domain\n");
Christophe JAILLETcec6dba2016-07-14 12:10:46 +0200572 return -ENODEV;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530573 }
574
575 xilinx_pcie_enable_msi(port);
576 }
577
578 return 0;
579}
580
581/**
582 * xilinx_pcie_init_port - Initialize hardware
583 * @port: PCIe port information
584 */
585static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
586{
587 if (xilinx_pcie_link_is_up(port))
588 dev_info(port->dev, "PCIe Link is UP\n");
589 else
590 dev_info(port->dev, "PCIe Link is DOWN\n");
591
592 /* Disable all interrupts */
593 pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
594 XILINX_PCIE_REG_IMR);
595
596 /* Clear pending interrupts */
597 pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
598 XILINX_PCIE_IMR_ALL_MASK,
599 XILINX_PCIE_REG_IDR);
600
601 /* Enable all interrupts */
602 pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
603
604 /* Enable the Bridge enable bit */
605 pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
606 XILINX_PCIE_REG_RPSC_BEN,
607 XILINX_PCIE_REG_RPSC);
608}
609
610/**
Srikanth Thokala8961def2014-08-20 21:56:02 +0530611 * xilinx_pcie_parse_dt - Parse Device tree
612 * @port: PCIe port information
613 *
614 * Return: '0' on success and error value on failure
615 */
616static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
617{
618 struct device *dev = port->dev;
619 struct device_node *node = dev->of_node;
620 struct resource regs;
621 const char *type;
622 int err;
623
624 type = of_get_property(node, "device_type", NULL);
625 if (!type || strcmp(type, "pci")) {
626 dev_err(dev, "invalid \"device_type\" %s\n", type);
627 return -EINVAL;
628 }
629
630 err = of_address_to_resource(node, 0, &regs);
631 if (err) {
632 dev_err(dev, "missing \"reg\" property\n");
633 return err;
634 }
635
636 port->reg_base = devm_ioremap_resource(dev, &regs);
637 if (IS_ERR(port->reg_base))
638 return PTR_ERR(port->reg_base);
639
640 port->irq = irq_of_parse_and_map(node, 0);
641 err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
Grygorii Strashko8ff0ef92015-12-10 21:18:20 +0200642 IRQF_SHARED | IRQF_NO_THREAD,
643 "xilinx-pcie", port);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530644 if (err) {
645 dev_err(dev, "unable to request irq %d\n", port->irq);
646 return err;
647 }
648
649 return 0;
650}
651
652/**
653 * xilinx_pcie_probe - Probe function
654 * @pdev: Platform device pointer
655 *
656 * Return: '0' on success and error value on failure
657 */
658static int xilinx_pcie_probe(struct platform_device *pdev)
659{
660 struct xilinx_pcie_port *port;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530661 struct device *dev = &pdev->dev;
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530662 struct pci_bus *bus;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530663 int err;
Bharat Kumar Gogada02598822016-02-11 21:58:07 +0530664 resource_size_t iobase = 0;
665 LIST_HEAD(res);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530666
667 if (!dev->of_node)
668 return -ENODEV;
669
670 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
671 if (!port)
672 return -ENOMEM;
673
674 port->dev = dev;
675
676 err = xilinx_pcie_parse_dt(port);
677 if (err) {
678 dev_err(dev, "Parsing DT failed\n");
679 return err;
680 }
681
682 xilinx_pcie_init_port(port);
683
684 err = xilinx_pcie_init_irq_domain(port);
685 if (err) {
686 dev_err(dev, "Failed creating IRQ Domain\n");
687 return err;
688 }
689
Bharat Kumar Gogada02598822016-02-11 21:58:07 +0530690 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
691 &iobase);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530692 if (err) {
Bharat Kumar Gogada02598822016-02-11 21:58:07 +0530693 dev_err(dev, "Getting bridge resources failed\n");
Srikanth Thokala8961def2014-08-20 21:56:02 +0530694 return err;
695 }
Bjorn Helgaas93a5b5e2016-05-28 18:27:03 -0500696
697 err = devm_request_pci_bus_resources(dev, &res);
698 if (err)
699 goto error;
700
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530701 bus = pci_create_root_bus(&pdev->dev, 0,
702 &xilinx_pcie_ops, port, &res);
Bjorn Helgaasc41be7a2016-05-31 11:49:14 -0500703 if (!bus) {
704 err = -ENOMEM;
705 goto error;
706 }
Yijing Wang8dd26dc2014-11-11 15:45:31 -0700707
708#ifdef CONFIG_PCI_MSI
709 xilinx_pcie_msi_chip.dev = port->dev;
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530710 bus->msi = &xilinx_pcie_msi_chip;
Yijing Wang8dd26dc2014-11-11 15:45:31 -0700711#endif
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530712 pci_scan_child_bus(bus);
713 pci_assign_unassigned_bus_resources(bus);
Bharat Kumar Gogada2c513912016-02-11 21:58:09 +0530714#ifndef CONFIG_MICROBLAZE
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530715 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
Bharat Kumar Gogada2c513912016-02-11 21:58:09 +0530716#endif
Bharat Kumar Gogada4c01f3b2016-02-11 21:58:08 +0530717 pci_bus_add_devices(bus);
718 platform_set_drvdata(pdev, port);
Srikanth Thokala8961def2014-08-20 21:56:02 +0530719
720 return 0;
Bjorn Helgaasc41be7a2016-05-31 11:49:14 -0500721
722error:
723 pci_free_resource_list(&res);
724 return err;
Srikanth Thokala8961def2014-08-20 21:56:02 +0530725}
726
727/**
728 * xilinx_pcie_remove - Remove function
729 * @pdev: Platform device pointer
730 *
731 * Return: '0' always
732 */
733static int xilinx_pcie_remove(struct platform_device *pdev)
734{
735 struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
736
737 xilinx_pcie_free_irq_domain(port);
738
739 return 0;
740}
741
742static struct of_device_id xilinx_pcie_of_match[] = {
743 { .compatible = "xlnx,axi-pcie-host-1.00.a", },
744 {}
745};
746
747static struct platform_driver xilinx_pcie_driver = {
748 .driver = {
749 .name = "xilinx-pcie",
Srikanth Thokala8961def2014-08-20 21:56:02 +0530750 .of_match_table = xilinx_pcie_of_match,
751 .suppress_bind_attrs = true,
752 },
753 .probe = xilinx_pcie_probe,
754 .remove = xilinx_pcie_remove,
755};
756module_platform_driver(xilinx_pcie_driver);
757
758MODULE_AUTHOR("Xilinx Inc");
759MODULE_DESCRIPTION("Xilinx AXI PCIe driver");
760MODULE_LICENSE("GPL v2");