Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * PCIe driver for Marvell Armada 370 and Armada XP SoCs |
| 3 | * |
| 4 | * This file is licensed under the terms of the GNU General Public |
| 5 | * License version 2. This program is licensed "as is" without any |
| 6 | * warranty of any kind, whether express or implied. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/pci.h> |
| 11 | #include <linux/clk.h> |
Sebastian Hesselbarth | 52ba992 | 2013-08-13 14:25:23 +0200 | [diff] [blame] | 12 | #include <linux/delay.h> |
| 13 | #include <linux/gpio.h> |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 14 | #include <linux/module.h> |
| 15 | #include <linux/mbus.h> |
Thomas Petazzoni | 5b4deb6 | 2013-08-09 22:27:14 +0200 | [diff] [blame] | 16 | #include <linux/msi.h> |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 17 | #include <linux/slab.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/of_address.h> |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 20 | #include <linux/of_irq.h> |
Sebastian Hesselbarth | 52ba992 | 2013-08-13 14:25:23 +0200 | [diff] [blame] | 21 | #include <linux/of_gpio.h> |
| 22 | #include <linux/of_pci.h> |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 23 | #include <linux/of_platform.h> |
| 24 | |
| 25 | /* |
| 26 | * PCIe unit register offsets. |
| 27 | */ |
| 28 | #define PCIE_DEV_ID_OFF 0x0000 |
| 29 | #define PCIE_CMD_OFF 0x0004 |
| 30 | #define PCIE_DEV_REV_OFF 0x0008 |
| 31 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) |
| 32 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) |
| 33 | #define PCIE_HEADER_LOG_4_OFF 0x0128 |
| 34 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) |
| 35 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) |
| 36 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) |
| 37 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) |
| 38 | #define PCIE_WIN5_CTRL_OFF 0x1880 |
| 39 | #define PCIE_WIN5_BASE_OFF 0x1884 |
| 40 | #define PCIE_WIN5_REMAP_OFF 0x188c |
| 41 | #define PCIE_CONF_ADDR_OFF 0x18f8 |
| 42 | #define PCIE_CONF_ADDR_EN 0x80000000 |
| 43 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) |
| 44 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) |
| 45 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) |
| 46 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) |
| 47 | #define PCIE_CONF_ADDR(bus, devfn, where) \ |
| 48 | (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ |
| 49 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ |
| 50 | PCIE_CONF_ADDR_EN) |
| 51 | #define PCIE_CONF_DATA_OFF 0x18fc |
| 52 | #define PCIE_MASK_OFF 0x1910 |
| 53 | #define PCIE_MASK_ENABLE_INTS 0x0f000000 |
| 54 | #define PCIE_CTRL_OFF 0x1a00 |
| 55 | #define PCIE_CTRL_X1_MODE 0x0001 |
| 56 | #define PCIE_STAT_OFF 0x1a04 |
| 57 | #define PCIE_STAT_BUS 0xff00 |
Thomas Petazzoni | f4ac990 | 2013-05-23 16:32:51 +0200 | [diff] [blame] | 58 | #define PCIE_STAT_DEV 0x1f0000 |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 59 | #define PCIE_STAT_LINK_DOWN BIT(0) |
| 60 | #define PCIE_DEBUG_CTRL 0x1a60 |
| 61 | #define PCIE_DEBUG_SOFT_RESET BIT(20) |
| 62 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 63 | /* PCI configuration space of a PCI-to-PCI bridge */ |
| 64 | struct mvebu_sw_pci_bridge { |
| 65 | u16 vendor; |
| 66 | u16 device; |
| 67 | u16 command; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 68 | u16 class; |
| 69 | u8 interface; |
| 70 | u8 revision; |
| 71 | u8 bist; |
| 72 | u8 header_type; |
| 73 | u8 latency_timer; |
| 74 | u8 cache_line_size; |
| 75 | u32 bar[2]; |
| 76 | u8 primary_bus; |
| 77 | u8 secondary_bus; |
| 78 | u8 subordinate_bus; |
| 79 | u8 secondary_latency_timer; |
| 80 | u8 iobase; |
| 81 | u8 iolimit; |
| 82 | u16 secondary_status; |
| 83 | u16 membase; |
| 84 | u16 memlimit; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 85 | u16 iobaseupper; |
| 86 | u16 iolimitupper; |
| 87 | u8 cappointer; |
| 88 | u8 reserved1; |
| 89 | u16 reserved2; |
| 90 | u32 romaddr; |
| 91 | u8 intline; |
| 92 | u8 intpin; |
| 93 | u16 bridgectrl; |
| 94 | }; |
| 95 | |
| 96 | struct mvebu_pcie_port; |
| 97 | |
| 98 | /* Structure representing all PCIe interfaces */ |
| 99 | struct mvebu_pcie { |
| 100 | struct platform_device *pdev; |
| 101 | struct mvebu_pcie_port *ports; |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 102 | struct msi_controller *msi; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 103 | struct resource io; |
| 104 | struct resource realio; |
| 105 | struct resource mem; |
| 106 | struct resource busn; |
| 107 | int nports; |
| 108 | }; |
| 109 | |
| 110 | /* Structure representing one PCIe interface */ |
| 111 | struct mvebu_pcie_port { |
| 112 | char *name; |
| 113 | void __iomem *base; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 114 | u32 port; |
| 115 | u32 lane; |
| 116 | int devfn; |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 117 | unsigned int mem_target; |
| 118 | unsigned int mem_attr; |
| 119 | unsigned int io_target; |
| 120 | unsigned int io_attr; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 121 | struct clk *clk; |
Sebastian Hesselbarth | 52ba992 | 2013-08-13 14:25:23 +0200 | [diff] [blame] | 122 | int reset_gpio; |
| 123 | int reset_active_low; |
| 124 | char *reset_name; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 125 | struct mvebu_sw_pci_bridge bridge; |
| 126 | struct device_node *dn; |
| 127 | struct mvebu_pcie *pcie; |
| 128 | phys_addr_t memwin_base; |
| 129 | size_t memwin_size; |
| 130 | phys_addr_t iowin_base; |
| 131 | size_t iowin_size; |
Thomas Petazzoni | ab14d45 | 2015-03-17 15:55:45 +0100 | [diff] [blame] | 132 | u32 saved_pcie_stat; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 133 | }; |
| 134 | |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 135 | static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) |
| 136 | { |
| 137 | writel(val, port->base + reg); |
| 138 | } |
| 139 | |
| 140 | static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) |
| 141 | { |
| 142 | return readl(port->base + reg); |
| 143 | } |
| 144 | |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 145 | static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) |
| 146 | { |
| 147 | return port->io_target != -1 && port->io_attr != -1; |
| 148 | } |
| 149 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 150 | static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) |
| 151 | { |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 152 | return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) |
| 156 | { |
| 157 | u32 stat; |
| 158 | |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 159 | stat = mvebu_readl(port, PCIE_STAT_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 160 | stat &= ~PCIE_STAT_BUS; |
| 161 | stat |= nr << 8; |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 162 | mvebu_writel(port, stat, PCIE_STAT_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 163 | } |
| 164 | |
Thomas Petazzoni | f4ac990 | 2013-05-23 16:32:51 +0200 | [diff] [blame] | 165 | static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) |
| 166 | { |
| 167 | u32 stat; |
| 168 | |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 169 | stat = mvebu_readl(port, PCIE_STAT_OFF); |
Thomas Petazzoni | f4ac990 | 2013-05-23 16:32:51 +0200 | [diff] [blame] | 170 | stat &= ~PCIE_STAT_DEV; |
| 171 | stat |= nr << 16; |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 172 | mvebu_writel(port, stat, PCIE_STAT_OFF); |
Thomas Petazzoni | f4ac990 | 2013-05-23 16:32:51 +0200 | [diff] [blame] | 173 | } |
| 174 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 175 | /* |
| 176 | * Setup PCIE BARs and Address Decode Wins: |
| 177 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks |
| 178 | * WIN[0-3] -> DRAM bank[0-3] |
| 179 | */ |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 180 | static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 181 | { |
| 182 | const struct mbus_dram_target_info *dram; |
| 183 | u32 size; |
| 184 | int i; |
| 185 | |
| 186 | dram = mv_mbus_dram_info(); |
| 187 | |
| 188 | /* First, disable and clear BARs and windows. */ |
| 189 | for (i = 1; i < 3; i++) { |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 190 | mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); |
| 191 | mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); |
| 192 | mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | for (i = 0; i < 5; i++) { |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 196 | mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); |
| 197 | mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); |
| 198 | mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 199 | } |
| 200 | |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 201 | mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); |
| 202 | mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); |
| 203 | mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 204 | |
| 205 | /* Setup windows for DDR banks. Count total DDR size on the fly. */ |
| 206 | size = 0; |
| 207 | for (i = 0; i < dram->num_cs; i++) { |
| 208 | const struct mbus_dram_window *cs = dram->cs + i; |
| 209 | |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 210 | mvebu_writel(port, cs->base & 0xffff0000, |
| 211 | PCIE_WIN04_BASE_OFF(i)); |
| 212 | mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); |
| 213 | mvebu_writel(port, |
| 214 | ((cs->size - 1) & 0xffff0000) | |
| 215 | (cs->mbus_attr << 8) | |
| 216 | (dram->mbus_dram_target_id << 4) | 1, |
| 217 | PCIE_WIN04_CTRL_OFF(i)); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 218 | |
| 219 | size += cs->size; |
| 220 | } |
| 221 | |
| 222 | /* Round up 'size' to the nearest power of two. */ |
| 223 | if ((size & (size - 1)) != 0) |
| 224 | size = 1 << fls(size); |
| 225 | |
| 226 | /* Setup BAR[1] to all DRAM banks. */ |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 227 | mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); |
| 228 | mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); |
| 229 | mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, |
| 230 | PCIE_BAR_CTRL_OFF(1)); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 231 | } |
| 232 | |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 233 | static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 234 | { |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 235 | u32 cmd, mask; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 236 | |
| 237 | /* Point PCIe unit MBUS decode windows to DRAM space. */ |
| 238 | mvebu_pcie_setup_wins(port); |
| 239 | |
| 240 | /* Master + slave enable. */ |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 241 | cmd = mvebu_readl(port, PCIE_CMD_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 242 | cmd |= PCI_COMMAND_IO; |
| 243 | cmd |= PCI_COMMAND_MEMORY; |
| 244 | cmd |= PCI_COMMAND_MASTER; |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 245 | mvebu_writel(port, cmd, PCIE_CMD_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 246 | |
| 247 | /* Enable interrupt lines A-D. */ |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 248 | mask = mvebu_readl(port, PCIE_MASK_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 249 | mask |= PCIE_MASK_ENABLE_INTS; |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 250 | mvebu_writel(port, mask, PCIE_MASK_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 251 | } |
| 252 | |
| 253 | static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, |
| 254 | struct pci_bus *bus, |
| 255 | u32 devfn, int where, int size, u32 *val) |
| 256 | { |
Russell King | 79e3f6c | 2015-09-23 18:17:32 +0100 | [diff] [blame] | 257 | void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; |
| 258 | |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 259 | mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), |
| 260 | PCIE_CONF_ADDR_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 261 | |
Russell King | 79e3f6c | 2015-09-23 18:17:32 +0100 | [diff] [blame] | 262 | switch (size) { |
| 263 | case 1: |
| 264 | *val = readb_relaxed(conf_data + (where & 3)); |
| 265 | break; |
| 266 | case 2: |
| 267 | *val = readw_relaxed(conf_data + (where & 2)); |
| 268 | break; |
| 269 | case 4: |
| 270 | *val = readl_relaxed(conf_data); |
| 271 | break; |
| 272 | } |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 273 | |
| 274 | return PCIBIOS_SUCCESSFUL; |
| 275 | } |
| 276 | |
| 277 | static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, |
| 278 | struct pci_bus *bus, |
| 279 | u32 devfn, int where, int size, u32 val) |
| 280 | { |
Russell King | 79e3f6c | 2015-09-23 18:17:32 +0100 | [diff] [blame] | 281 | void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 282 | |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 283 | mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), |
| 284 | PCIE_CONF_ADDR_OFF); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 285 | |
Russell King | 79e3f6c | 2015-09-23 18:17:32 +0100 | [diff] [blame] | 286 | switch (size) { |
| 287 | case 1: |
| 288 | writeb(val, conf_data + (where & 3)); |
| 289 | break; |
| 290 | case 2: |
| 291 | writew(val, conf_data + (where & 2)); |
| 292 | break; |
| 293 | case 4: |
| 294 | writel(val, conf_data); |
| 295 | break; |
| 296 | default: |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 297 | return PCIBIOS_BAD_REGISTER_NUMBER; |
Russell King | 79e3f6c | 2015-09-23 18:17:32 +0100 | [diff] [blame] | 298 | } |
Seungwon Jeon | 032b4c0 | 2013-10-04 18:58:15 +0900 | [diff] [blame] | 299 | |
| 300 | return PCIBIOS_SUCCESSFUL; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 301 | } |
| 302 | |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 303 | /* |
| 304 | * Remove windows, starting from the largest ones to the smallest |
| 305 | * ones. |
| 306 | */ |
| 307 | static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, |
| 308 | phys_addr_t base, size_t size) |
| 309 | { |
| 310 | while (size) { |
| 311 | size_t sz = 1 << (fls(size) - 1); |
| 312 | |
| 313 | mvebu_mbus_del_window(base, sz); |
| 314 | base += sz; |
| 315 | size -= sz; |
| 316 | } |
| 317 | } |
| 318 | |
| 319 | /* |
| 320 | * MBus windows can only have a power of two size, but PCI BARs do not |
| 321 | * have this constraint. Therefore, we have to split the PCI BAR into |
| 322 | * areas each having a power of two size. We start from the largest |
| 323 | * one (i.e highest order bit set in the size). |
| 324 | */ |
| 325 | static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, |
| 326 | unsigned int target, unsigned int attribute, |
| 327 | phys_addr_t base, size_t size, |
| 328 | phys_addr_t remap) |
| 329 | { |
| 330 | size_t size_mapped = 0; |
| 331 | |
| 332 | while (size) { |
| 333 | size_t sz = 1 << (fls(size) - 1); |
| 334 | int ret; |
| 335 | |
| 336 | ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, |
| 337 | sz, remap); |
| 338 | if (ret) { |
Fabio Estevam | 9aa5285 | 2014-04-29 09:58:07 -0300 | [diff] [blame] | 339 | phys_addr_t end = base + sz - 1; |
| 340 | |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 341 | dev_err(&port->pcie->pdev->dev, |
Fabio Estevam | 9aa5285 | 2014-04-29 09:58:07 -0300 | [diff] [blame] | 342 | "Could not create MBus window at [mem %pa-%pa]: %d\n", |
| 343 | &base, &end, ret); |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 344 | mvebu_pcie_del_windows(port, base - size_mapped, |
| 345 | size_mapped); |
| 346 | return; |
| 347 | } |
| 348 | |
| 349 | size -= sz; |
| 350 | size_mapped += sz; |
| 351 | base += sz; |
| 352 | if (remap != MVEBU_MBUS_NO_REMAP) |
| 353 | remap += sz; |
| 354 | } |
| 355 | } |
| 356 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 357 | static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) |
| 358 | { |
| 359 | phys_addr_t iobase; |
| 360 | |
| 361 | /* Are the new iobase/iolimit values invalid? */ |
| 362 | if (port->bridge.iolimit < port->bridge.iobase || |
Jason Gunthorpe | 43a16f9 | 2013-11-26 11:02:54 -0700 | [diff] [blame] | 363 | port->bridge.iolimitupper < port->bridge.iobaseupper || |
| 364 | !(port->bridge.command & PCI_COMMAND_IO)) { |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 365 | |
| 366 | /* If a window was configured, remove it */ |
| 367 | if (port->iowin_base) { |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 368 | mvebu_pcie_del_windows(port, port->iowin_base, |
| 369 | port->iowin_size); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 370 | port->iowin_base = 0; |
| 371 | port->iowin_size = 0; |
| 372 | } |
| 373 | |
| 374 | return; |
| 375 | } |
| 376 | |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 377 | if (!mvebu_has_ioport(port)) { |
| 378 | dev_WARN(&port->pcie->pdev->dev, |
| 379 | "Attempt to set IO when IO is disabled\n"); |
| 380 | return; |
| 381 | } |
| 382 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 383 | /* |
| 384 | * We read the PCI-to-PCI bridge emulated registers, and |
| 385 | * calculate the base address and size of the address decoding |
| 386 | * window to setup, according to the PCI-to-PCI bridge |
| 387 | * specifications. iobase is the bus address, port->iowin_base |
| 388 | * is the CPU address. |
| 389 | */ |
| 390 | iobase = ((port->bridge.iobase & 0xF0) << 8) | |
| 391 | (port->bridge.iobaseupper << 16); |
| 392 | port->iowin_base = port->pcie->io.start + iobase; |
| 393 | port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | |
| 394 | (port->bridge.iolimitupper << 16)) - |
Willy Tarreau | b6d07e0 | 2014-04-18 14:19:50 +0200 | [diff] [blame] | 395 | iobase) + 1; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 396 | |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 397 | mvebu_pcie_add_windows(port, port->io_target, port->io_attr, |
| 398 | port->iowin_base, port->iowin_size, |
| 399 | iobase); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 400 | } |
| 401 | |
| 402 | static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) |
| 403 | { |
| 404 | /* Are the new membase/memlimit values invalid? */ |
Jason Gunthorpe | 43a16f9 | 2013-11-26 11:02:54 -0700 | [diff] [blame] | 405 | if (port->bridge.memlimit < port->bridge.membase || |
| 406 | !(port->bridge.command & PCI_COMMAND_MEMORY)) { |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 407 | |
| 408 | /* If a window was configured, remove it */ |
| 409 | if (port->memwin_base) { |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 410 | mvebu_pcie_del_windows(port, port->memwin_base, |
| 411 | port->memwin_size); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 412 | port->memwin_base = 0; |
| 413 | port->memwin_size = 0; |
| 414 | } |
| 415 | |
| 416 | return; |
| 417 | } |
| 418 | |
| 419 | /* |
| 420 | * We read the PCI-to-PCI bridge emulated registers, and |
| 421 | * calculate the base address and size of the address decoding |
| 422 | * window to setup, according to the PCI-to-PCI bridge |
| 423 | * specifications. |
| 424 | */ |
| 425 | port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); |
| 426 | port->memwin_size = |
| 427 | (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - |
Willy Tarreau | b6d07e0 | 2014-04-18 14:19:50 +0200 | [diff] [blame] | 428 | port->memwin_base + 1; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 429 | |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 430 | mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr, |
| 431 | port->memwin_base, port->memwin_size, |
| 432 | MVEBU_MBUS_NO_REMAP); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | /* |
| 436 | * Initialize the configuration space of the PCI-to-PCI bridge |
| 437 | * associated with the given PCIe interface. |
| 438 | */ |
| 439 | static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) |
| 440 | { |
| 441 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; |
| 442 | |
| 443 | memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); |
| 444 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 445 | bridge->class = PCI_CLASS_BRIDGE_PCI; |
| 446 | bridge->vendor = PCI_VENDOR_ID_MARVELL; |
Andrew Lunn | a760d2f | 2014-02-05 11:55:49 +0100 | [diff] [blame] | 447 | bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; |
| 448 | bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 449 | bridge->header_type = PCI_HEADER_TYPE_BRIDGE; |
| 450 | bridge->cache_line_size = 0x10; |
| 451 | |
| 452 | /* We support 32 bits I/O addressing */ |
| 453 | bridge->iobase = PCI_IO_RANGE_TYPE_32; |
| 454 | bridge->iolimit = PCI_IO_RANGE_TYPE_32; |
| 455 | } |
| 456 | |
| 457 | /* |
| 458 | * Read the configuration space of the PCI-to-PCI bridge associated to |
| 459 | * the given PCIe interface. |
| 460 | */ |
| 461 | static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, |
| 462 | unsigned int where, int size, u32 *value) |
| 463 | { |
| 464 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; |
| 465 | |
| 466 | switch (where & ~3) { |
| 467 | case PCI_VENDOR_ID: |
| 468 | *value = bridge->device << 16 | bridge->vendor; |
| 469 | break; |
| 470 | |
| 471 | case PCI_COMMAND: |
Thomas Petazzoni | 6eb237c | 2013-05-23 16:32:53 +0200 | [diff] [blame] | 472 | *value = bridge->command; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 473 | break; |
| 474 | |
| 475 | case PCI_CLASS_REVISION: |
| 476 | *value = bridge->class << 16 | bridge->interface << 8 | |
| 477 | bridge->revision; |
| 478 | break; |
| 479 | |
| 480 | case PCI_CACHE_LINE_SIZE: |
| 481 | *value = bridge->bist << 24 | bridge->header_type << 16 | |
| 482 | bridge->latency_timer << 8 | bridge->cache_line_size; |
| 483 | break; |
| 484 | |
| 485 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: |
| 486 | *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; |
| 487 | break; |
| 488 | |
| 489 | case PCI_PRIMARY_BUS: |
| 490 | *value = (bridge->secondary_latency_timer << 24 | |
| 491 | bridge->subordinate_bus << 16 | |
| 492 | bridge->secondary_bus << 8 | |
| 493 | bridge->primary_bus); |
| 494 | break; |
| 495 | |
| 496 | case PCI_IO_BASE: |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 497 | if (!mvebu_has_ioport(port)) |
| 498 | *value = bridge->secondary_status << 16; |
| 499 | else |
| 500 | *value = (bridge->secondary_status << 16 | |
| 501 | bridge->iolimit << 8 | |
| 502 | bridge->iobase); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 503 | break; |
| 504 | |
| 505 | case PCI_MEMORY_BASE: |
| 506 | *value = (bridge->memlimit << 16 | bridge->membase); |
| 507 | break; |
| 508 | |
| 509 | case PCI_PREF_MEMORY_BASE: |
Thomas Petazzoni | 36dd1f3 | 2013-08-01 15:44:19 +0200 | [diff] [blame] | 510 | *value = 0; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 511 | break; |
| 512 | |
| 513 | case PCI_IO_BASE_UPPER16: |
| 514 | *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); |
| 515 | break; |
| 516 | |
| 517 | case PCI_ROM_ADDRESS1: |
| 518 | *value = 0; |
| 519 | break; |
| 520 | |
Jason Gunthorpe | f407dae | 2013-11-26 11:27:28 -0700 | [diff] [blame] | 521 | case PCI_INTERRUPT_LINE: |
| 522 | /* LINE PIN MIN_GNT MAX_LAT */ |
| 523 | *value = 0; |
| 524 | break; |
| 525 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 526 | default: |
Russell King | 58c19a1 | 2015-09-23 18:17:26 +0100 | [diff] [blame] | 527 | /* |
| 528 | * PCI defines configuration read accesses to reserved or |
| 529 | * unimplemented registers to read as zero and complete |
| 530 | * normally. |
| 531 | */ |
| 532 | *value = 0; |
| 533 | return PCIBIOS_SUCCESSFUL; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 534 | } |
| 535 | |
| 536 | if (size == 2) |
| 537 | *value = (*value >> (8 * (where & 3))) & 0xffff; |
| 538 | else if (size == 1) |
| 539 | *value = (*value >> (8 * (where & 3))) & 0xff; |
| 540 | |
| 541 | return PCIBIOS_SUCCESSFUL; |
| 542 | } |
| 543 | |
| 544 | /* Write to the PCI-to-PCI bridge configuration space */ |
| 545 | static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, |
| 546 | unsigned int where, int size, u32 value) |
| 547 | { |
| 548 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; |
| 549 | u32 mask, reg; |
| 550 | int err; |
| 551 | |
| 552 | if (size == 4) |
| 553 | mask = 0x0; |
| 554 | else if (size == 2) |
| 555 | mask = ~(0xffff << ((where & 3) * 8)); |
| 556 | else if (size == 1) |
| 557 | mask = ~(0xff << ((where & 3) * 8)); |
| 558 | else |
| 559 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 560 | |
| 561 | err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); |
| 562 | if (err) |
| 563 | return err; |
| 564 | |
| 565 | value = (reg & mask) | value << ((where & 3) * 8); |
| 566 | |
| 567 | switch (where & ~3) { |
| 568 | case PCI_COMMAND: |
Jason Gunthorpe | 43a16f9 | 2013-11-26 11:02:54 -0700 | [diff] [blame] | 569 | { |
| 570 | u32 old = bridge->command; |
| 571 | |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 572 | if (!mvebu_has_ioport(port)) |
| 573 | value &= ~PCI_COMMAND_IO; |
| 574 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 575 | bridge->command = value & 0xffff; |
Jason Gunthorpe | 43a16f9 | 2013-11-26 11:02:54 -0700 | [diff] [blame] | 576 | if ((old ^ bridge->command) & PCI_COMMAND_IO) |
| 577 | mvebu_pcie_handle_iobase_change(port); |
| 578 | if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) |
| 579 | mvebu_pcie_handle_membase_change(port); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 580 | break; |
Jason Gunthorpe | 43a16f9 | 2013-11-26 11:02:54 -0700 | [diff] [blame] | 581 | } |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 582 | |
| 583 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: |
| 584 | bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; |
| 585 | break; |
| 586 | |
| 587 | case PCI_IO_BASE: |
| 588 | /* |
| 589 | * We also keep bit 1 set, it is a read-only bit that |
| 590 | * indicates we support 32 bits addressing for the |
| 591 | * I/O |
| 592 | */ |
| 593 | bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; |
| 594 | bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 595 | mvebu_pcie_handle_iobase_change(port); |
| 596 | break; |
| 597 | |
| 598 | case PCI_MEMORY_BASE: |
| 599 | bridge->membase = value & 0xffff; |
| 600 | bridge->memlimit = value >> 16; |
| 601 | mvebu_pcie_handle_membase_change(port); |
| 602 | break; |
| 603 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 604 | case PCI_IO_BASE_UPPER16: |
| 605 | bridge->iobaseupper = value & 0xffff; |
| 606 | bridge->iolimitupper = value >> 16; |
| 607 | mvebu_pcie_handle_iobase_change(port); |
| 608 | break; |
| 609 | |
| 610 | case PCI_PRIMARY_BUS: |
| 611 | bridge->primary_bus = value & 0xff; |
| 612 | bridge->secondary_bus = (value >> 8) & 0xff; |
| 613 | bridge->subordinate_bus = (value >> 16) & 0xff; |
| 614 | bridge->secondary_latency_timer = (value >> 24) & 0xff; |
| 615 | mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); |
| 616 | break; |
| 617 | |
| 618 | default: |
| 619 | break; |
| 620 | } |
| 621 | |
| 622 | return PCIBIOS_SUCCESSFUL; |
| 623 | } |
| 624 | |
| 625 | static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) |
| 626 | { |
| 627 | return sys->private_data; |
| 628 | } |
| 629 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 630 | static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, |
| 631 | struct pci_bus *bus, |
| 632 | int devfn) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 633 | { |
| 634 | int i; |
| 635 | |
| 636 | for (i = 0; i < pcie->nports; i++) { |
| 637 | struct mvebu_pcie_port *port = &pcie->ports[i]; |
Jingoo Han | cf3a9d6 | 2014-11-12 12:27:54 +0900 | [diff] [blame] | 638 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 639 | if (bus->number == 0 && port->devfn == devfn) |
| 640 | return port; |
| 641 | if (bus->number != 0 && |
Thomas Petazzoni | 197fc22 | 2013-05-23 16:32:52 +0200 | [diff] [blame] | 642 | bus->number >= port->bridge.secondary_bus && |
| 643 | bus->number <= port->bridge.subordinate_bus) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 644 | return port; |
| 645 | } |
| 646 | |
| 647 | return NULL; |
| 648 | } |
| 649 | |
| 650 | /* PCI configuration space write function */ |
| 651 | static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 652 | int where, int size, u32 val) |
| 653 | { |
| 654 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); |
| 655 | struct mvebu_pcie_port *port; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 656 | int ret; |
| 657 | |
| 658 | port = mvebu_pcie_find_port(pcie, bus, devfn); |
| 659 | if (!port) |
| 660 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 661 | |
| 662 | /* Access the emulated PCI-to-PCI bridge */ |
| 663 | if (bus->number == 0) |
| 664 | return mvebu_sw_pci_bridge_write(port, where, size, val); |
| 665 | |
Jason Gunthorpe | 9f352f0 | 2013-10-01 11:58:00 -0600 | [diff] [blame] | 666 | if (!mvebu_pcie_link_up(port)) |
Thomas Petazzoni | 197fc22 | 2013-05-23 16:32:52 +0200 | [diff] [blame] | 667 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 668 | |
| 669 | /* |
| 670 | * On the secondary bus, we don't want to expose any other |
| 671 | * device than the device physically connected in the PCIe |
| 672 | * slot, visible in slot 0. In slot 1, there's a special |
| 673 | * Marvell device that only makes sense when the Armada is |
| 674 | * used as a PCIe endpoint. |
| 675 | */ |
| 676 | if (bus->number == port->bridge.secondary_bus && |
| 677 | PCI_SLOT(devfn) != 0) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 678 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 679 | |
| 680 | /* Access the real PCIe interface */ |
Thomas Petazzoni | f4ac990 | 2013-05-23 16:32:51 +0200 | [diff] [blame] | 681 | ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 682 | where, size, val); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 683 | |
| 684 | return ret; |
| 685 | } |
| 686 | |
| 687 | /* PCI configuration space read function */ |
| 688 | static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 689 | int size, u32 *val) |
| 690 | { |
| 691 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); |
| 692 | struct mvebu_pcie_port *port; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 693 | int ret; |
| 694 | |
| 695 | port = mvebu_pcie_find_port(pcie, bus, devfn); |
| 696 | if (!port) { |
| 697 | *val = 0xffffffff; |
| 698 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 699 | } |
| 700 | |
| 701 | /* Access the emulated PCI-to-PCI bridge */ |
| 702 | if (bus->number == 0) |
| 703 | return mvebu_sw_pci_bridge_read(port, where, size, val); |
| 704 | |
Jason Gunthorpe | 9f352f0 | 2013-10-01 11:58:00 -0600 | [diff] [blame] | 705 | if (!mvebu_pcie_link_up(port)) { |
Thomas Petazzoni | 197fc22 | 2013-05-23 16:32:52 +0200 | [diff] [blame] | 706 | *val = 0xffffffff; |
| 707 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 708 | } |
| 709 | |
| 710 | /* |
| 711 | * On the secondary bus, we don't want to expose any other |
| 712 | * device than the device physically connected in the PCIe |
| 713 | * slot, visible in slot 0. In slot 1, there's a special |
| 714 | * Marvell device that only makes sense when the Armada is |
| 715 | * used as a PCIe endpoint. |
| 716 | */ |
| 717 | if (bus->number == port->bridge.secondary_bus && |
| 718 | PCI_SLOT(devfn) != 0) { |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 719 | *val = 0xffffffff; |
| 720 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 721 | } |
| 722 | |
| 723 | /* Access the real PCIe interface */ |
Thomas Petazzoni | f4ac990 | 2013-05-23 16:32:51 +0200 | [diff] [blame] | 724 | ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 725 | where, size, val); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 726 | |
| 727 | return ret; |
| 728 | } |
| 729 | |
| 730 | static struct pci_ops mvebu_pcie_ops = { |
| 731 | .read = mvebu_pcie_rd_conf, |
| 732 | .write = mvebu_pcie_wr_conf, |
| 733 | }; |
| 734 | |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 735 | static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 736 | { |
| 737 | struct mvebu_pcie *pcie = sys_to_pcie(sys); |
| 738 | int i; |
| 739 | |
Lorenzo Pieralisi | 8c7d1474 | 2014-11-21 11:29:26 +0000 | [diff] [blame] | 740 | pcie->mem.name = "PCI MEM"; |
| 741 | pcie->realio.name = "PCI I/O"; |
Jason Gunthorpe | 2613ba4 | 2014-02-12 15:57:08 -0700 | [diff] [blame] | 742 | |
| 743 | if (request_resource(&iomem_resource, &pcie->mem)) |
| 744 | return 0; |
| 745 | |
| 746 | if (resource_size(&pcie->realio) != 0) { |
| 747 | if (request_resource(&ioport_resource, &pcie->realio)) { |
| 748 | release_resource(&pcie->mem); |
| 749 | return 0; |
| 750 | } |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 751 | pci_add_resource_offset(&sys->resources, &pcie->realio, |
| 752 | sys->io_offset); |
Jason Gunthorpe | 2613ba4 | 2014-02-12 15:57:08 -0700 | [diff] [blame] | 753 | } |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 754 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); |
| 755 | pci_add_resource(&sys->resources, &pcie->busn); |
| 756 | |
| 757 | for (i = 0; i < pcie->nports; i++) { |
| 758 | struct mvebu_pcie_port *port = &pcie->ports[i]; |
Jingoo Han | cf3a9d6 | 2014-11-12 12:27:54 +0900 | [diff] [blame] | 759 | |
Ezequiel Garcia | b22503a | 2013-07-26 10:17:49 -0300 | [diff] [blame] | 760 | if (!port->base) |
| 761 | continue; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 762 | mvebu_pcie_setup_hw(port); |
| 763 | } |
| 764 | |
| 765 | return 1; |
| 766 | } |
| 767 | |
Jingoo Han | f5072df | 2013-09-17 14:26:46 +0900 | [diff] [blame] | 768 | static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 769 | const struct resource *res, |
| 770 | resource_size_t start, |
| 771 | resource_size_t size, |
| 772 | resource_size_t align) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 773 | { |
| 774 | if (dev->bus->number != 0) |
| 775 | return start; |
| 776 | |
| 777 | /* |
| 778 | * On the PCI-to-PCI bridge side, the I/O windows must have at |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 779 | * least a 64 KB size and the memory windows must have at |
| 780 | * least a 1 MB size. Moreover, MBus windows need to have a |
| 781 | * base address aligned on their size, and their size must be |
| 782 | * a power of two. This means that if the BAR doesn't have a |
| 783 | * power of two size, several MBus windows will actually be |
| 784 | * created. We need to ensure that the biggest MBus window |
| 785 | * (which will be the first one) is aligned on its size, which |
| 786 | * explains the rounddown_pow_of_two() being done here. |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 787 | */ |
| 788 | if (res->flags & IORESOURCE_IO) |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 789 | return round_up(start, max_t(resource_size_t, SZ_64K, |
| 790 | rounddown_pow_of_two(size))); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 791 | else if (res->flags & IORESOURCE_MEM) |
Thomas Petazzoni | 398f5d5 | 2014-04-18 14:19:53 +0200 | [diff] [blame] | 792 | return round_up(start, max_t(resource_size_t, SZ_1M, |
| 793 | rounddown_pow_of_two(size))); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 794 | else |
| 795 | return start; |
| 796 | } |
| 797 | |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 798 | static void mvebu_pcie_enable(struct mvebu_pcie *pcie) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 799 | { |
| 800 | struct hw_pci hw; |
| 801 | |
| 802 | memset(&hw, 0, sizeof(hw)); |
| 803 | |
Yijing Wang | 2691423 | 2014-11-11 15:44:17 -0700 | [diff] [blame] | 804 | #ifdef CONFIG_PCI_MSI |
| 805 | hw.msi_ctrl = pcie->msi; |
| 806 | #endif |
| 807 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 808 | hw.nr_controllers = 1; |
| 809 | hw.private_data = (void **)&pcie; |
| 810 | hw.setup = mvebu_pcie_setup; |
Grant Likely | 16b84e5 | 2013-09-19 16:44:55 -0500 | [diff] [blame] | 811 | hw.map_irq = of_irq_parse_and_map_pci; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 812 | hw.ops = &mvebu_pcie_ops; |
| 813 | hw.align_resource = mvebu_pcie_align_resource; |
| 814 | |
Yijing Wang | 2dead00 | 2015-04-28 15:01:35 +0800 | [diff] [blame] | 815 | pci_common_init_dev(&pcie->pdev->dev, &hw); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 816 | } |
| 817 | |
| 818 | /* |
| 819 | * Looks up the list of register addresses encoded into the reg = |
| 820 | * <...> property for one that matches the given port/lane. Once |
| 821 | * found, maps it. |
| 822 | */ |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 823 | static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 824 | struct device_node *np, |
| 825 | struct mvebu_pcie_port *port) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 826 | { |
| 827 | struct resource regs; |
| 828 | int ret = 0; |
| 829 | |
| 830 | ret = of_address_to_resource(np, 0, ®s); |
| 831 | if (ret) |
Tushar Behera | f48fbf9 | 2013-06-17 14:46:13 +0530 | [diff] [blame] | 832 | return ERR_PTR(ret); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 833 | |
Tushar Behera | f48fbf9 | 2013-06-17 14:46:13 +0530 | [diff] [blame] | 834 | return devm_ioremap_resource(&pdev->dev, ®s); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 835 | } |
| 836 | |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 837 | #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) |
| 838 | #define DT_TYPE_IO 0x1 |
| 839 | #define DT_TYPE_MEM32 0x2 |
| 840 | #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) |
| 841 | #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) |
| 842 | |
| 843 | static int mvebu_get_tgt_attr(struct device_node *np, int devfn, |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 844 | unsigned long type, |
| 845 | unsigned int *tgt, |
| 846 | unsigned int *attr) |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 847 | { |
| 848 | const int na = 3, ns = 2; |
| 849 | const __be32 *range; |
| 850 | int rlen, nranges, rangesz, pna, i; |
| 851 | |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 852 | *tgt = -1; |
| 853 | *attr = -1; |
| 854 | |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 855 | range = of_get_property(np, "ranges", &rlen); |
| 856 | if (!range) |
| 857 | return -EINVAL; |
| 858 | |
| 859 | pna = of_n_addr_cells(np); |
| 860 | rangesz = pna + na + ns; |
| 861 | nranges = rlen / sizeof(__be32) / rangesz; |
| 862 | |
Thomas Petazzoni | 56fab6e | 2014-09-17 17:58:27 +0200 | [diff] [blame] | 863 | for (i = 0; i < nranges; i++, range += rangesz) { |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 864 | u32 flags = of_read_number(range, 1); |
Jean-Jacques Hiblot | 4f4bde1 | 2014-02-14 11:46:15 -0700 | [diff] [blame] | 865 | u32 slot = of_read_number(range + 1, 1); |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 866 | u64 cpuaddr = of_read_number(range + na, pna); |
| 867 | unsigned long rtype; |
| 868 | |
| 869 | if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) |
| 870 | rtype = IORESOURCE_IO; |
| 871 | else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) |
| 872 | rtype = IORESOURCE_MEM; |
Thomas Petazzoni | 56fab6e | 2014-09-17 17:58:27 +0200 | [diff] [blame] | 873 | else |
| 874 | continue; |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 875 | |
| 876 | if (slot == PCI_SLOT(devfn) && type == rtype) { |
| 877 | *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); |
| 878 | *attr = DT_CPUADDR_TO_ATTR(cpuaddr); |
| 879 | return 0; |
| 880 | } |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 881 | } |
| 882 | |
| 883 | return -ENOENT; |
| 884 | } |
| 885 | |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 886 | static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie) |
Thomas Petazzoni | 5b4deb6 | 2013-08-09 22:27:14 +0200 | [diff] [blame] | 887 | { |
| 888 | struct device_node *msi_node; |
| 889 | |
| 890 | msi_node = of_parse_phandle(pcie->pdev->dev.of_node, |
| 891 | "msi-parent", 0); |
| 892 | if (!msi_node) |
| 893 | return; |
| 894 | |
| 895 | pcie->msi = of_pci_find_msi_chip_by_node(msi_node); |
Bjorn Helgaas | 3a10766 | 2015-08-04 14:54:04 -0500 | [diff] [blame] | 896 | of_node_put(msi_node); |
Thomas Petazzoni | 5b4deb6 | 2013-08-09 22:27:14 +0200 | [diff] [blame] | 897 | |
| 898 | if (pcie->msi) |
| 899 | pcie->msi->dev = &pcie->pdev->dev; |
| 900 | } |
| 901 | |
Thomas Petazzoni | ab14d45 | 2015-03-17 15:55:45 +0100 | [diff] [blame] | 902 | static int mvebu_pcie_suspend(struct device *dev) |
| 903 | { |
| 904 | struct mvebu_pcie *pcie; |
| 905 | int i; |
| 906 | |
| 907 | pcie = dev_get_drvdata(dev); |
| 908 | for (i = 0; i < pcie->nports; i++) { |
| 909 | struct mvebu_pcie_port *port = pcie->ports + i; |
| 910 | port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); |
| 911 | } |
| 912 | |
| 913 | return 0; |
| 914 | } |
| 915 | |
| 916 | static int mvebu_pcie_resume(struct device *dev) |
| 917 | { |
| 918 | struct mvebu_pcie *pcie; |
| 919 | int i; |
| 920 | |
| 921 | pcie = dev_get_drvdata(dev); |
| 922 | for (i = 0; i < pcie->nports; i++) { |
| 923 | struct mvebu_pcie_port *port = pcie->ports + i; |
| 924 | mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); |
| 925 | mvebu_pcie_setup_hw(port); |
| 926 | } |
| 927 | |
| 928 | return 0; |
| 929 | } |
| 930 | |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 931 | static int mvebu_pcie_probe(struct platform_device *pdev) |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 932 | { |
| 933 | struct mvebu_pcie *pcie; |
| 934 | struct device_node *np = pdev->dev.of_node; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 935 | struct device_node *child; |
Russell King | 7de36cd | 2015-09-23 18:17:37 +0100 | [diff] [blame] | 936 | int num, i, ret; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 937 | |
| 938 | pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), |
| 939 | GFP_KERNEL); |
| 940 | if (!pcie) |
| 941 | return -ENOMEM; |
| 942 | |
| 943 | pcie->pdev = pdev; |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 944 | platform_set_drvdata(pdev, pcie); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 945 | |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 946 | /* Get the PCIe memory and I/O aperture */ |
| 947 | mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); |
| 948 | if (resource_size(&pcie->mem) == 0) { |
| 949 | dev_err(&pdev->dev, "invalid memory aperture size\n"); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 950 | return -EINVAL; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 951 | } |
| 952 | |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 953 | mvebu_mbus_get_pcie_io_aperture(&pcie->io); |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 954 | |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 955 | if (resource_size(&pcie->io) != 0) { |
| 956 | pcie->realio.flags = pcie->io.flags; |
| 957 | pcie->realio.start = PCIBIOS_MIN_IO; |
| 958 | pcie->realio.end = min_t(resource_size_t, |
| 959 | IO_SPACE_LIMIT, |
| 960 | resource_size(&pcie->io)); |
| 961 | } else |
| 962 | pcie->realio = pcie->io; |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 963 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 964 | /* Get the bus range */ |
| 965 | ret = of_pci_parse_bus_range(np, &pcie->busn); |
| 966 | if (ret) { |
| 967 | dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", |
| 968 | ret); |
| 969 | return ret; |
| 970 | } |
| 971 | |
Russell King | 7de36cd | 2015-09-23 18:17:37 +0100 | [diff] [blame] | 972 | num = of_get_available_child_count(pdev->dev.of_node); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 973 | |
Russell King | 7de36cd | 2015-09-23 18:17:37 +0100 | [diff] [blame] | 974 | pcie->ports = devm_kzalloc(&pdev->dev, num * |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 975 | sizeof(struct mvebu_pcie_port), |
| 976 | GFP_KERNEL); |
| 977 | if (!pcie->ports) |
| 978 | return -ENOMEM; |
| 979 | |
| 980 | i = 0; |
Russell King | 2aee2ed | 2015-09-23 18:17:42 +0100 | [diff] [blame^] | 981 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 982 | struct mvebu_pcie_port *port = &pcie->ports[i]; |
Sebastian Hesselbarth | 52ba992 | 2013-08-13 14:25:23 +0200 | [diff] [blame] | 983 | enum of_gpio_flags flags; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 984 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 985 | port->pcie = pcie; |
| 986 | |
| 987 | if (of_property_read_u32(child, "marvell,pcie-port", |
| 988 | &port->port)) { |
| 989 | dev_warn(&pdev->dev, |
| 990 | "ignoring PCIe DT node, missing pcie-port property\n"); |
| 991 | continue; |
| 992 | } |
| 993 | |
| 994 | if (of_property_read_u32(child, "marvell,pcie-lane", |
| 995 | &port->lane)) |
| 996 | port->lane = 0; |
| 997 | |
| 998 | port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", |
| 999 | port->port, port->lane); |
| 1000 | |
| 1001 | port->devfn = of_pci_get_devfn(child); |
| 1002 | if (port->devfn < 0) |
| 1003 | continue; |
| 1004 | |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 1005 | ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM, |
| 1006 | &port->mem_target, &port->mem_attr); |
| 1007 | if (ret < 0) { |
| 1008 | dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n", |
| 1009 | port->port, port->lane); |
| 1010 | continue; |
| 1011 | } |
| 1012 | |
Jason Gunthorpe | 641e674 | 2013-11-26 11:02:55 -0700 | [diff] [blame] | 1013 | if (resource_size(&pcie->io) != 0) |
| 1014 | mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO, |
| 1015 | &port->io_target, &port->io_attr); |
| 1016 | else { |
| 1017 | port->io_target = -1; |
| 1018 | port->io_attr = -1; |
Thomas Petazzoni | 11be654 | 2013-07-26 10:17:48 -0300 | [diff] [blame] | 1019 | } |
| 1020 | |
Sebastian Hesselbarth | 52ba992 | 2013-08-13 14:25:23 +0200 | [diff] [blame] | 1021 | port->reset_gpio = of_get_named_gpio_flags(child, |
| 1022 | "reset-gpios", 0, &flags); |
| 1023 | if (gpio_is_valid(port->reset_gpio)) { |
| 1024 | u32 reset_udelay = 20000; |
| 1025 | |
| 1026 | port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW; |
| 1027 | port->reset_name = kasprintf(GFP_KERNEL, |
| 1028 | "pcie%d.%d-reset", port->port, port->lane); |
| 1029 | of_property_read_u32(child, "reset-delay-us", |
| 1030 | &reset_udelay); |
| 1031 | |
| 1032 | ret = devm_gpio_request_one(&pdev->dev, |
| 1033 | port->reset_gpio, GPIOF_DIR_OUT, port->reset_name); |
| 1034 | if (ret) { |
| 1035 | if (ret == -EPROBE_DEFER) |
| 1036 | return ret; |
| 1037 | continue; |
| 1038 | } |
| 1039 | |
| 1040 | gpio_set_value(port->reset_gpio, |
| 1041 | (port->reset_active_low) ? 1 : 0); |
| 1042 | msleep(reset_udelay/1000); |
| 1043 | } |
| 1044 | |
Sebastian Hesselbarth | b42285f | 2013-08-13 14:25:20 +0200 | [diff] [blame] | 1045 | port->clk = of_clk_get_by_name(child, NULL); |
| 1046 | if (IS_ERR(port->clk)) { |
| 1047 | dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n", |
| 1048 | port->port, port->lane); |
| 1049 | continue; |
| 1050 | } |
| 1051 | |
| 1052 | ret = clk_prepare_enable(port->clk); |
| 1053 | if (ret) |
| 1054 | continue; |
| 1055 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1056 | port->base = mvebu_pcie_map_registers(pdev, child, port); |
Tushar Behera | f48fbf9 | 2013-06-17 14:46:13 +0530 | [diff] [blame] | 1057 | if (IS_ERR(port->base)) { |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1058 | dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", |
| 1059 | port->port, port->lane); |
Tushar Behera | f48fbf9 | 2013-06-17 14:46:13 +0530 | [diff] [blame] | 1060 | port->base = NULL; |
Sebastian Hesselbarth | b42285f | 2013-08-13 14:25:20 +0200 | [diff] [blame] | 1061 | clk_disable_unprepare(port->clk); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1062 | continue; |
| 1063 | } |
| 1064 | |
Thomas Petazzoni | f4ac990 | 2013-05-23 16:32:51 +0200 | [diff] [blame] | 1065 | mvebu_pcie_set_local_dev_nr(port, 1); |
| 1066 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1067 | port->dn = child; |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1068 | mvebu_sw_pci_bridge_init(port); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1069 | i++; |
| 1070 | } |
| 1071 | |
Sebastian Hesselbarth | bf09b6a | 2013-08-13 14:25:21 +0200 | [diff] [blame] | 1072 | pcie->nports = i; |
Thomas Petazzoni | 31e45ec | 2013-12-26 16:52:41 +0100 | [diff] [blame] | 1073 | |
| 1074 | for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K) |
| 1075 | pci_ioremap_io(i, pcie->io.start + i); |
| 1076 | |
Thomas Petazzoni | 5b4deb6 | 2013-08-09 22:27:14 +0200 | [diff] [blame] | 1077 | mvebu_pcie_msi_enable(pcie); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1078 | mvebu_pcie_enable(pcie); |
| 1079 | |
Thomas Petazzoni | ab14d45 | 2015-03-17 15:55:45 +0100 | [diff] [blame] | 1080 | platform_set_drvdata(pdev, pcie); |
| 1081 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1082 | return 0; |
| 1083 | } |
| 1084 | |
| 1085 | static const struct of_device_id mvebu_pcie_of_match_table[] = { |
| 1086 | { .compatible = "marvell,armada-xp-pcie", }, |
| 1087 | { .compatible = "marvell,armada-370-pcie", }, |
Sebastian Hesselbarth | cc54ccd | 2013-08-13 14:25:24 +0200 | [diff] [blame] | 1088 | { .compatible = "marvell,dove-pcie", }, |
Thomas Petazzoni | 005625f | 2013-05-15 15:36:54 +0200 | [diff] [blame] | 1089 | { .compatible = "marvell,kirkwood-pcie", }, |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1090 | {}, |
| 1091 | }; |
| 1092 | MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); |
| 1093 | |
Thomas Petazzoni | ab14d45 | 2015-03-17 15:55:45 +0100 | [diff] [blame] | 1094 | static struct dev_pm_ops mvebu_pcie_pm_ops = { |
| 1095 | .suspend_noirq = mvebu_pcie_suspend, |
| 1096 | .resume_noirq = mvebu_pcie_resume, |
| 1097 | }; |
| 1098 | |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1099 | static struct platform_driver mvebu_pcie_driver = { |
| 1100 | .driver = { |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1101 | .name = "mvebu-pcie", |
Sachin Kamat | 339135f | 2013-12-19 14:34:59 +0530 | [diff] [blame] | 1102 | .of_match_table = mvebu_pcie_of_match_table, |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 1103 | /* driver unloading/unbinding currently not supported */ |
| 1104 | .suppress_bind_attrs = true, |
Thomas Petazzoni | ab14d45 | 2015-03-17 15:55:45 +0100 | [diff] [blame] | 1105 | .pm = &mvebu_pcie_pm_ops, |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1106 | }, |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 1107 | .probe = mvebu_pcie_probe, |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1108 | }; |
Sebastian Hesselbarth | e5615c3 | 2013-08-13 14:25:22 +0200 | [diff] [blame] | 1109 | module_platform_driver(mvebu_pcie_driver); |
Thomas Petazzoni | 45361a4 | 2013-05-16 17:55:22 +0200 | [diff] [blame] | 1110 | |
| 1111 | MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); |
| 1112 | MODULE_DESCRIPTION("Marvell EBU PCIe driver"); |
Thierry Reding | 505d865 | 2014-07-11 08:58:57 +0200 | [diff] [blame] | 1113 | MODULE_LICENSE("GPL v2"); |