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Prashant Gaikwad8f8f4842013-01-11 13:16:20 +05301/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
Prashant Gaikwad61fd2902013-01-11 13:16:26 +053019#include <linux/of.h>
20#include <linux/clk/tegra.h>
Prashant Gaikwad8f8f4842013-01-11 13:16:20 +053021
22#include "clk.h"
23
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +030024#define CLK_OUT_ENB_L 0x010
25#define CLK_OUT_ENB_H 0x014
26#define CLK_OUT_ENB_U 0x018
27#define CLK_OUT_ENB_V 0x360
28#define CLK_OUT_ENB_W 0x364
29#define CLK_OUT_ENB_X 0x280
30#define CLK_OUT_ENB_SET_L 0x320
31#define CLK_OUT_ENB_CLR_L 0x324
32#define CLK_OUT_ENB_SET_H 0x328
33#define CLK_OUT_ENB_CLR_H 0x32c
34#define CLK_OUT_ENB_SET_U 0x330
35#define CLK_OUT_ENB_CLR_U 0x334
36#define CLK_OUT_ENB_SET_V 0x440
37#define CLK_OUT_ENB_CLR_V 0x444
38#define CLK_OUT_ENB_SET_W 0x448
39#define CLK_OUT_ENB_CLR_W 0x44c
40#define CLK_OUT_ENB_SET_X 0x284
41#define CLK_OUT_ENB_CLR_X 0x288
42
43#define RST_DEVICES_L 0x004
44#define RST_DEVICES_H 0x008
45#define RST_DEVICES_U 0x00C
46#define RST_DFLL_DVCO 0x2F4
47#define RST_DEVICES_V 0x358
48#define RST_DEVICES_W 0x35C
49#define RST_DEVICES_X 0x28C
50#define RST_DEVICES_SET_L 0x300
51#define RST_DEVICES_CLR_L 0x304
52#define RST_DEVICES_SET_H 0x308
53#define RST_DEVICES_CLR_H 0x30c
54#define RST_DEVICES_SET_U 0x310
55#define RST_DEVICES_CLR_U 0x314
56#define RST_DEVICES_SET_V 0x430
57#define RST_DEVICES_CLR_V 0x434
58#define RST_DEVICES_SET_W 0x438
59#define RST_DEVICES_CLR_W 0x43c
Peter De Schrijver2b239072013-09-11 17:57:37 +030060#define RST_DEVICES_SET_X 0x290
61#define RST_DEVICES_CLR_X 0x294
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +030062
Prashant Gaikwad61fd2902013-01-11 13:16:26 +053063/* Global data of Tegra CPU CAR ops */
Peter De Schrijver6a676fa2013-04-03 17:40:35 +030064static struct tegra_cpu_car_ops dummy_car_ops;
65struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
Prashant Gaikwad61fd2902013-01-11 13:16:26 +053066
Peter De Schrijver343a6072013-09-02 15:22:02 +030067int *periph_clk_enb_refcnt;
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +030068static int periph_banks;
Peter De Schrijver343a6072013-09-02 15:22:02 +030069static struct clk **clks;
70static int clk_num;
71static struct clk_onecell_data clk_data;
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +030072
73static struct tegra_clk_periph_regs periph_regs[] = {
74 [0] = {
75 .enb_reg = CLK_OUT_ENB_L,
76 .enb_set_reg = CLK_OUT_ENB_SET_L,
77 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
78 .rst_reg = RST_DEVICES_L,
79 .rst_set_reg = RST_DEVICES_SET_L,
80 .rst_clr_reg = RST_DEVICES_CLR_L,
81 },
82 [1] = {
83 .enb_reg = CLK_OUT_ENB_H,
84 .enb_set_reg = CLK_OUT_ENB_SET_H,
85 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
86 .rst_reg = RST_DEVICES_H,
87 .rst_set_reg = RST_DEVICES_SET_H,
88 .rst_clr_reg = RST_DEVICES_CLR_H,
89 },
90 [2] = {
91 .enb_reg = CLK_OUT_ENB_U,
92 .enb_set_reg = CLK_OUT_ENB_SET_U,
93 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
94 .rst_reg = RST_DEVICES_U,
95 .rst_set_reg = RST_DEVICES_SET_U,
96 .rst_clr_reg = RST_DEVICES_CLR_U,
97 },
98 [3] = {
99 .enb_reg = CLK_OUT_ENB_V,
100 .enb_set_reg = CLK_OUT_ENB_SET_V,
101 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
102 .rst_reg = RST_DEVICES_V,
103 .rst_set_reg = RST_DEVICES_SET_V,
104 .rst_clr_reg = RST_DEVICES_CLR_V,
105 },
106 [4] = {
107 .enb_reg = CLK_OUT_ENB_W,
108 .enb_set_reg = CLK_OUT_ENB_SET_W,
109 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
110 .rst_reg = RST_DEVICES_W,
111 .rst_set_reg = RST_DEVICES_SET_W,
112 .rst_clr_reg = RST_DEVICES_CLR_W,
113 },
Peter De Schrijver2b239072013-09-11 17:57:37 +0300114 [5] = {
115 .enb_reg = CLK_OUT_ENB_X,
116 .enb_set_reg = CLK_OUT_ENB_SET_X,
117 .enb_clr_reg = CLK_OUT_ENB_CLR_X,
118 .rst_reg = RST_DEVICES_X,
119 .rst_set_reg = RST_DEVICES_SET_X,
120 .rst_clr_reg = RST_DEVICES_CLR_X,
121 },
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +0300122};
123
124struct tegra_clk_periph_regs *get_reg_bank(int clkid)
125{
126 int reg_bank = clkid / 32;
127
128 if (reg_bank < periph_banks)
129 return &periph_regs[reg_bank];
130 else {
131 WARN_ON(1);
132 return NULL;
133 }
134}
135
Peter De Schrijver343a6072013-09-02 15:22:02 +0300136struct clk ** __init tegra_clk_init(int num, int banks)
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +0300137{
Peter De Schrijver343a6072013-09-02 15:22:02 +0300138 if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
139 return NULL;
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +0300140
Peter De Schrijver343a6072013-09-02 15:22:02 +0300141 periph_clk_enb_refcnt = kzalloc(32 * banks *
142 sizeof(*periph_clk_enb_refcnt), GFP_KERNEL);
143 if (!periph_clk_enb_refcnt)
144 return NULL;
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +0300145
Peter De Schrijver343a6072013-09-02 15:22:02 +0300146 periph_banks = banks;
147
148 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL);
149 if (!clks)
150 kfree(periph_clk_enb_refcnt);
151
152 clk_num = num;
153
154 return clks;
Peter De Schrijverd5ff89a2013-08-22 18:44:06 +0300155}
156
Prashant Gaikwad8f8f4842013-01-11 13:16:20 +0530157void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
158 struct clk *clks[], int clk_max)
159{
160 struct clk *clk;
161
162 for (; dup_list->clk_id < clk_max; dup_list++) {
163 clk = clks[dup_list->clk_id];
164 dup_list->lookup.clk = clk;
165 clkdev_add(&dup_list->lookup);
166 }
167}
168
169void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
170 struct clk *clks[], int clk_max)
171{
172 struct clk *clk;
173
174 for (; tbl->clk_id < clk_max; tbl++) {
175 clk = clks[tbl->clk_id];
176 if (IS_ERR_OR_NULL(clk))
177 return;
178
179 if (tbl->parent_id < clk_max) {
180 struct clk *parent = clks[tbl->parent_id];
181 if (clk_set_parent(clk, parent)) {
182 pr_err("%s: Failed to set parent %s of %s\n",
183 __func__, __clk_get_name(parent),
184 __clk_get_name(clk));
185 WARN_ON(1);
186 }
187 }
188
189 if (tbl->rate)
190 if (clk_set_rate(clk, tbl->rate)) {
191 pr_err("%s: Failed to set rate %lu of %s\n",
192 __func__, tbl->rate,
193 __clk_get_name(clk));
194 WARN_ON(1);
195 }
196
197 if (tbl->state)
198 if (clk_prepare_enable(clk)) {
199 pr_err("%s: Failed to enable %s\n", __func__,
200 __clk_get_name(clk));
201 WARN_ON(1);
202 }
203 }
204}
Prashant Gaikwad61fd2902013-01-11 13:16:26 +0530205
Peter De Schrijver343a6072013-09-02 15:22:02 +0300206void __init tegra_add_of_provider(struct device_node *np)
207{
208 int i;
209
210 for (i = 0; i < clk_num; i++) {
211 if (IS_ERR(clks[i])) {
212 pr_err
213 ("Tegra clk %d: register failed with %ld\n",
214 i, PTR_ERR(clks[i]));
215 }
216 if (!clks[i])
217 clks[i] = ERR_PTR(-EINVAL);
218 }
219
220 clk_data.clks = clks;
221 clk_data.clk_num = clk_num;
222 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
223}
224
Peter De Schrijver73d37e42013-10-09 14:47:57 +0300225void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
226{
227 int i;
228
229 for (i = 0; i < num; i++, dev_clks++)
230 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
231 dev_clks->dev_id);
232}
233
Peter De Schrijverb8700d52013-10-14 16:47:37 +0300234struct clk ** __init tegra_lookup_dt_id(int clk_id,
235 struct tegra_clk *tegra_clk)
236{
237 if (tegra_clk[clk_id].present)
238 return &clks[tegra_clk[clk_id].dt_id];
239 else
240 return NULL;
241}
242
Stephen Warren441f1992013-03-25 13:22:24 -0600243tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
244
245void __init tegra_clocks_apply_init_table(void)
246{
247 if (!tegra_clk_apply_init_table)
248 return;
249
250 tegra_clk_apply_init_table();
251}