Tony Truong | 65dc748 | 2017-10-24 15:22:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | #include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h> |
| 14 | |
| 15 | &soc { |
| 16 | pcie0: qcom,pcie@1c00000 { |
| 17 | compatible = "qcom,pci-msm"; |
| 18 | cell-index = <0>; |
| 19 | |
| 20 | reg = <0x01c00000 0x2000>, |
| 21 | <0x01c02000 0x1000>, |
| 22 | <0x40000000 0xf1d>, |
| 23 | <0x40000f20 0xa8>, |
| 24 | <0x40001000 0x1000>, |
| 25 | <0x40100000 0x100000>, |
| 26 | <0x40200000 0x100000>, |
| 27 | <0x40300000 0x1d00000>, |
| 28 | <0x01fce008 0x4>; |
| 29 | |
| 30 | reg-names = "parf", "phy", "dm_core", "elbi", "iatu", |
| 31 | "conf", "io", "bars", "tcsr"; |
| 32 | |
| 33 | #address-cells = <3>; |
| 34 | #size-cells = <2>; |
| 35 | ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, |
| 36 | <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1d00000>; |
| 37 | interrupt-parent = <&pcie0>; |
| 38 | interrupts = <0 1 2 3 4 5>; |
| 39 | #interrupt-cells = <1>; |
| 40 | interrupt-map-mask = <0 0 0 0xffffffff>; |
| 41 | interrupt-map = <0 0 0 0 &intc 0 119 0 |
| 42 | 0 0 0 1 &intc 0 141 0 |
| 43 | 0 0 0 2 &intc 0 142 0 |
| 44 | 0 0 0 3 &intc 0 143 0 |
| 45 | 0 0 0 4 &intc 0 144 0 |
| 46 | 0 0 0 5 &intc 0 140 0>; |
| 47 | |
| 48 | interrupt-names = "int_msi", "int_a", "int_b", "int_c", |
| 49 | "int_d", "int_global_int"; |
| 50 | |
| 51 | qcom,phy-sequence = <0x840 0x03 0x0 |
| 52 | 0x094 0x08 0x0 |
| 53 | 0x154 0x33 0x0 |
| 54 | 0x058 0x0f 0x0 |
| 55 | 0x0a4 0x42 0x0 |
| 56 | 0x1bc 0x11 0x0 |
| 57 | 0x0bc 0x82 0x0 |
| 58 | 0x0d4 0x03 0x0 |
| 59 | 0x0d0 0x55 0x0 |
| 60 | 0x0cc 0x55 0x0 |
| 61 | 0x0b0 0x1a 0x0 |
| 62 | 0x0ac 0x0a 0x0 |
| 63 | 0x158 0x01 0x0 |
| 64 | 0x074 0x06 0x0 |
| 65 | 0x07c 0x16 0x0 |
| 66 | 0x084 0x36 0x0 |
| 67 | 0x1b0 0x1e 0x0 |
| 68 | 0x1ac 0xb9 0x0 |
| 69 | 0x050 0x07 0x0 |
| 70 | 0x29c 0x12 0x0 |
| 71 | 0x284 0x05 0x0 |
| 72 | 0x234 0xd9 0x0 |
| 73 | 0x238 0xcc 0x0 |
| 74 | 0x51c 0x03 0x0 |
| 75 | 0x518 0x1c 0x0 |
| 76 | 0x524 0x14 0x0 |
| 77 | 0x4ec 0x0e 0x0 |
| 78 | 0x4f0 0x4a 0x0 |
| 79 | 0x4f4 0x0f 0x0 |
| 80 | 0x5b4 0x04 0x0 |
| 81 | 0x434 0x7f 0x0 |
| 82 | 0x444 0x70 0x0 |
| 83 | 0x510 0x17 0x0 |
| 84 | 0x4d8 0x01 0x0 |
| 85 | 0x598 0xe0 0x0 |
| 86 | 0x59c 0xc8 0x0 |
| 87 | 0x5a0 0xc8 0x0 |
| 88 | 0x5a4 0x09 0x0 |
| 89 | 0x5a8 0xb1 0x0 |
| 90 | 0x584 0x24 0x0 |
| 91 | 0x588 0xe4 0x0 |
| 92 | 0x58c 0xec 0x0 |
| 93 | 0x590 0x39 0x0 |
| 94 | 0x594 0x36 0x0 |
| 95 | 0x570 0xef 0x0 |
| 96 | 0x574 0xef 0x0 |
| 97 | 0x578 0x2f 0x0 |
| 98 | 0x57c 0xd3 0x0 |
| 99 | 0x580 0x40 0x0 |
| 100 | 0x4fc 0x00 0x0 |
| 101 | 0x4f8 0xc0 0x0 |
| 102 | 0x9a4 0x01 0x0 |
| 103 | 0xc90 0x00 0x0 |
| 104 | 0xc40 0x01 0x0 |
| 105 | 0xc48 0x01 0x0 |
| 106 | 0xca0 0x11 0x0 |
| 107 | 0x048 0x90 0x0 |
| 108 | 0xc1c 0xc1 0x0 |
| 109 | 0x988 0x88 0x0 |
| 110 | 0x998 0x08 0x0 |
| 111 | 0x8dc 0x0d 0x0 |
| 112 | 0x800 0x00 0x0 |
| 113 | 0x844 0x03 0x0>; |
| 114 | |
| 115 | pinctrl-names = "default"; |
| 116 | pinctrl-0 = <&pcie0_clkreq_default |
| 117 | &pcie0_perst_default |
| 118 | &pcie0_wake_default>; |
| 119 | |
| 120 | perst-gpio = <&tlmm 57 0>; |
| 121 | wake-gpio = <&tlmm 53 0>; |
| 122 | |
| 123 | gdsc-vdd-supply = <&gdsc_pcie>; |
| 124 | vreg-1.8-supply = <&pmxpoorwills_l1>; |
| 125 | vreg-0.9-supply = <&pmxpoorwills_l4>; |
| 126 | vreg-cx-supply = <&pmxpoorwills_s5_level>; |
| 127 | |
| 128 | qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; |
| 129 | qcom,vreg-0.9-voltage-level = <872000 872000 24000>; |
| 130 | qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX |
| 131 | RPMH_REGULATOR_LEVEL_SVS 0>; |
| 132 | |
| 133 | qcom,l0s-supported; |
| 134 | qcom,l1-supported; |
| 135 | qcom,l1ss-supported; |
| 136 | qcom,aux-clk-sync; |
| 137 | |
| 138 | qcom,ep-latency = <10>; |
| 139 | |
| 140 | qcom,slv-addr-space-size = <0x40000000>; |
| 141 | |
Tony Truong | 2b675ba | 2017-12-12 14:52:00 -0800 | [diff] [blame^] | 142 | qcom,phy-status-offset = <0x814>; |
| 143 | |
Tony Truong | 65dc748 | 2017-10-24 15:22:06 -0700 | [diff] [blame] | 144 | qcom,cpl-timeout = <0x2>; |
| 145 | |
| 146 | qcom,boot-option = <0x1>; |
| 147 | |
| 148 | linux,pci-domain = <0>; |
| 149 | |
| 150 | qcom,use-19p2mhz-aux-clk; |
| 151 | |
| 152 | qcom,msm-bus,name = "pcie0"; |
| 153 | qcom,msm-bus,num-cases = <2>; |
| 154 | qcom,msm-bus,num-paths = <1>; |
| 155 | qcom,msm-bus,vectors-KBps = |
| 156 | <45 512 0 0>, |
| 157 | <45 512 500 800>; |
| 158 | |
| 159 | clocks = <&clock_gcc GCC_PCIE_PIPE_CLK>, |
| 160 | <&clock_rpmh RPMH_CXO_CLK>, |
| 161 | <&clock_gcc GCC_PCIE_AUX_CLK>, |
| 162 | <&clock_gcc GCC_PCIE_CFG_AHB_CLK>, |
| 163 | <&clock_gcc GCC_PCIE_MSTR_AXI_CLK>, |
| 164 | <&clock_gcc GCC_PCIE_SLV_AXI_CLK>, |
| 165 | <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, |
| 166 | <&clock_gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, |
| 167 | <&clock_gcc GCC_PCIE_SLEEP_CLK>, |
| 168 | <&clock_gcc GCC_PCIE_PHY_REFGEN_CLK>; |
| 169 | |
| 170 | clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", |
| 171 | "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", |
| 172 | "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", |
| 173 | "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", |
| 174 | "pcie_0_sleep_clk", "pcie_phy_refgen_clk"; |
| 175 | |
| 176 | max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>, |
| 177 | <0>, <0>, <0>, <0>, <100000000>; |
| 178 | |
| 179 | resets = <&clock_gcc GCC_PCIE_BCR>, |
| 180 | <&clock_gcc GCC_PCIE_PHY_BCR>; |
| 181 | |
| 182 | reset-names = "pcie_0_core_reset", |
| 183 | "pcie_0_phy_reset"; |
| 184 | }; |
| 185 | }; |