blob: 306ebc51599a2bb1e6e83983aa3e71017840c8ce [file] [log] [blame]
Sekhar Noria6c0f6e2009-11-03 15:14:13 +05301/*
2 * CPU idle for DaVinci SoCs
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Derived from Marvell Kirkwood CPU idle code
7 * (arch/arm/mach-kirkwood/cpuidle.c)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/cpuidle.h>
18#include <linux/io.h>
Paul Gortmakerdc280942011-07-31 16:17:29 -040019#include <linux/export.h>
Robert Lee19976c22012-03-20 15:22:45 -050020#include <asm/cpuidle.h>
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053021
22#include <mach/cpuidle.h>
Nicolas Pitre0020afb2011-07-05 22:52:57 -040023#include <mach/ddr2.h>
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053024
25#define DAVINCI_CPUIDLE_MAX_STATES 2
26
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053027static void __iomem *ddr2_reg_base;
Daniel Lezcano5af4a212013-02-04 12:01:41 +000028static bool ddr2_pdown;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053029
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053030static void davinci_save_ddr_power(int enter, bool pdown)
31{
32 u32 val;
33
34 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
35
36 if (enter) {
37 if (pdown)
38 val |= DDR2_SRPD_BIT;
39 else
40 val &= ~DDR2_SRPD_BIT;
41 val |= DDR2_LPMODEN_BIT;
42 } else {
43 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
44 }
45
46 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
47}
48
Daniel Lezcano8d601432013-02-04 12:01:42 +000049/* Actual code that puts the SoC in different idle states */
50static int davinci_enter_idle(struct cpuidle_device *dev,
Daniel Lezcanoc062d442013-04-03 12:15:19 +000051 struct cpuidle_driver *drv, int index)
Daniel Lezcano8d601432013-02-04 12:01:42 +000052{
Daniel Lezcano36ce8d42013-02-04 12:01:43 +000053 davinci_save_ddr_power(1, ddr2_pdown);
Daniel Lezcanoc062d442013-04-03 12:15:19 +000054 cpu_do_idle();
Daniel Lezcano36ce8d42013-02-04 12:01:43 +000055 davinci_save_ddr_power(0, ddr2_pdown);
Daniel Lezcano8d601432013-02-04 12:01:42 +000056
57 return index;
58}
59
60static struct cpuidle_driver davinci_idle_driver = {
61 .name = "cpuidle-davinci",
62 .owner = THIS_MODULE,
Daniel Lezcano8d601432013-02-04 12:01:42 +000063 .states[0] = ARM_CPUIDLE_WFI_STATE,
64 .states[1] = {
65 .enter = davinci_enter_idle,
66 .exit_latency = 10,
Daniel Lezcano7006b8a2013-06-28 12:09:09 +020067 .target_residency = 10000,
Daniel Lezcano8d601432013-02-04 12:01:42 +000068 .name = "DDR SR",
69 .desc = "WFI and DDR Self Refresh",
70 },
71 .state_count = DAVINCI_CPUIDLE_MAX_STATES,
72};
73
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053074static int __init davinci_cpuidle_probe(struct platform_device *pdev)
75{
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053076 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053077
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053078 if (!pdata) {
79 dev_err(&pdev->dev, "cannot get platform data\n");
80 return -ENOENT;
81 }
82
Sekhar Nori948c66d2009-11-16 17:21:37 +053083 ddr2_reg_base = pdata->ddr2_ctlr_base;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053084
Daniel Lezcano5af4a212013-02-04 12:01:41 +000085 ddr2_pdown = pdata->ddr2_pdown;
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053086
Daniel Lezcano3aec0342013-04-23 08:54:44 +000087 return cpuidle_register(&davinci_idle_driver, NULL);
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053088}
89
90static struct platform_driver davinci_cpuidle_driver = {
91 .driver = {
92 .name = "cpuidle-davinci",
Sekhar Noria6c0f6e2009-11-03 15:14:13 +053093 },
94};
95
96static int __init davinci_cpuidle_init(void)
97{
98 return platform_driver_probe(&davinci_cpuidle_driver,
99 davinci_cpuidle_probe);
100}
101device_initcall(davinci_cpuidle_init);
102