David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 6 | * Copyright (C) 2004-2016 Cavium Networks |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 7 | * Copyright (C) 2008 Wind River Systems |
| 8 | */ |
| 9 | |
| 10 | #include <linux/init.h> |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 11 | #include <linux/delay.h> |
Aaro Koskinen | 377de39 | 2016-02-24 00:52:06 +0200 | [diff] [blame] | 12 | #include <linux/etherdevice.h> |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 13 | #include <linux/of_platform.h> |
| 14 | #include <linux/of_fdt.h> |
| 15 | #include <linux/libfdt.h> |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 16 | #include <linux/usb/ehci_def.h> |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 17 | #include <linux/usb/ehci_pdriver.h> |
| 18 | #include <linux/usb/ohci_pdriver.h> |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 19 | |
| 20 | #include <asm/octeon/octeon.h> |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 21 | #include <asm/octeon/cvmx-helper-board.h> |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 22 | #include <asm/octeon/cvmx-uctlx-defs.h> |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 23 | |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 24 | #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) |
| 25 | #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) |
| 26 | |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 27 | /* Octeon Random Number Generator. */ |
| 28 | static int __init octeon_rng_device_init(void) |
| 29 | { |
| 30 | struct platform_device *pd; |
| 31 | int ret = 0; |
| 32 | |
| 33 | struct resource rng_resources[] = { |
| 34 | { |
| 35 | .flags = IORESOURCE_MEM, |
| 36 | .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), |
| 37 | .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf |
| 38 | }, { |
| 39 | .flags = IORESOURCE_MEM, |
| 40 | .start = cvmx_build_io_address(8, 0), |
| 41 | .end = cvmx_build_io_address(8, 0) + 0x7 |
| 42 | } |
| 43 | }; |
| 44 | |
| 45 | pd = platform_device_alloc("octeon_rng", -1); |
| 46 | if (!pd) { |
| 47 | ret = -ENOMEM; |
| 48 | goto out; |
| 49 | } |
| 50 | |
| 51 | ret = platform_device_add_resources(pd, rng_resources, |
| 52 | ARRAY_SIZE(rng_resources)); |
| 53 | if (ret) |
| 54 | goto fail; |
| 55 | |
| 56 | ret = platform_device_add(pd); |
| 57 | if (ret) |
| 58 | goto fail; |
| 59 | |
| 60 | return ret; |
| 61 | fail: |
| 62 | platform_device_put(pd); |
| 63 | |
| 64 | out: |
| 65 | return ret; |
| 66 | } |
| 67 | device_initcall(octeon_rng_device_init); |
| 68 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 69 | #ifdef CONFIG_USB |
| 70 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 71 | static DEFINE_MUTEX(octeon2_usb_clocks_mutex); |
| 72 | |
| 73 | static int octeon2_usb_clock_start_cnt; |
| 74 | |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 75 | static int __init octeon2_usb_reset(void) |
| 76 | { |
| 77 | union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; |
| 78 | u32 ucmd; |
| 79 | |
| 80 | if (!OCTEON_IS_OCTEON2()) |
| 81 | return 0; |
| 82 | |
| 83 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
| 84 | if (clk_rst_ctl.s.hrst) { |
| 85 | ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD); |
| 86 | ucmd &= ~CMD_RUN; |
| 87 | cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); |
| 88 | mdelay(2); |
| 89 | ucmd |= CMD_RESET; |
| 90 | cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); |
| 91 | ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD); |
| 92 | ucmd |= CMD_RUN; |
| 93 | cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd); |
| 94 | } |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | arch_initcall(octeon2_usb_reset); |
| 99 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 100 | static void octeon2_usb_clocks_start(struct device *dev) |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 101 | { |
| 102 | u64 div; |
| 103 | union cvmx_uctlx_if_ena if_ena; |
| 104 | union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 105 | union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status; |
| 106 | int i; |
| 107 | unsigned long io_clk_64_to_ns; |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 108 | u32 clock_rate = 12000000; |
| 109 | bool is_crystal_clock = false; |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 110 | |
| 111 | |
| 112 | mutex_lock(&octeon2_usb_clocks_mutex); |
| 113 | |
| 114 | octeon2_usb_clock_start_cnt++; |
| 115 | if (octeon2_usb_clock_start_cnt != 1) |
| 116 | goto exit; |
| 117 | |
| 118 | io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate(); |
| 119 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 120 | if (dev->of_node) { |
| 121 | struct device_node *uctl_node; |
| 122 | const char *clock_type; |
| 123 | |
| 124 | uctl_node = of_get_parent(dev->of_node); |
| 125 | if (!uctl_node) { |
| 126 | dev_err(dev, "No UCTL device node\n"); |
| 127 | goto exit; |
| 128 | } |
| 129 | i = of_property_read_u32(uctl_node, |
| 130 | "refclk-frequency", &clock_rate); |
| 131 | if (i) { |
| 132 | dev_err(dev, "No UCTL \"refclk-frequency\"\n"); |
| 133 | goto exit; |
| 134 | } |
| 135 | i = of_property_read_string(uctl_node, |
| 136 | "refclk-type", &clock_type); |
| 137 | |
| 138 | if (!i && strcmp("crystal", clock_type) == 0) |
| 139 | is_crystal_clock = true; |
| 140 | } |
| 141 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 142 | /* |
| 143 | * Step 1: Wait for voltages stable. That surely happened |
| 144 | * before starting the kernel. |
| 145 | * |
| 146 | * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1 |
| 147 | */ |
| 148 | if_ena.u64 = 0; |
| 149 | if_ena.s.en = 1; |
| 150 | cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); |
| 151 | |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 152 | for (i = 0; i <= 1; i++) { |
| 153 | port_ctl_status.u64 = |
| 154 | cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); |
| 155 | /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */ |
| 156 | port_ctl_status.s.txvreftune = 15; |
| 157 | port_ctl_status.s.txrisetune = 1; |
| 158 | port_ctl_status.s.txpreemphasistune = 1; |
| 159 | cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), |
| 160 | port_ctl_status.u64); |
| 161 | } |
| 162 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 163 | /* Step 3: Configure the reference clock, PHY, and HCLK */ |
| 164 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
| 165 | |
| 166 | /* |
| 167 | * If the UCTL looks like it has already been started, skip |
| 168 | * the initialization, otherwise bus errors are obtained. |
| 169 | */ |
| 170 | if (clk_rst_ctl.s.hrst) |
| 171 | goto end_clock; |
| 172 | /* 3a */ |
| 173 | clk_rst_ctl.s.p_por = 1; |
| 174 | clk_rst_ctl.s.hrst = 0; |
| 175 | clk_rst_ctl.s.p_prst = 0; |
| 176 | clk_rst_ctl.s.h_clkdiv_rst = 0; |
| 177 | clk_rst_ctl.s.o_clkdiv_rst = 0; |
| 178 | clk_rst_ctl.s.h_clkdiv_en = 0; |
| 179 | clk_rst_ctl.s.o_clkdiv_en = 0; |
| 180 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 181 | |
| 182 | /* 3b */ |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 183 | clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1; |
| 184 | switch (clock_rate) { |
| 185 | default: |
| 186 | pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n", |
| 187 | clock_rate); |
| 188 | /* Fall through */ |
| 189 | case 12000000: |
| 190 | clk_rst_ctl.s.p_refclk_div = 0; |
| 191 | break; |
| 192 | case 24000000: |
| 193 | clk_rst_ctl.s.p_refclk_div = 1; |
| 194 | break; |
| 195 | case 48000000: |
| 196 | clk_rst_ctl.s.p_refclk_div = 2; |
| 197 | break; |
| 198 | } |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 199 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 200 | |
| 201 | /* 3c */ |
| 202 | div = octeon_get_io_clock_rate() / 130000000ull; |
| 203 | |
| 204 | switch (div) { |
| 205 | case 0: |
| 206 | div = 1; |
| 207 | break; |
| 208 | case 1: |
| 209 | case 2: |
| 210 | case 3: |
| 211 | case 4: |
| 212 | break; |
| 213 | case 5: |
| 214 | div = 4; |
| 215 | break; |
| 216 | case 6: |
| 217 | case 7: |
| 218 | div = 6; |
| 219 | break; |
| 220 | case 8: |
| 221 | case 9: |
| 222 | case 10: |
| 223 | case 11: |
| 224 | div = 8; |
| 225 | break; |
| 226 | default: |
| 227 | div = 12; |
| 228 | break; |
| 229 | } |
| 230 | clk_rst_ctl.s.h_div = div; |
| 231 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 232 | /* Read it back, */ |
| 233 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
| 234 | clk_rst_ctl.s.h_clkdiv_en = 1; |
| 235 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 236 | /* 3d */ |
| 237 | clk_rst_ctl.s.h_clkdiv_rst = 1; |
| 238 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 239 | |
| 240 | /* 3e: delay 64 io clocks */ |
| 241 | ndelay(io_clk_64_to_ns); |
| 242 | |
| 243 | /* |
| 244 | * Step 4: Program the power-on reset field in the UCTL |
| 245 | * clock-reset-control register. |
| 246 | */ |
| 247 | clk_rst_ctl.s.p_por = 0; |
| 248 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 249 | |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 250 | /* Step 5: Wait 3 ms for the PHY clock to start. */ |
| 251 | mdelay(3); |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 252 | |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 253 | /* Steps 6..9 for ATE only, are skipped. */ |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 254 | |
| 255 | /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */ |
| 256 | /* 10a */ |
| 257 | clk_rst_ctl.s.o_clkdiv_rst = 1; |
| 258 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 259 | |
| 260 | /* 10b */ |
| 261 | clk_rst_ctl.s.o_clkdiv_en = 1; |
| 262 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 263 | |
| 264 | /* 10c */ |
| 265 | ndelay(io_clk_64_to_ns); |
| 266 | |
| 267 | /* |
| 268 | * Step 11: Program the PHY reset field: |
| 269 | * UCTL0_CLK_RST_CTL[P_PRST] = 1 |
| 270 | */ |
| 271 | clk_rst_ctl.s.p_prst = 1; |
| 272 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 273 | |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 274 | /* Step 11b */ |
| 275 | udelay(1); |
| 276 | |
| 277 | /* Step 11c */ |
| 278 | clk_rst_ctl.s.p_prst = 0; |
| 279 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 280 | |
| 281 | /* Step 11d */ |
| 282 | mdelay(1); |
| 283 | |
| 284 | /* Step 11e */ |
| 285 | clk_rst_ctl.s.p_prst = 1; |
| 286 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 287 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 288 | /* Step 12: Wait 1 uS. */ |
| 289 | udelay(1); |
| 290 | |
| 291 | /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */ |
| 292 | clk_rst_ctl.s.hrst = 1; |
| 293 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 294 | |
| 295 | end_clock: |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 296 | /* Set uSOF cycle period to 60,000 bits. */ |
| 297 | cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); |
Steven J. Hill | 7e78db9 | 2016-07-26 10:26:26 -0500 | [diff] [blame] | 298 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 299 | exit: |
| 300 | mutex_unlock(&octeon2_usb_clocks_mutex); |
| 301 | } |
| 302 | |
| 303 | static void octeon2_usb_clocks_stop(void) |
| 304 | { |
| 305 | mutex_lock(&octeon2_usb_clocks_mutex); |
| 306 | octeon2_usb_clock_start_cnt--; |
| 307 | mutex_unlock(&octeon2_usb_clocks_mutex); |
| 308 | } |
| 309 | |
| 310 | static int octeon_ehci_power_on(struct platform_device *pdev) |
| 311 | { |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 312 | octeon2_usb_clocks_start(&pdev->dev); |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | static void octeon_ehci_power_off(struct platform_device *pdev) |
| 317 | { |
| 318 | octeon2_usb_clocks_stop(); |
| 319 | } |
| 320 | |
| 321 | static struct usb_ehci_pdata octeon_ehci_pdata = { |
| 322 | /* Octeon EHCI matches CPU endianness. */ |
| 323 | #ifdef __BIG_ENDIAN |
| 324 | .big_endian_mmio = 1, |
| 325 | #endif |
Steven J. Hill | 8552b5b | 2016-07-26 10:26:23 -0500 | [diff] [blame] | 326 | /* |
| 327 | * We can DMA from anywhere. But the descriptors must be in |
| 328 | * the lower 4GB. |
| 329 | */ |
| 330 | .dma_mask_64 = 0, |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 331 | .power_on = octeon_ehci_power_on, |
| 332 | .power_off = octeon_ehci_power_off, |
| 333 | }; |
| 334 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 335 | static void __init octeon_ehci_hw_start(struct device *dev) |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 336 | { |
| 337 | union cvmx_uctlx_ehci_ctl ehci_ctl; |
| 338 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 339 | octeon2_usb_clocks_start(dev); |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 340 | |
| 341 | ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); |
| 342 | /* Use 64-bit addressing. */ |
| 343 | ehci_ctl.s.ehci_64b_addr_en = 1; |
| 344 | ehci_ctl.s.l2c_addr_msb = 0; |
Paul Martin | b0abf36 | 2015-03-30 17:00:57 +0100 | [diff] [blame] | 345 | #ifdef __BIG_ENDIAN |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 346 | ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ |
| 347 | ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ |
Paul Martin | b0abf36 | 2015-03-30 17:00:57 +0100 | [diff] [blame] | 348 | #else |
| 349 | ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ |
| 350 | ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ |
| 351 | ehci_ctl.s.inv_reg_a2 = 1; |
| 352 | #endif |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 353 | cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); |
| 354 | |
| 355 | octeon2_usb_clocks_stop(); |
| 356 | } |
| 357 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 358 | static int __init octeon_ehci_device_init(void) |
| 359 | { |
| 360 | struct platform_device *pd; |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 361 | struct device_node *ehci_node; |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 362 | int ret = 0; |
| 363 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 364 | ehci_node = of_find_node_by_name(NULL, "ehci"); |
| 365 | if (!ehci_node) |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 366 | return 0; |
| 367 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 368 | pd = of_find_device_by_node(ehci_node); |
Nicholas Mc Guire | 819a8da | 2018-06-16 09:06:33 +0200 | [diff] [blame] | 369 | of_node_put(ehci_node); |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 370 | if (!pd) |
| 371 | return 0; |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 372 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 373 | pd->dev.platform_data = &octeon_ehci_pdata; |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 374 | octeon_ehci_hw_start(&pd->dev); |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 375 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 376 | return ret; |
| 377 | } |
| 378 | device_initcall(octeon_ehci_device_init); |
| 379 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 380 | static int octeon_ohci_power_on(struct platform_device *pdev) |
| 381 | { |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 382 | octeon2_usb_clocks_start(&pdev->dev); |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 383 | return 0; |
| 384 | } |
| 385 | |
| 386 | static void octeon_ohci_power_off(struct platform_device *pdev) |
| 387 | { |
| 388 | octeon2_usb_clocks_stop(); |
| 389 | } |
| 390 | |
| 391 | static struct usb_ohci_pdata octeon_ohci_pdata = { |
| 392 | /* Octeon OHCI matches CPU endianness. */ |
| 393 | #ifdef __BIG_ENDIAN |
| 394 | .big_endian_mmio = 1, |
| 395 | #endif |
| 396 | .power_on = octeon_ohci_power_on, |
| 397 | .power_off = octeon_ohci_power_off, |
| 398 | }; |
| 399 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 400 | static void __init octeon_ohci_hw_start(struct device *dev) |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 401 | { |
| 402 | union cvmx_uctlx_ohci_ctl ohci_ctl; |
| 403 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 404 | octeon2_usb_clocks_start(dev); |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 405 | |
| 406 | ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); |
| 407 | ohci_ctl.s.l2c_addr_msb = 0; |
Paul Martin | b0abf36 | 2015-03-30 17:00:57 +0100 | [diff] [blame] | 408 | #ifdef __BIG_ENDIAN |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 409 | ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ |
| 410 | ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ |
Paul Martin | b0abf36 | 2015-03-30 17:00:57 +0100 | [diff] [blame] | 411 | #else |
| 412 | ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ |
| 413 | ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ |
| 414 | ohci_ctl.s.inv_reg_a2 = 1; |
| 415 | #endif |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 416 | cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); |
| 417 | |
| 418 | octeon2_usb_clocks_stop(); |
| 419 | } |
| 420 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 421 | static int __init octeon_ohci_device_init(void) |
| 422 | { |
| 423 | struct platform_device *pd; |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 424 | struct device_node *ohci_node; |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 425 | int ret = 0; |
| 426 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 427 | ohci_node = of_find_node_by_name(NULL, "ohci"); |
| 428 | if (!ohci_node) |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 429 | return 0; |
| 430 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 431 | pd = of_find_device_by_node(ohci_node); |
Nicholas Mc Guire | 819a8da | 2018-06-16 09:06:33 +0200 | [diff] [blame] | 432 | of_node_put(ohci_node); |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 433 | if (!pd) |
| 434 | return 0; |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 435 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 436 | pd->dev.platform_data = &octeon_ohci_pdata; |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 437 | octeon_ohci_hw_start(&pd->dev); |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 438 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 439 | return ret; |
| 440 | } |
| 441 | device_initcall(octeon_ohci_device_init); |
| 442 | |
| 443 | #endif /* CONFIG_USB */ |
| 444 | |
Andreas Herrmann | a95cfa6 | 2015-01-06 13:48:56 +0100 | [diff] [blame] | 445 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 446 | static struct of_device_id __initdata octeon_ids[] = { |
| 447 | { .compatible = "simple-bus", }, |
| 448 | { .compatible = "cavium,octeon-6335-uctl", }, |
David Daney | d617f9e | 2013-12-03 11:46:51 -0800 | [diff] [blame] | 449 | { .compatible = "cavium,octeon-5750-usbn", }, |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 450 | { .compatible = "cavium,octeon-3860-bootbus", }, |
| 451 | { .compatible = "cavium,mdio-mux", }, |
| 452 | { .compatible = "gpio-leds", }, |
| 453 | {}, |
| 454 | }; |
| 455 | |
| 456 | static bool __init octeon_has_88e1145(void) |
| 457 | { |
| 458 | return !OCTEON_IS_MODEL(OCTEON_CN52XX) && |
| 459 | !OCTEON_IS_MODEL(OCTEON_CN6XXX) && |
| 460 | !OCTEON_IS_MODEL(OCTEON_CN56XX); |
| 461 | } |
| 462 | |
| 463 | static void __init octeon_fdt_set_phy(int eth, int phy_addr) |
| 464 | { |
| 465 | const __be32 *phy_handle; |
| 466 | const __be32 *alt_phy_handle; |
| 467 | const __be32 *reg; |
| 468 | u32 phandle; |
| 469 | int phy; |
| 470 | int alt_phy; |
| 471 | const char *p; |
| 472 | int current_len; |
| 473 | char new_name[20]; |
| 474 | |
| 475 | phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); |
| 476 | if (!phy_handle) |
| 477 | return; |
| 478 | |
| 479 | phandle = be32_to_cpup(phy_handle); |
| 480 | phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); |
| 481 | |
| 482 | alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); |
| 483 | if (alt_phy_handle) { |
| 484 | u32 alt_phandle = be32_to_cpup(alt_phy_handle); |
| 485 | alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); |
| 486 | } else { |
| 487 | alt_phy = -1; |
| 488 | } |
| 489 | |
| 490 | if (phy_addr < 0 || phy < 0) { |
| 491 | /* Delete the PHY things */ |
| 492 | fdt_nop_property(initial_boot_params, eth, "phy-handle"); |
| 493 | /* This one may fail */ |
| 494 | fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); |
| 495 | if (phy >= 0) |
| 496 | fdt_nop_node(initial_boot_params, phy); |
| 497 | if (alt_phy >= 0) |
| 498 | fdt_nop_node(initial_boot_params, alt_phy); |
| 499 | return; |
| 500 | } |
| 501 | |
| 502 | if (phy_addr >= 256 && alt_phy > 0) { |
| 503 | const struct fdt_property *phy_prop; |
| 504 | struct fdt_property *alt_prop; |
Aaro Koskinen | 2bd3bfa | 2018-11-22 00:37:29 +0200 | [diff] [blame^] | 505 | fdt32_t phy_handle_name; |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 506 | |
| 507 | /* Use the alt phy node instead.*/ |
| 508 | phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); |
| 509 | phy_handle_name = phy_prop->nameoff; |
| 510 | fdt_nop_node(initial_boot_params, phy); |
| 511 | fdt_nop_property(initial_boot_params, eth, "phy-handle"); |
| 512 | alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); |
| 513 | alt_prop->nameoff = phy_handle_name; |
| 514 | phy = alt_phy; |
| 515 | } |
| 516 | |
| 517 | phy_addr &= 0xff; |
| 518 | |
| 519 | if (octeon_has_88e1145()) { |
| 520 | fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); |
| 521 | memset(new_name, 0, sizeof(new_name)); |
| 522 | strcpy(new_name, "marvell,88e1145"); |
| 523 | p = fdt_getprop(initial_boot_params, phy, "compatible", |
| 524 | ¤t_len); |
| 525 | if (p && current_len >= strlen(new_name)) |
| 526 | fdt_setprop_inplace(initial_boot_params, phy, |
| 527 | "compatible", new_name, current_len); |
| 528 | } |
| 529 | |
| 530 | reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); |
| 531 | if (phy_addr == be32_to_cpup(reg)) |
| 532 | return; |
| 533 | |
| 534 | fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); |
| 535 | |
| 536 | snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); |
| 537 | |
| 538 | p = fdt_get_name(initial_boot_params, phy, ¤t_len); |
| 539 | if (p && current_len == strlen(new_name)) |
| 540 | fdt_set_name(initial_boot_params, phy, new_name); |
| 541 | else |
| 542 | pr_err("Error: could not rename ethernet phy: <%s>", p); |
| 543 | } |
| 544 | |
| 545 | static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) |
| 546 | { |
Aaro Koskinen | 377de39 | 2016-02-24 00:52:06 +0200 | [diff] [blame] | 547 | const u8 *old_mac; |
| 548 | int old_len; |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 549 | u8 new_mac[6]; |
| 550 | u64 mac = *pmac; |
| 551 | int r; |
| 552 | |
Aaro Koskinen | 377de39 | 2016-02-24 00:52:06 +0200 | [diff] [blame] | 553 | old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address", |
| 554 | &old_len); |
| 555 | if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac)) |
| 556 | return; |
| 557 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 558 | new_mac[0] = (mac >> 40) & 0xff; |
| 559 | new_mac[1] = (mac >> 32) & 0xff; |
| 560 | new_mac[2] = (mac >> 24) & 0xff; |
| 561 | new_mac[3] = (mac >> 16) & 0xff; |
| 562 | new_mac[4] = (mac >> 8) & 0xff; |
| 563 | new_mac[5] = mac & 0xff; |
| 564 | |
| 565 | r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", |
| 566 | new_mac, sizeof(new_mac)); |
| 567 | |
| 568 | if (r) { |
| 569 | pr_err("Setting \"local-mac-address\" failed %d", r); |
| 570 | return; |
| 571 | } |
| 572 | *pmac = mac + 1; |
| 573 | } |
| 574 | |
| 575 | static void __init octeon_fdt_rm_ethernet(int node) |
| 576 | { |
| 577 | const __be32 *phy_handle; |
| 578 | |
| 579 | phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); |
| 580 | if (phy_handle) { |
| 581 | u32 ph = be32_to_cpup(phy_handle); |
| 582 | int p = fdt_node_offset_by_phandle(initial_boot_params, ph); |
| 583 | if (p >= 0) |
| 584 | fdt_nop_node(initial_boot_params, p); |
| 585 | } |
| 586 | fdt_nop_node(initial_boot_params, node); |
| 587 | } |
| 588 | |
Aaro Koskinen | 43349b9 | 2016-02-24 00:52:05 +0200 | [diff] [blame] | 589 | static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 590 | { |
| 591 | char name_buffer[20]; |
| 592 | int eth; |
| 593 | int phy_addr; |
| 594 | int ipd_port; |
| 595 | |
| 596 | snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); |
| 597 | eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); |
| 598 | if (eth < 0) |
| 599 | return; |
| 600 | if (p > max) { |
| 601 | pr_debug("Deleting port %x:%x\n", i, p); |
| 602 | octeon_fdt_rm_ethernet(eth); |
| 603 | return; |
| 604 | } |
| 605 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
| 606 | ipd_port = (0x100 * i) + (0x10 * p) + 0x800; |
| 607 | else |
| 608 | ipd_port = 16 * i + p; |
| 609 | |
| 610 | phy_addr = cvmx_helper_board_get_mii_address(ipd_port); |
| 611 | octeon_fdt_set_phy(eth, phy_addr); |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 612 | } |
| 613 | |
Aaro Koskinen | 43349b9 | 2016-02-24 00:52:05 +0200 | [diff] [blame] | 614 | static void __init octeon_fdt_pip_iface(int pip, int idx) |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 615 | { |
| 616 | char name_buffer[20]; |
| 617 | int iface; |
| 618 | int p; |
Faidon Liambotis | ab2bb14 | 2013-07-11 21:08:09 +0000 | [diff] [blame] | 619 | int count = 0; |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 620 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 621 | snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); |
| 622 | iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); |
| 623 | if (iface < 0) |
| 624 | return; |
| 625 | |
Aaro Koskinen | b2e4f15 | 2013-11-01 17:06:04 +0200 | [diff] [blame] | 626 | if (cvmx_helper_interface_enumerate(idx) == 0) |
| 627 | count = cvmx_helper_ports_on_interface(idx); |
| 628 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 629 | for (p = 0; p < 16; p++) |
Aaro Koskinen | 43349b9 | 2016-02-24 00:52:05 +0200 | [diff] [blame] | 630 | octeon_fdt_pip_port(iface, idx, p, count - 1); |
| 631 | } |
| 632 | |
| 633 | void __init octeon_fill_mac_addresses(void) |
| 634 | { |
| 635 | const char *alias_prop; |
| 636 | char name_buffer[20]; |
| 637 | u64 mac_addr_base; |
| 638 | int aliases; |
| 639 | int pip; |
| 640 | int i; |
| 641 | |
| 642 | aliases = fdt_path_offset(initial_boot_params, "/aliases"); |
| 643 | if (aliases < 0) |
| 644 | return; |
| 645 | |
| 646 | mac_addr_base = |
| 647 | ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | |
| 648 | ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | |
| 649 | ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | |
| 650 | ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | |
| 651 | ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | |
| 652 | (octeon_bootinfo->mac_addr_base[5] & 0xffull); |
| 653 | |
| 654 | for (i = 0; i < 2; i++) { |
| 655 | int mgmt; |
| 656 | |
| 657 | snprintf(name_buffer, sizeof(name_buffer), "mix%d", i); |
| 658 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 659 | name_buffer, NULL); |
| 660 | if (!alias_prop) |
| 661 | continue; |
| 662 | mgmt = fdt_path_offset(initial_boot_params, alias_prop); |
| 663 | if (mgmt < 0) |
| 664 | continue; |
| 665 | octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); |
| 666 | } |
| 667 | |
| 668 | alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL); |
| 669 | if (!alias_prop) |
| 670 | return; |
| 671 | |
| 672 | pip = fdt_path_offset(initial_boot_params, alias_prop); |
| 673 | if (pip < 0) |
| 674 | return; |
| 675 | |
| 676 | for (i = 0; i <= 4; i++) { |
| 677 | int iface; |
| 678 | int p; |
| 679 | |
| 680 | snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i); |
| 681 | iface = fdt_subnode_offset(initial_boot_params, pip, |
| 682 | name_buffer); |
| 683 | if (iface < 0) |
| 684 | continue; |
| 685 | for (p = 0; p < 16; p++) { |
| 686 | int eth; |
| 687 | |
| 688 | snprintf(name_buffer, sizeof(name_buffer), |
| 689 | "ethernet@%x", p); |
| 690 | eth = fdt_subnode_offset(initial_boot_params, iface, |
| 691 | name_buffer); |
| 692 | if (eth < 0) |
| 693 | continue; |
| 694 | octeon_fdt_set_mac_addr(eth, &mac_addr_base); |
| 695 | } |
| 696 | } |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 697 | } |
| 698 | |
| 699 | int __init octeon_prune_device_tree(void) |
| 700 | { |
| 701 | int i, max_port, uart_mask; |
| 702 | const char *pip_path; |
| 703 | const char *alias_prop; |
| 704 | char name_buffer[20]; |
| 705 | int aliases; |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 706 | |
| 707 | if (fdt_check_header(initial_boot_params)) |
| 708 | panic("Corrupt Device Tree."); |
| 709 | |
Aaro Koskinen | 86bee12 | 2016-06-05 00:18:18 +0300 | [diff] [blame] | 710 | WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N, |
| 711 | "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.", |
| 712 | cvmx_board_type_to_string(octeon_bootinfo->board_type)); |
| 713 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 714 | aliases = fdt_path_offset(initial_boot_params, "/aliases"); |
| 715 | if (aliases < 0) { |
| 716 | pr_err("Error: No /aliases node in device tree."); |
| 717 | return -EINVAL; |
| 718 | } |
| 719 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 720 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) |
| 721 | max_port = 2; |
| 722 | else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) |
| 723 | max_port = 1; |
| 724 | else |
| 725 | max_port = 0; |
| 726 | |
| 727 | if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) |
| 728 | max_port = 0; |
| 729 | |
| 730 | for (i = 0; i < 2; i++) { |
| 731 | int mgmt; |
| 732 | snprintf(name_buffer, sizeof(name_buffer), |
| 733 | "mix%d", i); |
| 734 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 735 | name_buffer, NULL); |
| 736 | if (alias_prop) { |
| 737 | mgmt = fdt_path_offset(initial_boot_params, alias_prop); |
| 738 | if (mgmt < 0) |
| 739 | continue; |
| 740 | if (i >= max_port) { |
| 741 | pr_debug("Deleting mix%d\n", i); |
| 742 | octeon_fdt_rm_ethernet(mgmt); |
| 743 | fdt_nop_property(initial_boot_params, aliases, |
| 744 | name_buffer); |
| 745 | } else { |
| 746 | int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); |
| 747 | octeon_fdt_set_phy(mgmt, phy_addr); |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 748 | } |
| 749 | } |
| 750 | } |
| 751 | |
| 752 | pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); |
| 753 | if (pip_path) { |
| 754 | int pip = fdt_path_offset(initial_boot_params, pip_path); |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 755 | if (pip >= 0) |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 756 | for (i = 0; i <= 4; i++) |
Aaro Koskinen | 43349b9 | 2016-02-24 00:52:05 +0200 | [diff] [blame] | 757 | octeon_fdt_pip_iface(pip, i); |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 758 | } |
| 759 | |
| 760 | /* I2C */ |
| 761 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || |
| 762 | OCTEON_IS_MODEL(OCTEON_CN63XX) || |
| 763 | OCTEON_IS_MODEL(OCTEON_CN68XX) || |
| 764 | OCTEON_IS_MODEL(OCTEON_CN56XX)) |
| 765 | max_port = 2; |
| 766 | else |
| 767 | max_port = 1; |
| 768 | |
| 769 | for (i = 0; i < 2; i++) { |
| 770 | int i2c; |
| 771 | snprintf(name_buffer, sizeof(name_buffer), |
| 772 | "twsi%d", i); |
| 773 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 774 | name_buffer, NULL); |
| 775 | |
| 776 | if (alias_prop) { |
| 777 | i2c = fdt_path_offset(initial_boot_params, alias_prop); |
| 778 | if (i2c < 0) |
| 779 | continue; |
| 780 | if (i >= max_port) { |
| 781 | pr_debug("Deleting twsi%d\n", i); |
| 782 | fdt_nop_node(initial_boot_params, i2c); |
| 783 | fdt_nop_property(initial_boot_params, aliases, |
| 784 | name_buffer); |
| 785 | } |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | /* SMI/MDIO */ |
| 790 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
| 791 | max_port = 4; |
| 792 | else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || |
| 793 | OCTEON_IS_MODEL(OCTEON_CN63XX) || |
| 794 | OCTEON_IS_MODEL(OCTEON_CN56XX)) |
| 795 | max_port = 2; |
| 796 | else |
| 797 | max_port = 1; |
| 798 | |
| 799 | for (i = 0; i < 2; i++) { |
| 800 | int i2c; |
| 801 | snprintf(name_buffer, sizeof(name_buffer), |
| 802 | "smi%d", i); |
| 803 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 804 | name_buffer, NULL); |
| 805 | |
| 806 | if (alias_prop) { |
| 807 | i2c = fdt_path_offset(initial_boot_params, alias_prop); |
| 808 | if (i2c < 0) |
| 809 | continue; |
| 810 | if (i >= max_port) { |
| 811 | pr_debug("Deleting smi%d\n", i); |
| 812 | fdt_nop_node(initial_boot_params, i2c); |
| 813 | fdt_nop_property(initial_boot_params, aliases, |
| 814 | name_buffer); |
| 815 | } |
| 816 | } |
| 817 | } |
| 818 | |
| 819 | /* Serial */ |
| 820 | uart_mask = 3; |
| 821 | |
| 822 | /* Right now CN52XX is the only chip with a third uart */ |
| 823 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) |
| 824 | uart_mask |= 4; /* uart2 */ |
| 825 | |
| 826 | for (i = 0; i < 3; i++) { |
| 827 | int uart; |
| 828 | snprintf(name_buffer, sizeof(name_buffer), |
| 829 | "uart%d", i); |
| 830 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 831 | name_buffer, NULL); |
| 832 | |
| 833 | if (alias_prop) { |
| 834 | uart = fdt_path_offset(initial_boot_params, alias_prop); |
David Daney | 5219343 | 2013-06-19 20:37:26 +0000 | [diff] [blame] | 835 | if (uart_mask & (1 << i)) { |
| 836 | __be32 f; |
| 837 | |
| 838 | f = cpu_to_be32(octeon_get_io_clock_rate()); |
| 839 | fdt_setprop_inplace(initial_boot_params, |
| 840 | uart, "clock-frequency", |
| 841 | &f, sizeof(f)); |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 842 | continue; |
David Daney | 5219343 | 2013-06-19 20:37:26 +0000 | [diff] [blame] | 843 | } |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 844 | pr_debug("Deleting uart%d\n", i); |
| 845 | fdt_nop_node(initial_boot_params, uart); |
| 846 | fdt_nop_property(initial_boot_params, aliases, |
| 847 | name_buffer); |
| 848 | } |
| 849 | } |
| 850 | |
| 851 | /* Compact Flash */ |
| 852 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 853 | "cf0", NULL); |
| 854 | if (alias_prop) { |
| 855 | union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; |
| 856 | unsigned long base_ptr, region_base, region_size; |
| 857 | unsigned long region1_base = 0; |
| 858 | unsigned long region1_size = 0; |
| 859 | int cs, bootbus; |
| 860 | bool is_16bit = false; |
| 861 | bool is_true_ide = false; |
| 862 | __be32 new_reg[6]; |
| 863 | __be32 *ranges; |
| 864 | int len; |
| 865 | |
| 866 | int cf = fdt_path_offset(initial_boot_params, alias_prop); |
| 867 | base_ptr = 0; |
| 868 | if (octeon_bootinfo->major_version == 1 |
| 869 | && octeon_bootinfo->minor_version >= 1) { |
| 870 | if (octeon_bootinfo->compact_flash_common_base_addr) |
| 871 | base_ptr = octeon_bootinfo->compact_flash_common_base_addr; |
| 872 | } else { |
| 873 | base_ptr = 0x1d000800; |
| 874 | } |
| 875 | |
| 876 | if (!base_ptr) |
| 877 | goto no_cf; |
| 878 | |
| 879 | /* Find CS0 region. */ |
| 880 | for (cs = 0; cs < 8; cs++) { |
| 881 | mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
| 882 | region_base = mio_boot_reg_cfg.s.base << 16; |
| 883 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
| 884 | if (mio_boot_reg_cfg.s.en && base_ptr >= region_base |
| 885 | && base_ptr < region_base + region_size) { |
| 886 | is_16bit = mio_boot_reg_cfg.s.width; |
| 887 | break; |
| 888 | } |
| 889 | } |
| 890 | if (cs >= 7) { |
| 891 | /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ |
| 892 | goto no_cf; |
| 893 | } |
| 894 | |
| 895 | if (!(base_ptr & 0xfffful)) { |
| 896 | /* |
| 897 | * Boot loader signals availability of DMA (true_ide |
| 898 | * mode) by setting low order bits of base_ptr to |
| 899 | * zero. |
| 900 | */ |
| 901 | |
| 902 | /* Asume that CS1 immediately follows. */ |
| 903 | mio_boot_reg_cfg.u64 = |
| 904 | cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); |
| 905 | region1_base = mio_boot_reg_cfg.s.base << 16; |
| 906 | region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
| 907 | if (!mio_boot_reg_cfg.s.en) |
| 908 | goto no_cf; |
| 909 | is_true_ide = true; |
| 910 | |
| 911 | } else { |
| 912 | fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); |
| 913 | fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); |
| 914 | if (!is_16bit) { |
| 915 | __be32 width = cpu_to_be32(8); |
| 916 | fdt_setprop_inplace(initial_boot_params, cf, |
| 917 | "cavium,bus-width", &width, sizeof(width)); |
| 918 | } |
| 919 | } |
| 920 | new_reg[0] = cpu_to_be32(cs); |
| 921 | new_reg[1] = cpu_to_be32(0); |
| 922 | new_reg[2] = cpu_to_be32(0x10000); |
| 923 | new_reg[3] = cpu_to_be32(cs + 1); |
| 924 | new_reg[4] = cpu_to_be32(0); |
| 925 | new_reg[5] = cpu_to_be32(0x10000); |
| 926 | fdt_setprop_inplace(initial_boot_params, cf, |
| 927 | "reg", new_reg, sizeof(new_reg)); |
| 928 | |
| 929 | bootbus = fdt_parent_offset(initial_boot_params, cf); |
| 930 | if (bootbus < 0) |
| 931 | goto no_cf; |
| 932 | ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); |
| 933 | if (!ranges || len < (5 * 8 * sizeof(__be32))) |
| 934 | goto no_cf; |
| 935 | |
| 936 | ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); |
| 937 | ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); |
| 938 | ranges[(cs * 5) + 4] = cpu_to_be32(region_size); |
| 939 | if (is_true_ide) { |
| 940 | cs++; |
| 941 | ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); |
| 942 | ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); |
| 943 | ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); |
| 944 | } |
| 945 | goto end_cf; |
| 946 | no_cf: |
| 947 | fdt_nop_node(initial_boot_params, cf); |
| 948 | |
| 949 | end_cf: |
| 950 | ; |
| 951 | } |
| 952 | |
| 953 | /* 8 char LED */ |
| 954 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 955 | "led0", NULL); |
| 956 | if (alias_prop) { |
| 957 | union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; |
| 958 | unsigned long base_ptr, region_base, region_size; |
| 959 | int cs, bootbus; |
| 960 | __be32 new_reg[6]; |
| 961 | __be32 *ranges; |
| 962 | int len; |
| 963 | int led = fdt_path_offset(initial_boot_params, alias_prop); |
| 964 | |
| 965 | base_ptr = octeon_bootinfo->led_display_base_addr; |
| 966 | if (base_ptr == 0) |
| 967 | goto no_led; |
| 968 | /* Find CS0 region. */ |
| 969 | for (cs = 0; cs < 8; cs++) { |
| 970 | mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
| 971 | region_base = mio_boot_reg_cfg.s.base << 16; |
| 972 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
| 973 | if (mio_boot_reg_cfg.s.en && base_ptr >= region_base |
| 974 | && base_ptr < region_base + region_size) |
| 975 | break; |
| 976 | } |
| 977 | |
| 978 | if (cs > 7) |
| 979 | goto no_led; |
| 980 | |
| 981 | new_reg[0] = cpu_to_be32(cs); |
| 982 | new_reg[1] = cpu_to_be32(0x20); |
| 983 | new_reg[2] = cpu_to_be32(0x20); |
| 984 | new_reg[3] = cpu_to_be32(cs); |
| 985 | new_reg[4] = cpu_to_be32(0); |
| 986 | new_reg[5] = cpu_to_be32(0x20); |
| 987 | fdt_setprop_inplace(initial_boot_params, led, |
| 988 | "reg", new_reg, sizeof(new_reg)); |
| 989 | |
| 990 | bootbus = fdt_parent_offset(initial_boot_params, led); |
| 991 | if (bootbus < 0) |
| 992 | goto no_led; |
| 993 | ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); |
| 994 | if (!ranges || len < (5 * 8 * sizeof(__be32))) |
| 995 | goto no_led; |
| 996 | |
| 997 | ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); |
| 998 | ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); |
| 999 | ranges[(cs * 5) + 4] = cpu_to_be32(region_size); |
| 1000 | goto end_led; |
| 1001 | |
| 1002 | no_led: |
| 1003 | fdt_nop_node(initial_boot_params, led); |
| 1004 | end_led: |
| 1005 | ; |
| 1006 | } |
| 1007 | |
| 1008 | /* OHCI/UHCI USB */ |
| 1009 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 1010 | "uctl", NULL); |
| 1011 | if (alias_prop) { |
| 1012 | int uctl = fdt_path_offset(initial_boot_params, alias_prop); |
| 1013 | |
| 1014 | if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || |
| 1015 | octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { |
| 1016 | pr_debug("Deleting uctl\n"); |
| 1017 | fdt_nop_node(initial_boot_params, uctl); |
| 1018 | fdt_nop_property(initial_boot_params, aliases, "uctl"); |
| 1019 | } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || |
| 1020 | octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { |
| 1021 | /* Missing "refclk-type" defaults to crystal. */ |
| 1022 | fdt_nop_property(initial_boot_params, uctl, "refclk-type"); |
| 1023 | } |
| 1024 | } |
| 1025 | |
David Daney | d617f9e | 2013-12-03 11:46:51 -0800 | [diff] [blame] | 1026 | /* DWC2 USB */ |
| 1027 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 1028 | "usbn", NULL); |
| 1029 | if (alias_prop) { |
| 1030 | int usbn = fdt_path_offset(initial_boot_params, alias_prop); |
| 1031 | |
| 1032 | if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 || |
| 1033 | !octeon_has_feature(OCTEON_FEATURE_USB))) { |
| 1034 | pr_debug("Deleting usbn\n"); |
| 1035 | fdt_nop_node(initial_boot_params, usbn); |
| 1036 | fdt_nop_property(initial_boot_params, aliases, "usbn"); |
| 1037 | } else { |
| 1038 | __be32 new_f[1]; |
| 1039 | enum cvmx_helper_board_usb_clock_types c; |
| 1040 | c = __cvmx_helper_board_usb_get_clock_type(); |
| 1041 | switch (c) { |
| 1042 | case USB_CLOCK_TYPE_REF_48: |
| 1043 | new_f[0] = cpu_to_be32(48000000); |
| 1044 | fdt_setprop_inplace(initial_boot_params, usbn, |
| 1045 | "refclk-frequency", new_f, sizeof(new_f)); |
| 1046 | /* Fall through ...*/ |
| 1047 | case USB_CLOCK_TYPE_REF_12: |
| 1048 | /* Missing "refclk-type" defaults to external. */ |
| 1049 | fdt_nop_property(initial_boot_params, usbn, "refclk-type"); |
| 1050 | break; |
| 1051 | default: |
| 1052 | break; |
| 1053 | } |
| 1054 | } |
| 1055 | } |
| 1056 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 1057 | return 0; |
| 1058 | } |
| 1059 | |
| 1060 | static int __init octeon_publish_devices(void) |
| 1061 | { |
| 1062 | return of_platform_bus_probe(NULL, octeon_ids, NULL); |
| 1063 | } |
Aaro Koskinen | 8074d78 | 2016-08-23 21:39:43 +0300 | [diff] [blame] | 1064 | arch_initcall(octeon_publish_devices); |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 1065 | |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 1066 | MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); |
| 1067 | MODULE_LICENSE("GPL"); |
| 1068 | MODULE_DESCRIPTION("Platform driver for Octeon SOC"); |