Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 1 | /* |
| 2 | * isp.h |
| 3 | * |
| 4 | * TI OMAP3 ISP - Core |
| 5 | * |
| 6 | * Copyright (C) 2009-2010 Nokia Corporation |
| 7 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 8 | * |
| 9 | * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 10 | * Sakari Ailus <sakari.ailus@iki.fi> |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 19 | * General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 24 | * 02110-1301 USA |
| 25 | */ |
| 26 | |
| 27 | #ifndef OMAP3_ISP_CORE_H |
| 28 | #define OMAP3_ISP_CORE_H |
| 29 | |
Laurent Pinchart | b98d32f | 2011-08-12 19:09:34 +0200 | [diff] [blame] | 30 | #include <media/omap3isp.h> |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 31 | #include <media/v4l2-device.h> |
| 32 | #include <linux/device.h> |
| 33 | #include <linux/io.h> |
Tony Lindgren | c8d35c8 | 2012-11-02 12:24:03 -0700 | [diff] [blame] | 34 | #include <linux/iommu.h> |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 35 | #include <linux/platform_device.h> |
| 36 | #include <linux/wait.h> |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 37 | |
| 38 | #include "ispstat.h" |
| 39 | #include "ispccdc.h" |
| 40 | #include "ispreg.h" |
| 41 | #include "ispresizer.h" |
| 42 | #include "isppreview.h" |
| 43 | #include "ispcsiphy.h" |
| 44 | #include "ispcsi2.h" |
| 45 | #include "ispccp2.h" |
| 46 | |
| 47 | #define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8) |
| 48 | |
| 49 | #define ISP_TOK_TERM 0xFFFFFFFF /* |
| 50 | * terminating token for ISP |
| 51 | * modules reg list |
| 52 | */ |
| 53 | #define to_isp_device(ptr_module) \ |
| 54 | container_of(ptr_module, struct isp_device, isp_##ptr_module) |
| 55 | #define to_device(ptr_module) \ |
| 56 | (to_isp_device(ptr_module)->dev) |
| 57 | |
| 58 | enum isp_mem_resources { |
| 59 | OMAP3_ISP_IOMEM_MAIN, |
| 60 | OMAP3_ISP_IOMEM_CCP2, |
| 61 | OMAP3_ISP_IOMEM_CCDC, |
| 62 | OMAP3_ISP_IOMEM_HIST, |
| 63 | OMAP3_ISP_IOMEM_H3A, |
| 64 | OMAP3_ISP_IOMEM_PREV, |
| 65 | OMAP3_ISP_IOMEM_RESZ, |
| 66 | OMAP3_ISP_IOMEM_SBL, |
| 67 | OMAP3_ISP_IOMEM_CSI2A_REGS1, |
| 68 | OMAP3_ISP_IOMEM_CSIPHY2, |
| 69 | OMAP3_ISP_IOMEM_CSI2A_REGS2, |
| 70 | OMAP3_ISP_IOMEM_CSI2C_REGS1, |
| 71 | OMAP3_ISP_IOMEM_CSIPHY1, |
| 72 | OMAP3_ISP_IOMEM_CSI2C_REGS2, |
Sakari Ailus | c19d19e | 2012-10-14 07:31:48 -0300 | [diff] [blame] | 73 | OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE, |
| 74 | OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL, |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 75 | OMAP3_ISP_IOMEM_LAST |
| 76 | }; |
| 77 | |
| 78 | enum isp_sbl_resource { |
| 79 | OMAP3_ISP_SBL_CSI1_READ = 0x1, |
| 80 | OMAP3_ISP_SBL_CSI1_WRITE = 0x2, |
| 81 | OMAP3_ISP_SBL_CSI2A_WRITE = 0x4, |
| 82 | OMAP3_ISP_SBL_CSI2C_WRITE = 0x8, |
| 83 | OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10, |
| 84 | OMAP3_ISP_SBL_CCDC_WRITE = 0x20, |
| 85 | OMAP3_ISP_SBL_PREVIEW_READ = 0x40, |
| 86 | OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80, |
| 87 | OMAP3_ISP_SBL_RESIZER_READ = 0x100, |
| 88 | OMAP3_ISP_SBL_RESIZER_WRITE = 0x200, |
| 89 | }; |
| 90 | |
| 91 | enum isp_subclk_resource { |
| 92 | OMAP3_ISP_SUBCLK_CCDC = (1 << 0), |
Laurent Pinchart | be9a1b9 | 2012-05-25 08:35:10 -0300 | [diff] [blame] | 93 | OMAP3_ISP_SUBCLK_AEWB = (1 << 1), |
| 94 | OMAP3_ISP_SUBCLK_AF = (1 << 2), |
| 95 | OMAP3_ISP_SUBCLK_HIST = (1 << 3), |
| 96 | OMAP3_ISP_SUBCLK_PREVIEW = (1 << 4), |
| 97 | OMAP3_ISP_SUBCLK_RESIZER = (1 << 5), |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 98 | }; |
| 99 | |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 100 | /* ISP: OMAP 34xx ES 1.0 */ |
| 101 | #define ISP_REVISION_1_0 0x10 |
| 102 | /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */ |
| 103 | #define ISP_REVISION_2_0 0x20 |
| 104 | /* ISP2P: OMAP 36xx */ |
| 105 | #define ISP_REVISION_15_0 0xF0 |
| 106 | |
| 107 | /* |
| 108 | * struct isp_res_mapping - Map ISP io resources to ISP revision. |
| 109 | * @isp_rev: ISP_REVISION_x_x |
| 110 | * @map: bitmap for enum isp_mem_resources |
| 111 | */ |
| 112 | struct isp_res_mapping { |
| 113 | u32 isp_rev; |
| 114 | u32 map; |
| 115 | }; |
| 116 | |
| 117 | /* |
| 118 | * struct isp_reg - Structure for ISP register values. |
| 119 | * @reg: 32-bit Register address. |
| 120 | * @val: 32-bit Register value. |
| 121 | */ |
| 122 | struct isp_reg { |
| 123 | enum isp_mem_resources mmio_range; |
| 124 | u32 reg; |
| 125 | u32 val; |
| 126 | }; |
| 127 | |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 128 | struct isp_platform_callback { |
| 129 | u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel); |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | /* |
| 133 | * struct isp_device - ISP device structure. |
| 134 | * @dev: Device pointer specific to the OMAP3 ISP. |
| 135 | * @revision: Stores current ISP module revision. |
| 136 | * @irq_num: Currently used IRQ number. |
| 137 | * @mmio_base: Array with kernel base addresses for ioremapped ISP register |
| 138 | * regions. |
| 139 | * @mmio_base_phys: Array with physical L4 bus addresses for ISP register |
| 140 | * regions. |
| 141 | * @mmio_size: Array with ISP register regions size in bytes. |
| 142 | * @raw_dmamask: Raw DMA mask |
| 143 | * @stat_lock: Spinlock for handling statistics |
| 144 | * @isp_mutex: Mutex for serializing requests to ISP. |
Laurent Pinchart | 1567bb7 | 2011-11-18 11:28:24 -0300 | [diff] [blame] | 145 | * @crashed: Bitmask of crashed entities (indexed by entity ID) |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 146 | * @has_context: Context has been saved at least once and can be restored. |
| 147 | * @ref_count: Reference count for handling multiple ISP requests. |
| 148 | * @cam_ick: Pointer to camera interface clock structure. |
| 149 | * @cam_mclk: Pointer to camera functional clock structure. |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 150 | * @csi2_fck: Pointer to camera CSI2 complexIO clock structure. |
| 151 | * @l3_ick: Pointer to OMAP3 L3 bus interface clock. |
| 152 | * @irq: Currently attached ISP ISR callbacks information structure. |
| 153 | * @isp_af: Pointer to current settings for ISP AutoFocus SCM. |
| 154 | * @isp_hist: Pointer to current settings for ISP Histogram SCM. |
| 155 | * @isp_h3a: Pointer to current settings for ISP Auto Exposure and |
| 156 | * White Balance SCM. |
| 157 | * @isp_res: Pointer to current settings for ISP Resizer. |
| 158 | * @isp_prev: Pointer to current settings for ISP Preview. |
| 159 | * @isp_ccdc: Pointer to current settings for ISP CCDC. |
| 160 | * @iommu: Pointer to requested IOMMU instance for ISP. |
| 161 | * @platform_cb: ISP driver callback function pointers for platform code |
| 162 | * |
| 163 | * This structure is used to store the OMAP ISP Information. |
| 164 | */ |
| 165 | struct isp_device { |
| 166 | struct v4l2_device v4l2_dev; |
| 167 | struct media_device media_dev; |
| 168 | struct device *dev; |
| 169 | u32 revision; |
| 170 | |
| 171 | /* platform HW resources */ |
| 172 | struct isp_platform_data *pdata; |
| 173 | unsigned int irq_num; |
| 174 | |
| 175 | void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST]; |
| 176 | unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST]; |
| 177 | resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST]; |
| 178 | |
| 179 | u64 raw_dmamask; |
| 180 | |
| 181 | /* ISP Obj */ |
| 182 | spinlock_t stat_lock; /* common lock for statistic drivers */ |
| 183 | struct mutex isp_mutex; /* For handling ref_count field */ |
Laurent Pinchart | 1567bb7 | 2011-11-18 11:28:24 -0300 | [diff] [blame] | 184 | u32 crashed; |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 185 | int has_context; |
| 186 | int ref_count; |
| 187 | unsigned int autoidle; |
| 188 | u32 xclk_divisor[2]; /* Two clocks, a and b. */ |
| 189 | #define ISP_CLK_CAM_ICK 0 |
| 190 | #define ISP_CLK_CAM_MCLK 1 |
Laurent Pinchart | 6d1aa02 | 2012-11-10 12:06:25 +0100 | [diff] [blame] | 191 | #define ISP_CLK_CSI2_FCK 2 |
| 192 | #define ISP_CLK_L3_ICK 3 |
| 193 | struct clk *clock[4]; |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 194 | |
| 195 | /* ISP modules */ |
| 196 | struct ispstat isp_af; |
| 197 | struct ispstat isp_aewb; |
| 198 | struct ispstat isp_hist; |
| 199 | struct isp_res_device isp_res; |
| 200 | struct isp_prev_device isp_prev; |
| 201 | struct isp_ccdc_device isp_ccdc; |
| 202 | struct isp_csi2_device isp_csi2a; |
| 203 | struct isp_csi2_device isp_csi2c; |
| 204 | struct isp_ccp2_device isp_ccp2; |
| 205 | struct isp_csiphy isp_csiphy1; |
| 206 | struct isp_csiphy isp_csiphy2; |
| 207 | |
| 208 | unsigned int sbl_resources; |
| 209 | unsigned int subclk_resources; |
| 210 | |
Ohad Ben-Cohen | f626b52 | 2011-06-02 01:46:12 +0300 | [diff] [blame] | 211 | struct iommu_domain *domain; |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 212 | |
| 213 | struct isp_platform_callback platform_cb; |
| 214 | }; |
| 215 | |
| 216 | #define v4l2_dev_to_isp_device(dev) \ |
| 217 | container_of(dev, struct isp_device, v4l2_dev) |
| 218 | |
| 219 | void omap3isp_hist_dma_done(struct isp_device *isp); |
| 220 | |
| 221 | void omap3isp_flush(struct isp_device *isp); |
| 222 | |
| 223 | int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, |
| 224 | atomic_t *stopping); |
| 225 | |
| 226 | int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait, |
| 227 | atomic_t *stopping); |
| 228 | |
| 229 | int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe, |
| 230 | enum isp_pipeline_stream_state state); |
| 231 | void omap3isp_configure_bridge(struct isp_device *isp, |
| 232 | enum ccdc_input_entity input, |
Michael Jones | c09af04 | 2011-03-29 05:19:09 -0300 | [diff] [blame] | 233 | const struct isp_parallel_platform_data *pdata, |
Laurent Pinchart | c51364c | 2011-08-31 11:03:53 -0300 | [diff] [blame] | 234 | unsigned int shift, unsigned int bridge); |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 235 | |
Sakari Ailus | 448de7e | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 236 | struct isp_device *omap3isp_get(struct isp_device *isp); |
| 237 | void omap3isp_put(struct isp_device *isp); |
| 238 | |
| 239 | void omap3isp_print_status(struct isp_device *isp); |
| 240 | |
| 241 | void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res); |
| 242 | void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res); |
| 243 | |
| 244 | void omap3isp_subclk_enable(struct isp_device *isp, |
| 245 | enum isp_subclk_resource res); |
| 246 | void omap3isp_subclk_disable(struct isp_device *isp, |
| 247 | enum isp_subclk_resource res); |
| 248 | |
| 249 | int omap3isp_pipeline_pm_use(struct media_entity *entity, int use); |
| 250 | |
| 251 | int omap3isp_register_entities(struct platform_device *pdev, |
| 252 | struct v4l2_device *v4l2_dev); |
| 253 | void omap3isp_unregister_entities(struct platform_device *pdev); |
| 254 | |
| 255 | /* |
| 256 | * isp_reg_readl - Read value of an OMAP3 ISP register |
| 257 | * @dev: Device pointer specific to the OMAP3 ISP. |
| 258 | * @isp_mmio_range: Range to which the register offset refers to. |
| 259 | * @reg_offset: Register offset to read from. |
| 260 | * |
| 261 | * Returns an unsigned 32 bit value with the required register contents. |
| 262 | */ |
| 263 | static inline |
| 264 | u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, |
| 265 | u32 reg_offset) |
| 266 | { |
| 267 | return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); |
| 268 | } |
| 269 | |
| 270 | /* |
| 271 | * isp_reg_writel - Write value to an OMAP3 ISP register |
| 272 | * @dev: Device pointer specific to the OMAP3 ISP. |
| 273 | * @reg_value: 32 bit value to write to the register. |
| 274 | * @isp_mmio_range: Range to which the register offset refers to. |
| 275 | * @reg_offset: Register offset to write into. |
| 276 | */ |
| 277 | static inline |
| 278 | void isp_reg_writel(struct isp_device *isp, u32 reg_value, |
| 279 | enum isp_mem_resources isp_mmio_range, u32 reg_offset) |
| 280 | { |
| 281 | __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset); |
| 282 | } |
| 283 | |
| 284 | /* |
| 285 | * isp_reg_and - Clear individual bits in an OMAP3 ISP register |
| 286 | * @dev: Device pointer specific to the OMAP3 ISP. |
| 287 | * @mmio_range: Range to which the register offset refers to. |
| 288 | * @reg: Register offset to work on. |
| 289 | * @clr_bits: 32 bit value which would be cleared in the register. |
| 290 | */ |
| 291 | static inline |
| 292 | void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range, |
| 293 | u32 reg, u32 clr_bits) |
| 294 | { |
| 295 | u32 v = isp_reg_readl(isp, mmio_range, reg); |
| 296 | |
| 297 | isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg); |
| 298 | } |
| 299 | |
| 300 | /* |
| 301 | * isp_reg_set - Set individual bits in an OMAP3 ISP register |
| 302 | * @dev: Device pointer specific to the OMAP3 ISP. |
| 303 | * @mmio_range: Range to which the register offset refers to. |
| 304 | * @reg: Register offset to work on. |
| 305 | * @set_bits: 32 bit value which would be set in the register. |
| 306 | */ |
| 307 | static inline |
| 308 | void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, |
| 309 | u32 reg, u32 set_bits) |
| 310 | { |
| 311 | u32 v = isp_reg_readl(isp, mmio_range, reg); |
| 312 | |
| 313 | isp_reg_writel(isp, v | set_bits, mmio_range, reg); |
| 314 | } |
| 315 | |
| 316 | /* |
| 317 | * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register |
| 318 | * @dev: Device pointer specific to the OMAP3 ISP. |
| 319 | * @mmio_range: Range to which the register offset refers to. |
| 320 | * @reg: Register offset to work on. |
| 321 | * @clr_bits: 32 bit value which would be cleared in the register. |
| 322 | * @set_bits: 32 bit value which would be set in the register. |
| 323 | * |
| 324 | * The clear operation is done first, and then the set operation. |
| 325 | */ |
| 326 | static inline |
| 327 | void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range, |
| 328 | u32 reg, u32 clr_bits, u32 set_bits) |
| 329 | { |
| 330 | u32 v = isp_reg_readl(isp, mmio_range, reg); |
| 331 | |
| 332 | isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); |
| 333 | } |
| 334 | |
| 335 | static inline enum v4l2_buf_type |
| 336 | isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad) |
| 337 | { |
| 338 | if (pad >= subdev->entity.num_pads) |
| 339 | return 0; |
| 340 | |
| 341 | if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK) |
| 342 | return V4L2_BUF_TYPE_VIDEO_OUTPUT; |
| 343 | else |
| 344 | return V4L2_BUF_TYPE_VIDEO_CAPTURE; |
| 345 | } |
| 346 | |
| 347 | #endif /* OMAP3_ISP_CORE_H */ |