Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007, Michael Ellerman, IBM Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version |
| 7 | * 2 of the License, or (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | |
| 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/irq.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/pci.h> |
| 15 | #include <linux/msi.h> |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 16 | #include <linux/of_platform.h> |
Michael Ellerman | 72cac21 | 2008-05-23 14:21:30 +1000 | [diff] [blame] | 17 | #include <linux/debugfs.h> |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 18 | |
| 19 | #include <asm/dcr.h> |
| 20 | #include <asm/machdep.h> |
| 21 | #include <asm/prom.h> |
| 22 | |
| 23 | |
| 24 | /* |
| 25 | * MSIC registers, specified as offsets from dcr_base |
| 26 | */ |
| 27 | #define MSIC_CTRL_REG 0x0 |
| 28 | |
| 29 | /* Base Address registers specify FIFO location in BE memory */ |
| 30 | #define MSIC_BASE_ADDR_HI_REG 0x3 |
| 31 | #define MSIC_BASE_ADDR_LO_REG 0x4 |
| 32 | |
| 33 | /* Hold the read/write offsets into the FIFO */ |
| 34 | #define MSIC_READ_OFFSET_REG 0x5 |
| 35 | #define MSIC_WRITE_OFFSET_REG 0x6 |
| 36 | |
| 37 | |
| 38 | /* MSIC control register flags */ |
| 39 | #define MSIC_CTRL_ENABLE 0x0001 |
| 40 | #define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002 |
| 41 | #define MSIC_CTRL_IRQ_ENABLE 0x0008 |
| 42 | #define MSIC_CTRL_FULL_STOP_ENABLE 0x0010 |
| 43 | |
| 44 | /* |
| 45 | * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB. |
| 46 | * Currently we're using a 64KB FIFO size. |
| 47 | */ |
| 48 | #define MSIC_FIFO_SIZE_SHIFT 16 |
| 49 | #define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT) |
| 50 | |
| 51 | /* |
| 52 | * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits |
| 53 | * 8-9 of the MSIC control reg. |
| 54 | */ |
| 55 | #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300) |
| 56 | |
| 57 | /* |
| 58 | * We need to mask the read/write offsets to make sure they stay within |
| 59 | * the bounds of the FIFO. Also they should always be 16-byte aligned. |
| 60 | */ |
| 61 | #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu) |
| 62 | |
| 63 | /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */ |
| 64 | #define MSIC_FIFO_ENTRY_SIZE 0x10 |
| 65 | |
| 66 | |
| 67 | struct axon_msic { |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 68 | struct irq_host *irq_host; |
Michael Ellerman | de4c928 | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 69 | __le32 *fifo_virt; |
| 70 | dma_addr_t fifo_phys; |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 71 | dcr_host_t dcr_host; |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 72 | u32 read_offset; |
Michael Ellerman | 72cac21 | 2008-05-23 14:21:30 +1000 | [diff] [blame] | 73 | #ifdef DEBUG |
| 74 | u32 __iomem *trigger; |
| 75 | #endif |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 76 | }; |
| 77 | |
Michael Ellerman | 72cac21 | 2008-05-23 14:21:30 +1000 | [diff] [blame] | 78 | #ifdef DEBUG |
| 79 | void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic); |
| 80 | #else |
| 81 | static inline void axon_msi_debug_setup(struct device_node *dn, |
| 82 | struct axon_msic *msic) { } |
| 83 | #endif |
| 84 | |
| 85 | |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 86 | static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) |
| 87 | { |
| 88 | pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); |
| 89 | |
Michael Ellerman | 83f34df | 2007-10-15 19:34:36 +1000 | [diff] [blame] | 90 | dcr_write(msic->dcr_host, dcr_n, val); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 91 | } |
| 92 | |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 93 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) |
| 94 | { |
| 95 | struct axon_msic *msic = get_irq_data(irq); |
| 96 | u32 write_offset, msi; |
| 97 | int idx; |
| 98 | |
Michael Ellerman | 2843e7f | 2007-10-15 19:34:38 +1000 | [diff] [blame] | 99 | write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 100 | pr_debug("axon_msi: original write_offset 0x%x\n", write_offset); |
| 101 | |
| 102 | /* write_offset doesn't wrap properly, so we have to mask it */ |
| 103 | write_offset &= MSIC_FIFO_SIZE_MASK; |
| 104 | |
| 105 | while (msic->read_offset != write_offset) { |
| 106 | idx = msic->read_offset / sizeof(__le32); |
Michael Ellerman | de4c928 | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 107 | msi = le32_to_cpu(msic->fifo_virt[idx]); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 108 | msi &= 0xFFFF; |
| 109 | |
| 110 | pr_debug("axon_msi: woff %x roff %x msi %x\n", |
| 111 | write_offset, msic->read_offset, msi); |
| 112 | |
| 113 | msic->read_offset += MSIC_FIFO_ENTRY_SIZE; |
| 114 | msic->read_offset &= MSIC_FIFO_SIZE_MASK; |
| 115 | |
| 116 | if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) |
| 117 | generic_handle_irq(msi); |
| 118 | else |
| 119 | pr_debug("axon_msi: invalid irq 0x%x!\n", msi); |
| 120 | } |
| 121 | |
| 122 | desc->chip->eoi(irq); |
| 123 | } |
| 124 | |
| 125 | static struct axon_msic *find_msi_translator(struct pci_dev *dev) |
| 126 | { |
| 127 | struct irq_host *irq_host; |
| 128 | struct device_node *dn, *tmp; |
| 129 | const phandle *ph; |
| 130 | struct axon_msic *msic = NULL; |
| 131 | |
Michael Ellerman | db220b2 | 2007-09-17 16:03:45 +1000 | [diff] [blame] | 132 | dn = of_node_get(pci_device_to_OF_node(dev)); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 133 | if (!dn) { |
| 134 | dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n"); |
| 135 | return NULL; |
| 136 | } |
| 137 | |
Michael Ellerman | 988479e | 2008-04-24 12:08:54 +1000 | [diff] [blame] | 138 | for (; dn; dn = of_get_next_parent(dn)) { |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 139 | ph = of_get_property(dn, "msi-translator", NULL); |
| 140 | if (ph) |
| 141 | break; |
| 142 | } |
| 143 | |
| 144 | if (!ph) { |
| 145 | dev_dbg(&dev->dev, |
| 146 | "axon_msi: no msi-translator property found\n"); |
| 147 | goto out_error; |
| 148 | } |
| 149 | |
| 150 | tmp = dn; |
| 151 | dn = of_find_node_by_phandle(*ph); |
Stephen Rothwell | c6d0117 | 2008-02-05 13:13:15 +1100 | [diff] [blame] | 152 | of_node_put(tmp); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 153 | if (!dn) { |
| 154 | dev_dbg(&dev->dev, |
| 155 | "axon_msi: msi-translator doesn't point to a node\n"); |
| 156 | goto out_error; |
| 157 | } |
| 158 | |
| 159 | irq_host = irq_find_host(dn); |
| 160 | if (!irq_host) { |
| 161 | dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n", |
| 162 | dn->full_name); |
| 163 | goto out_error; |
| 164 | } |
| 165 | |
| 166 | msic = irq_host->host_data; |
| 167 | |
| 168 | out_error: |
| 169 | of_node_put(dn); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 170 | |
| 171 | return msic; |
| 172 | } |
| 173 | |
| 174 | static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type) |
| 175 | { |
| 176 | if (!find_msi_translator(dev)) |
| 177 | return -ENODEV; |
| 178 | |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg) |
| 183 | { |
Michael Ellerman | 988479e | 2008-04-24 12:08:54 +1000 | [diff] [blame] | 184 | struct device_node *dn; |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 185 | struct msi_desc *entry; |
| 186 | int len; |
| 187 | const u32 *prop; |
| 188 | |
Michael Ellerman | db220b2 | 2007-09-17 16:03:45 +1000 | [diff] [blame] | 189 | dn = of_node_get(pci_device_to_OF_node(dev)); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 190 | if (!dn) { |
| 191 | dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n"); |
| 192 | return -ENODEV; |
| 193 | } |
| 194 | |
| 195 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
| 196 | |
Michael Ellerman | 988479e | 2008-04-24 12:08:54 +1000 | [diff] [blame] | 197 | for (; dn; dn = of_get_next_parent(dn)) { |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 198 | if (entry->msi_attrib.is_64) { |
| 199 | prop = of_get_property(dn, "msi-address-64", &len); |
| 200 | if (prop) |
| 201 | break; |
| 202 | } |
| 203 | |
| 204 | prop = of_get_property(dn, "msi-address-32", &len); |
| 205 | if (prop) |
| 206 | break; |
| 207 | } |
| 208 | |
| 209 | if (!prop) { |
| 210 | dev_dbg(&dev->dev, |
| 211 | "axon_msi: no msi-address-(32|64) properties found\n"); |
| 212 | return -ENOENT; |
| 213 | } |
| 214 | |
| 215 | switch (len) { |
| 216 | case 8: |
| 217 | msg->address_hi = prop[0]; |
| 218 | msg->address_lo = prop[1]; |
| 219 | break; |
| 220 | case 4: |
| 221 | msg->address_hi = 0; |
| 222 | msg->address_lo = prop[0]; |
| 223 | break; |
| 224 | default: |
| 225 | dev_dbg(&dev->dev, |
| 226 | "axon_msi: malformed msi-address-(32|64) property\n"); |
| 227 | of_node_put(dn); |
| 228 | return -EINVAL; |
| 229 | } |
| 230 | |
| 231 | of_node_put(dn); |
| 232 | |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
| 237 | { |
| 238 | unsigned int virq, rc; |
| 239 | struct msi_desc *entry; |
| 240 | struct msi_msg msg; |
| 241 | struct axon_msic *msic; |
| 242 | |
| 243 | msic = find_msi_translator(dev); |
| 244 | if (!msic) |
| 245 | return -ENODEV; |
| 246 | |
| 247 | rc = setup_msi_msg_address(dev, &msg); |
| 248 | if (rc) |
| 249 | return rc; |
| 250 | |
| 251 | /* We rely on being able to stash a virq in a u16 */ |
| 252 | BUILD_BUG_ON(NR_IRQS > 65536); |
| 253 | |
| 254 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 255 | virq = irq_create_direct_mapping(msic->irq_host); |
| 256 | if (virq == NO_IRQ) { |
| 257 | dev_warn(&dev->dev, |
| 258 | "axon_msi: virq allocation failed!\n"); |
| 259 | return -1; |
| 260 | } |
| 261 | dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); |
| 262 | |
| 263 | set_irq_msi(virq, entry); |
| 264 | msg.data = virq; |
| 265 | write_msi_msg(virq, &msg); |
| 266 | } |
| 267 | |
| 268 | return 0; |
| 269 | } |
| 270 | |
| 271 | static void axon_msi_teardown_msi_irqs(struct pci_dev *dev) |
| 272 | { |
| 273 | struct msi_desc *entry; |
| 274 | |
| 275 | dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n"); |
| 276 | |
| 277 | list_for_each_entry(entry, &dev->msi_list, list) { |
| 278 | if (entry->irq == NO_IRQ) |
| 279 | continue; |
| 280 | |
| 281 | set_irq_msi(entry->irq, NULL); |
| 282 | irq_dispose_mapping(entry->irq); |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | static struct irq_chip msic_irq_chip = { |
| 287 | .mask = mask_msi_irq, |
| 288 | .unmask = unmask_msi_irq, |
| 289 | .shutdown = unmask_msi_irq, |
| 290 | .typename = "AXON-MSI", |
| 291 | }; |
| 292 | |
| 293 | static int msic_host_map(struct irq_host *h, unsigned int virq, |
| 294 | irq_hw_number_t hw) |
| 295 | { |
| 296 | set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); |
| 297 | |
| 298 | return 0; |
| 299 | } |
| 300 | |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 301 | static struct irq_host_ops msic_host_ops = { |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 302 | .map = msic_host_map, |
| 303 | }; |
| 304 | |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 305 | static int axon_msi_shutdown(struct of_device *device) |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 306 | { |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 307 | struct axon_msic *msic = device->dev.platform_data; |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 308 | u32 tmp; |
| 309 | |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 310 | pr_debug("axon_msi: disabling %s\n", |
| 311 | msic->irq_host->of_node->full_name); |
| 312 | tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); |
| 313 | tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; |
| 314 | msic_dcr_write(msic, MSIC_CTRL_REG, tmp); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 315 | |
| 316 | return 0; |
| 317 | } |
| 318 | |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 319 | static int axon_msi_probe(struct of_device *device, |
| 320 | const struct of_device_id *device_id) |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 321 | { |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 322 | struct device_node *dn = device->node; |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 323 | struct axon_msic *msic; |
| 324 | unsigned int virq; |
Michael Ellerman | 4acb8896 | 2007-09-17 16:05:02 +1000 | [diff] [blame] | 325 | int dcr_base, dcr_len; |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 326 | |
| 327 | pr_debug("axon_msi: setting up dn %s\n", dn->full_name); |
| 328 | |
| 329 | msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL); |
| 330 | if (!msic) { |
| 331 | printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n", |
| 332 | dn->full_name); |
| 333 | goto out; |
| 334 | } |
| 335 | |
Michael Ellerman | 4acb8896 | 2007-09-17 16:05:02 +1000 | [diff] [blame] | 336 | dcr_base = dcr_resource_start(dn, 0); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 337 | dcr_len = dcr_resource_len(dn, 0); |
| 338 | |
Michael Ellerman | 4acb8896 | 2007-09-17 16:05:02 +1000 | [diff] [blame] | 339 | if (dcr_base == 0 || dcr_len == 0) { |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 340 | printk(KERN_ERR |
| 341 | "axon_msi: couldn't parse dcr properties on %s\n", |
| 342 | dn->full_name); |
| 343 | goto out; |
| 344 | } |
| 345 | |
Michael Ellerman | 4acb8896 | 2007-09-17 16:05:02 +1000 | [diff] [blame] | 346 | msic->dcr_host = dcr_map(dn, dcr_base, dcr_len); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 347 | if (!DCR_MAP_OK(msic->dcr_host)) { |
| 348 | printk(KERN_ERR "axon_msi: dcr_map failed for %s\n", |
| 349 | dn->full_name); |
| 350 | goto out_free_msic; |
| 351 | } |
| 352 | |
Michael Ellerman | de4c928 | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 353 | msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, |
| 354 | &msic->fifo_phys, GFP_KERNEL); |
| 355 | if (!msic->fifo_virt) { |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 356 | printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n", |
| 357 | dn->full_name); |
| 358 | goto out_free_msic; |
| 359 | } |
| 360 | |
Michael Ellerman | 997526d | 2008-05-26 12:12:30 +1000 | [diff] [blame] | 361 | virq = irq_of_parse_and_map(dn, 0); |
| 362 | if (virq == NO_IRQ) { |
| 363 | printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n", |
| 364 | dn->full_name); |
| 365 | goto out_free_fifo; |
| 366 | } |
| 367 | |
Michael Ellerman | 19fc65b | 2008-05-26 12:12:32 +1000 | [diff] [blame] | 368 | msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP, |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 369 | NR_IRQS, &msic_host_ops, 0); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 370 | if (!msic->irq_host) { |
| 371 | printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n", |
| 372 | dn->full_name); |
| 373 | goto out_free_fifo; |
| 374 | } |
| 375 | |
| 376 | msic->irq_host->host_data = msic; |
| 377 | |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 378 | set_irq_data(virq, msic); |
| 379 | set_irq_chained_handler(virq, axon_msi_cascade); |
| 380 | pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq); |
| 381 | |
| 382 | /* Enable the MSIC hardware */ |
Michael Ellerman | de4c928 | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 383 | msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 384 | msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG, |
Michael Ellerman | de4c928 | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 385 | msic->fifo_phys & 0xFFFFFFFF); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 386 | msic_dcr_write(msic, MSIC_CTRL_REG, |
| 387 | MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE | |
| 388 | MSIC_CTRL_FIFO_SIZE); |
| 389 | |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 390 | device->dev.platform_data = msic; |
| 391 | |
| 392 | ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs; |
| 393 | ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs; |
| 394 | ppc_md.msi_check_device = axon_msi_check_device; |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 395 | |
Michael Ellerman | 72cac21 | 2008-05-23 14:21:30 +1000 | [diff] [blame] | 396 | axon_msi_debug_setup(dn, msic); |
| 397 | |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 398 | printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name); |
| 399 | |
| 400 | return 0; |
| 401 | |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 402 | out_free_fifo: |
Michael Ellerman | de4c928 | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 403 | dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt, |
| 404 | msic->fifo_phys); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 405 | out_free_msic: |
| 406 | kfree(msic); |
| 407 | out: |
| 408 | |
| 409 | return -1; |
| 410 | } |
| 411 | |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 412 | static const struct of_device_id axon_msi_device_id[] = { |
| 413 | { |
| 414 | .compatible = "ibm,axon-msic" |
| 415 | }, |
| 416 | {} |
| 417 | }; |
| 418 | |
| 419 | static struct of_platform_driver axon_msi_driver = { |
| 420 | .match_table = axon_msi_device_id, |
| 421 | .probe = axon_msi_probe, |
| 422 | .shutdown = axon_msi_shutdown, |
| 423 | .driver = { |
| 424 | .name = "axon-msi" |
| 425 | }, |
| 426 | }; |
| 427 | |
| 428 | static int __init axon_msi_init(void) |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 429 | { |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 430 | return of_register_platform_driver(&axon_msi_driver); |
Michael Ellerman | ce21b3c | 2007-07-20 21:39:28 +0200 | [diff] [blame] | 431 | } |
Michael Ellerman | e4347df | 2008-01-25 16:59:14 +1100 | [diff] [blame] | 432 | subsys_initcall(axon_msi_init); |
Michael Ellerman | 72cac21 | 2008-05-23 14:21:30 +1000 | [diff] [blame] | 433 | |
| 434 | |
| 435 | #ifdef DEBUG |
| 436 | static int msic_set(void *data, u64 val) |
| 437 | { |
| 438 | struct axon_msic *msic = data; |
| 439 | out_le32(msic->trigger, val); |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | static int msic_get(void *data, u64 *val) |
| 444 | { |
| 445 | *val = 0; |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n"); |
| 450 | |
| 451 | void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) |
| 452 | { |
| 453 | char name[8]; |
| 454 | u64 addr; |
| 455 | |
| 456 | addr = of_translate_address(dn, of_get_property(dn, "reg", NULL)); |
| 457 | if (addr == OF_BAD_ADDR) { |
| 458 | pr_debug("axon_msi: couldn't translate reg property\n"); |
| 459 | return; |
| 460 | } |
| 461 | |
| 462 | msic->trigger = ioremap(addr, 0x4); |
| 463 | if (!msic->trigger) { |
| 464 | pr_debug("axon_msi: ioremap failed\n"); |
| 465 | return; |
| 466 | } |
| 467 | |
| 468 | snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn)); |
| 469 | |
| 470 | if (!debugfs_create_file(name, 0600, powerpc_debugfs_root, |
| 471 | msic, &fops_msic)) { |
| 472 | pr_debug("axon_msi: debugfs_create_file failed!\n"); |
| 473 | return; |
| 474 | } |
| 475 | } |
| 476 | #endif /* DEBUG */ |