blob: 08371dbae543d8e8c07be0477db16d27ca46c559 [file] [log] [blame]
Joe.C0c3fb202014-11-11 15:53:43 +08001/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
James Liao3cc17a52015-07-07 14:45:10 +020015#include <dt-bindings/clock/mt8135-clk.h>
Joe.C0c3fb202014-11-11 15:53:43 +080016#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
Sascha Hauer8dd29d22015-07-07 14:45:11 +020018#include <dt-bindings/reset-controller/mt8135-resets.h>
Joe.C0c3fb202014-11-11 15:53:43 +080019#include "skeleton64.dtsi"
Hongzhou Yangcfb11672015-05-01 14:49:30 +080020#include "mt8135-pinfunc.h"
Joe.C0c3fb202014-11-11 15:53:43 +080021
22/ {
23 compatible = "mediatek,mt8135";
Yingjoe Chene0bed072014-11-25 09:04:00 +010024 interrupt-parent = <&sysirq>;
Joe.C0c3fb202014-11-11 15:53:43 +080025
26 cpu-map {
27 cluster0 {
28 core0 {
29 cpu = <&cpu0>;
30 };
31 core1 {
32 cpu = <&cpu1>;
33 };
34 };
35
36 cluster1 {
37 core0 {
38 cpu = <&cpu2>;
39 };
40 core1 {
41 cpu = <&cpu3>;
42 };
43 };
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <0x000>;
54 };
55
56 cpu1: cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a7";
59 reg = <0x001>;
60 };
61
62 cpu2: cpu@100 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <0x100>;
66 };
67
68 cpu3: cpu@101 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a15";
71 reg = <0x101>;
72 };
73 };
74
75 clocks {
76 #address-cells = <2>;
77 #size-cells = <2>;
78 compatible = "simple-bus";
79 ranges;
80
81 system_clk: dummy13m {
82 compatible = "fixed-clock";
83 clock-frequency = <13000000>;
84 #clock-cells = <0>;
85 };
86
87 rtc_clk: dummy32k {
88 compatible = "fixed-clock";
89 clock-frequency = <32000>;
90 #clock-cells = <0>;
91 };
Eddie Huang07149472014-10-22 15:12:00 +020092
James Liao3cc17a52015-07-07 14:45:10 +020093 clk26m: clk26m {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <26000000>;
97 };
Joe.C0c3fb202014-11-11 15:53:43 +080098 };
99
100 soc {
101 #address-cells = <2>;
102 #size-cells = <2>;
103 compatible = "simple-bus";
104 ranges;
105
James Liao3cc17a52015-07-07 14:45:10 +0200106 topckgen: topckgen@10000000 {
107 compatible = "mediatek,mt8135-topckgen";
108 reg = <0 0x10000000 0 0x1000>;
109 #clock-cells = <1>;
110 };
111
112 infracfg: infracfg@10001000 {
113 #reset-cells = <1>;
114 #clock-cells = <1>;
115 compatible = "mediatek,mt8135-infracfg", "syscon";
116 reg = <0 0x10001000 0 0x1000>;
117 };
118
119 pericfg: pericfg@10003000 {
120 #reset-cells = <1>;
121 #clock-cells = <1>;
122 compatible = "mediatek,mt8135-pericfg", "syscon";
123 reg = <0 0x10003000 0 0x1000>;
124 };
125
Hongzhou Yangcfb11672015-05-01 14:49:30 +0800126 /*
127 * Pinctrl access register at 0x10005000 and 0x1020c000 through
128 * regmap. Register 0x1000b000 is used by EINT.
129 */
130 pio: pinctrl@10005000 {
131 compatible = "mediatek,mt8135-pinctrl";
132 reg = <0 0x1000b000 0 0x1000>;
133 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
134 pins-are-numbered;
135 gpio-controller;
136 #gpio-cells = <2>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
139 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
142 };
143
144 syscfg_pctl_a: syscfg_pctl_a@10005000 {
145 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
146 reg = <0 0x10005000 0 0x1000>;
147 };
148
Joe.C0c3fb202014-11-11 15:53:43 +0800149 timer: timer@10008000 {
150 compatible = "mediatek,mt8135-timer",
151 "mediatek,mt6577-timer";
152 reg = <0 0x10008000 0 0x80>;
Yingjoe Chene0bed072014-11-25 09:04:00 +0100153 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
Joe.C0c3fb202014-11-11 15:53:43 +0800154 clocks = <&system_clk>, <&rtc_clk>;
155 clock-names = "system-clk", "rtc-clk";
156 };
157
Sascha Hauer8dd29d22015-07-07 14:45:11 +0200158 pwrap: pwrap@1000f000 {
159 compatible = "mediatek,mt8135-pwrap";
160 reg = <0 0x1000f000 0 0x1000>,
161 <0 0x11017000 0 0x1000>;
162 reg-names = "pwrap", "pwrap-bridge";
163 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
164 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
165 <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
166 reset-names = "pwrap", "pwrap-bridge";
167 clocks = <&clk26m>, <&clk26m>;
168 clock-names = "spi", "wrap";
169 };
170
Yingjoe Chene0bed072014-11-25 09:04:00 +0100171 sysirq: interrupt-controller@10200030 {
172 compatible = "mediatek,mt8135-sysirq",
173 "mediatek,mt6577-sysirq";
174 interrupt-controller;
175 #interrupt-cells = <3>;
176 interrupt-parent = <&gic>;
177 reg = <0 0x10200030 0 0x1c>;
178 };
179
James Liao3cc17a52015-07-07 14:45:10 +0200180 apmixedsys: apmixedsys@10209000 {
181 compatible = "mediatek,mt8135-apmixedsys";
182 reg = <0 0x10209000 0 0x1000>;
183 #clock-cells = <1>;
184 };
185
Hongzhou Yangcfb11672015-05-01 14:49:30 +0800186 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
187 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
188 reg = <0 0x1020c000 0 0x1000>;
189 };
190
Joe.C0c3fb202014-11-11 15:53:43 +0800191 gic: interrupt-controller@10211000 {
192 compatible = "arm,cortex-a15-gic";
193 interrupt-controller;
194 #interrupt-cells = <3>;
Yingjoe Chene0bed072014-11-25 09:04:00 +0100195 interrupt-parent = <&gic>;
Joe.C0c3fb202014-11-11 15:53:43 +0800196 reg = <0 0x10211000 0 0x1000>,
197 <0 0x10212000 0 0x1000>,
198 <0 0x10214000 0 0x2000>,
199 <0 0x10216000 0 0x2000>;
200 };
Eddie Huang07149472014-10-22 15:12:00 +0200201
202 uart0: serial@11006000 {
203 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
204 reg = <0 0x11006000 0 0x400>;
205 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200206 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
207 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200208 status = "disabled";
209 };
210
211 uart1: serial@11007000 {
212 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
213 reg = <0 0x11007000 0 0x400>;
214 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200215 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
216 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200217 status = "disabled";
218 };
219
220 uart2: serial@11008000 {
221 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
222 reg = <0 0x11008000 0 0x400>;
223 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200224 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
225 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200226 status = "disabled";
227 };
228
229 uart3: serial@11009000 {
230 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
231 reg = <0 0x11009000 0 0x400>;
232 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200233 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
234 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200235 status = "disabled";
236 };
237
Joe.C0c3fb202014-11-11 15:53:43 +0800238 };
239};