Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 1 | /* |
| 2 | * SAMSUNG EXYNOS5410 SoC device tree source |
| 3 | * |
| 4 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. |
| 8 | * EXYNOS5410 based board files can include this file and provide |
| 9 | * values for board specfic bindings. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #include "skeleton.dtsi" |
Javier Martinez Canillas | 1462b13 | 2016-02-16 12:25:48 -0300 | [diff] [blame] | 17 | #include "exynos-syscon-restart.dtsi" |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 18 | #include <dt-bindings/clock/exynos5410.h> |
| 19 | |
| 20 | / { |
| 21 | compatible = "samsung,exynos5410", "samsung,exynos5"; |
| 22 | interrupt-parent = <&gic>; |
| 23 | |
Tomasz Figa | 1e64f48 | 2014-06-26 13:24:35 +0200 | [diff] [blame] | 24 | aliases { |
Hakjoo Kim | 1eca825 | 2015-03-15 23:00:33 +0100 | [diff] [blame] | 25 | pinctrl0 = &pinctrl_0; |
| 26 | pinctrl1 = &pinctrl_1; |
| 27 | pinctrl2 = &pinctrl_2; |
| 28 | pinctrl3 = &pinctrl_3; |
Tomasz Figa | 1e64f48 | 2014-06-26 13:24:35 +0200 | [diff] [blame] | 29 | serial0 = &uart0; |
| 30 | serial1 = &uart1; |
| 31 | serial2 = &uart2; |
| 32 | }; |
| 33 | |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 34 | cpus { |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <0>; |
| 37 | |
| 38 | CPU0: cpu@0 { |
| 39 | device_type = "cpu"; |
| 40 | compatible = "arm,cortex-a15"; |
| 41 | reg = <0x0>; |
Andreas Faerber | 22298d6 | 2014-07-08 08:17:14 +0900 | [diff] [blame] | 42 | clock-frequency = <1600000000>; |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 43 | }; |
| 44 | |
| 45 | CPU1: cpu@1 { |
| 46 | device_type = "cpu"; |
| 47 | compatible = "arm,cortex-a15"; |
| 48 | reg = <0x1>; |
Andreas Faerber | 22298d6 | 2014-07-08 08:17:14 +0900 | [diff] [blame] | 49 | clock-frequency = <1600000000>; |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | CPU2: cpu@2 { |
| 53 | device_type = "cpu"; |
| 54 | compatible = "arm,cortex-a15"; |
| 55 | reg = <0x2>; |
Andreas Faerber | 22298d6 | 2014-07-08 08:17:14 +0900 | [diff] [blame] | 56 | clock-frequency = <1600000000>; |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | CPU3: cpu@3 { |
| 60 | device_type = "cpu"; |
| 61 | compatible = "arm,cortex-a15"; |
| 62 | reg = <0x3>; |
Andreas Faerber | 22298d6 | 2014-07-08 08:17:14 +0900 | [diff] [blame] | 63 | clock-frequency = <1600000000>; |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 64 | }; |
| 65 | }; |
| 66 | |
| 67 | soc: soc { |
| 68 | compatible = "simple-bus"; |
| 69 | #address-cells = <1>; |
| 70 | #size-cells = <1>; |
| 71 | ranges; |
| 72 | |
| 73 | combiner: interrupt-controller@10440000 { |
| 74 | compatible = "samsung,exynos4210-combiner"; |
| 75 | #interrupt-cells = <2>; |
| 76 | interrupt-controller; |
| 77 | samsung,combiner-nr = <32>; |
| 78 | reg = <0x10440000 0x1000>; |
| 79 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, |
| 80 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, |
| 81 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, |
| 82 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, |
| 83 | <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, |
| 84 | <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, |
| 85 | <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, |
| 86 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; |
| 87 | }; |
| 88 | |
| 89 | gic: interrupt-controller@10481000 { |
| 90 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; |
| 91 | #interrupt-cells = <3>; |
| 92 | interrupt-controller; |
| 93 | reg = <0x10481000 0x1000>, |
| 94 | <0x10482000 0x1000>, |
| 95 | <0x10484000 0x2000>, |
| 96 | <0x10486000 0x2000>; |
| 97 | interrupts = <1 9 0xf04>; |
| 98 | }; |
| 99 | |
| 100 | chipid@10000000 { |
| 101 | compatible = "samsung,exynos4210-chipid"; |
| 102 | reg = <0x10000000 0x100>; |
| 103 | }; |
| 104 | |
Pankaj Dubey | 4d7820b | 2016-04-11 13:12:28 +0530 | [diff] [blame] | 105 | sromc: memory-controller@12250000 { |
| 106 | compatible = "samsung,exynos4210-srom"; |
Pavel Fedin | d2deef6 | 2015-11-16 10:43:03 +0300 | [diff] [blame] | 107 | reg = <0x12250000 0x14>; |
Pavel Fedin | a090435 | 2015-11-16 10:43:05 +0300 | [diff] [blame] | 108 | #address-cells = <2>; |
| 109 | #size-cells = <1>; |
| 110 | ranges = <0 0 0x04000000 0x20000 |
| 111 | 1 0 0x05000000 0x20000 |
| 112 | 2 0 0x06000000 0x20000 |
| 113 | 3 0 0x07000000 0x20000>; |
Pavel Fedin | d2deef6 | 2015-11-16 10:43:03 +0300 | [diff] [blame] | 114 | }; |
| 115 | |
Andreas Faerber | 0a8f594 | 2014-07-29 06:09:56 +0900 | [diff] [blame] | 116 | pmu_system_controller: system-controller@10040000 { |
| 117 | compatible = "samsung,exynos5410-pmu", "syscon"; |
| 118 | reg = <0x10040000 0x5000>; |
Krzysztof Kozlowski | 2cbc0de | 2016-05-16 10:26:48 +0200 | [diff] [blame^] | 119 | clock-names = "clkout16"; |
| 120 | clocks = <&fin_pll>; |
| 121 | #clock-cells = <1>; |
Andreas Faerber | 0a8f594 | 2014-07-29 06:09:56 +0900 | [diff] [blame] | 122 | }; |
| 123 | |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 124 | mct: mct@101C0000 { |
| 125 | compatible = "samsung,exynos4210-mct"; |
| 126 | reg = <0x101C0000 0xB00>; |
| 127 | interrupt-parent = <&interrupt_map>; |
| 128 | interrupts = <0>, <1>, <2>, <3>, |
| 129 | <4>, <5>, <6>, <7>, |
| 130 | <8>, <9>, <10>, <11>; |
| 131 | clocks = <&fin_pll>, <&clock CLK_MCT>; |
| 132 | clock-names = "fin_pll", "mct"; |
| 133 | |
| 134 | interrupt_map: interrupt-map { |
| 135 | #interrupt-cells = <1>; |
| 136 | #address-cells = <0>; |
| 137 | #size-cells = <0>; |
| 138 | interrupt-map = <0 &combiner 23 3>, |
| 139 | <1 &combiner 23 4>, |
| 140 | <2 &combiner 25 2>, |
| 141 | <3 &combiner 25 3>, |
| 142 | <4 &gic 0 120 0>, |
| 143 | <5 &gic 0 121 0>, |
| 144 | <6 &gic 0 122 0>, |
| 145 | <7 &gic 0 123 0>, |
| 146 | <8 &gic 0 128 0>, |
| 147 | <9 &gic 0 129 0>, |
| 148 | <10 &gic 0 130 0>, |
| 149 | <11 &gic 0 131 0>; |
| 150 | }; |
| 151 | }; |
| 152 | |
| 153 | sysram@02020000 { |
| 154 | compatible = "mmio-sram"; |
| 155 | reg = <0x02020000 0x54000>; |
| 156 | #address-cells = <1>; |
| 157 | #size-cells = <1>; |
| 158 | ranges = <0 0x02020000 0x54000>; |
| 159 | |
| 160 | smp-sysram@0 { |
| 161 | compatible = "samsung,exynos4210-sysram"; |
| 162 | reg = <0x0 0x1000>; |
| 163 | }; |
| 164 | |
| 165 | smp-sysram@53000 { |
| 166 | compatible = "samsung,exynos4210-sysram-ns"; |
| 167 | reg = <0x53000 0x1000>; |
| 168 | }; |
| 169 | }; |
| 170 | |
| 171 | clock: clock-controller@10010000 { |
| 172 | compatible = "samsung,exynos5410-clock"; |
| 173 | reg = <0x10010000 0x30000>; |
| 174 | #clock-cells = <1>; |
| 175 | }; |
| 176 | |
| 177 | mmc_0: mmc@12200000 { |
| 178 | compatible = "samsung,exynos5250-dw-mshc"; |
| 179 | reg = <0x12200000 0x1000>; |
| 180 | interrupts = <0 75 0>; |
| 181 | #address-cells = <1>; |
| 182 | #size-cells = <0>; |
| 183 | clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; |
| 184 | clock-names = "biu", "ciu"; |
| 185 | fifo-depth = <0x80>; |
| 186 | status = "disabled"; |
| 187 | }; |
| 188 | |
| 189 | mmc_1: mmc@12210000 { |
| 190 | compatible = "samsung,exynos5250-dw-mshc"; |
| 191 | reg = <0x12210000 0x1000>; |
| 192 | interrupts = <0 76 0>; |
| 193 | #address-cells = <1>; |
| 194 | #size-cells = <0>; |
| 195 | clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; |
| 196 | clock-names = "biu", "ciu"; |
| 197 | fifo-depth = <0x80>; |
| 198 | status = "disabled"; |
| 199 | }; |
| 200 | |
| 201 | mmc_2: mmc@12220000 { |
| 202 | compatible = "samsung,exynos5250-dw-mshc"; |
| 203 | reg = <0x12220000 0x1000>; |
| 204 | interrupts = <0 77 0>; |
| 205 | #address-cells = <1>; |
| 206 | #size-cells = <0>; |
| 207 | clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; |
| 208 | clock-names = "biu", "ciu"; |
| 209 | fifo-depth = <0x80>; |
| 210 | status = "disabled"; |
| 211 | }; |
| 212 | |
Hakjoo Kim | 1eca825 | 2015-03-15 23:00:33 +0100 | [diff] [blame] | 213 | pinctrl_0: pinctrl@13400000 { |
| 214 | compatible = "samsung,exynos5410-pinctrl"; |
| 215 | reg = <0x13400000 0x1000>; |
| 216 | interrupts = <0 45 0>; |
| 217 | |
| 218 | wakeup-interrupt-controller { |
| 219 | compatible = "samsung,exynos4210-wakeup-eint"; |
| 220 | interrupt-parent = <&gic>; |
| 221 | interrupts = <0 32 0>; |
| 222 | }; |
| 223 | }; |
| 224 | |
| 225 | pinctrl_1: pinctrl@14000000 { |
| 226 | compatible = "samsung,exynos5410-pinctrl"; |
| 227 | reg = <0x14000000 0x1000>; |
| 228 | interrupts = <0 46 0>; |
| 229 | }; |
| 230 | |
| 231 | pinctrl_2: pinctrl@10d10000 { |
| 232 | compatible = "samsung,exynos5410-pinctrl"; |
| 233 | reg = <0x10d10000 0x1000>; |
| 234 | interrupts = <0 50 0>; |
| 235 | }; |
| 236 | |
| 237 | pinctrl_3: pinctrl@03860000 { |
| 238 | compatible = "samsung,exynos5410-pinctrl"; |
| 239 | reg = <0x03860000 0x1000>; |
| 240 | interrupts = <0 47 0>; |
| 241 | }; |
| 242 | |
Tarek Dakhran | 107e6aa | 2014-05-27 06:54:13 +0900 | [diff] [blame] | 243 | uart0: serial@12C00000 { |
| 244 | compatible = "samsung,exynos4210-uart"; |
| 245 | reg = <0x12C00000 0x100>; |
| 246 | interrupts = <0 51 0>; |
| 247 | clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; |
| 248 | clock-names = "uart", "clk_uart_baud0"; |
| 249 | status = "disabled"; |
| 250 | }; |
| 251 | |
| 252 | uart1: serial@12C10000 { |
| 253 | compatible = "samsung,exynos4210-uart"; |
| 254 | reg = <0x12C10000 0x100>; |
| 255 | interrupts = <0 52 0>; |
| 256 | clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; |
| 257 | clock-names = "uart", "clk_uart_baud0"; |
| 258 | status = "disabled"; |
| 259 | }; |
| 260 | |
| 261 | uart2: serial@12C20000 { |
| 262 | compatible = "samsung,exynos4210-uart"; |
| 263 | reg = <0x12C20000 0x100>; |
| 264 | interrupts = <0 53 0>; |
| 265 | clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; |
| 266 | clock-names = "uart", "clk_uart_baud0"; |
| 267 | status = "disabled"; |
| 268 | }; |
| 269 | }; |
| 270 | }; |
Hakjoo Kim | 1eca825 | 2015-03-15 23:00:33 +0100 | [diff] [blame] | 271 | |
| 272 | #include "exynos5410-pinctrl.dtsi" |