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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_MSR_H
2#define _ASM_X86_MSR_H
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +02003
4#include <asm/msr-index.h>
5
Glauber de Oliveira Costa8f12dea2008-01-30 13:31:06 +01006#ifndef __ASSEMBLY__
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +01007
Jaswinder Singh Rajput8fa62ad2009-06-17 14:11:10 +05308#include <linux/types.h>
H. Peter Anvinff55df52009-08-31 14:16:57 -07009#include <linux/ioctl.h>
10
11#define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8])
12#define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8])
13
14#ifdef __KERNEL__
15
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010016#include <asm/asm.h>
17#include <asm/errno.h>
Borislav Petkov6bc10962009-05-22 12:12:01 +020018#include <asm/cpumask.h>
19
20struct msr {
21 union {
22 struct {
23 u32 l;
24 u32 h;
25 };
26 u64 q;
27 };
28};
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010029
Borislav Petkov6ede31e2009-12-17 00:16:25 +010030struct msr_info {
31 u32 msr_no;
32 struct msr reg;
33 struct msr *msrs;
34 int err;
35};
36
37struct msr_regs_info {
38 u32 *regs;
39 int err;
40};
41
Andrew Morton1e160cc2008-01-30 13:31:17 +010042static inline unsigned long long native_read_tscp(unsigned int *aux)
Glauber de Oliveira Costa8f12dea2008-01-30 13:31:06 +010043{
44 unsigned long low, high;
Joe Perchesabb0ade2008-03-23 01:02:51 -070045 asm volatile(".byte 0x0f,0x01,0xf9"
46 : "=a" (low), "=d" (high), "=c" (*aux));
Max Asbock41aefdc2008-06-25 14:45:28 -070047 return low | ((u64)high << 32);
Glauber de Oliveira Costa8f12dea2008-01-30 13:31:06 +010048}
49
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010050/*
Jike Songd4f1b102008-10-17 13:25:07 +080051 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
52 * constraint has different meanings. For i386, "A" means exactly
53 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
54 * it means rax *or* rdx.
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010055 */
56#ifdef CONFIG_X86_64
57#define DECLARE_ARGS(val, low, high) unsigned low, high
Joe Perchesabb0ade2008-03-23 01:02:51 -070058#define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010059#define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
60#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
61#else
62#define DECLARE_ARGS(val, low, high) unsigned long long val
63#define EAX_EDX_VAL(val, low, high) (val)
64#define EAX_EDX_ARGS(val, low, high) "A" (val)
65#define EAX_EDX_RET(val, low, high) "=A" (val)
Glauber de Oliveira Costa8f12dea2008-01-30 13:31:06 +010066#endif
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020067
68static inline unsigned long long native_read_msr(unsigned int msr)
69{
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010070 DECLARE_ARGS(val, low, high);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020071
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010072 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
73 return EAX_EDX_VAL(val, low, high);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020074}
75
76static inline unsigned long long native_read_msr_safe(unsigned int msr,
77 int *err)
78{
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010079 DECLARE_ARGS(val, low, high);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020080
H. Peter Anvin08970fc2008-08-25 22:39:15 -070081 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020082 "1:\n\t"
83 ".section .fixup,\"ax\"\n\t"
H. Peter Anvin08970fc2008-08-25 22:39:15 -070084 "3: mov %[fault],%[err] ; jmp 1b\n\t"
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020085 ".previous\n\t"
Joe Perchesabb0ade2008-03-23 01:02:51 -070086 _ASM_EXTABLE(2b, 3b)
H. Peter Anvin08970fc2008-08-25 22:39:15 -070087 : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
H. Peter Anvin0cc02132009-08-31 14:23:29 -070088 : "c" (msr), [fault] "i" (-EIO));
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +010089 return EAX_EDX_VAL(val, low, high);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020090}
91
Glauber de Oliveira Costac9dcda52008-01-30 13:31:07 +010092static inline void native_write_msr(unsigned int msr,
93 unsigned low, unsigned high)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020094{
Jeremy Fitzhardingeaf2b1c62008-06-25 00:18:59 -040095 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +020096}
97
Frederic Weisbecker0ca59dd2008-12-24 23:30:02 +010098/* Can be uninlined because referenced by paravirt */
99notrace static inline int native_write_msr_safe(unsigned int msr,
Glauber de Oliveira Costac9dcda52008-01-30 13:31:07 +0100100 unsigned low, unsigned high)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200101{
102 int err;
H. Peter Anvin08970fc2008-08-25 22:39:15 -0700103 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200104 "1:\n\t"
105 ".section .fixup,\"ax\"\n\t"
H. Peter Anvin08970fc2008-08-25 22:39:15 -0700106 "3: mov %[fault],%[err] ; jmp 1b\n\t"
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200107 ".previous\n\t"
Joe Perchesabb0ade2008-03-23 01:02:51 -0700108 _ASM_EXTABLE(2b, 3b)
H. Peter Anvin08970fc2008-08-25 22:39:15 -0700109 : [err] "=a" (err)
Glauber de Oliveira Costac9dcda52008-01-30 13:31:07 +0100110 : "c" (msr), "0" (low), "d" (high),
H. Peter Anvin0cc02132009-08-31 14:23:29 -0700111 [fault] "i" (-EIO)
Jeremy Fitzhardingeaf2b1c62008-06-25 00:18:59 -0400112 : "memory");
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200113 return err;
114}
115
Ingo Molnarcdc79572008-01-30 13:32:39 +0100116extern unsigned long long native_read_tsc(void);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200117
H. Peter Anvin8b956bf2009-08-31 14:13:48 -0700118extern int native_rdmsr_safe_regs(u32 regs[8]);
119extern int native_wrmsr_safe_regs(u32 regs[8]);
Borislav Petkov132ec922009-08-31 09:50:09 +0200120
Ingo Molnar92767af2008-01-30 13:32:40 +0100121static __always_inline unsigned long long __native_read_tsc(void)
122{
123 DECLARE_ARGS(val, low, high);
124
Ingo Molnar92767af2008-01-30 13:32:40 +0100125 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
Ingo Molnar92767af2008-01-30 13:32:40 +0100126
127 return EAX_EDX_VAL(val, low, high);
128}
129
Glauber de Oliveira Costab8d1fae2008-01-30 13:31:07 +0100130static inline unsigned long long native_read_pmc(int counter)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200131{
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +0100132 DECLARE_ARGS(val, low, high);
133
134 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
135 return EAX_EDX_VAL(val, low, high);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200136}
137
138#ifdef CONFIG_PARAVIRT
139#include <asm/paravirt.h>
Thomas Gleixner96a388d2007-10-11 11:20:03 +0200140#else
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200141#include <linux/errno.h>
142/*
143 * Access to machine-specific registers (available on 586 and better only)
144 * Note: the rd* operations modify the parameters directly (without using
145 * pointer indirection), this allows gcc to optimize better
146 */
147
Joe Perchesabb0ade2008-03-23 01:02:51 -0700148#define rdmsr(msr, val1, val2) \
149do { \
150 u64 __val = native_read_msr((msr)); \
Andi Kleen5f755292010-07-20 15:19:48 -0700151 (void)((val1) = (u32)__val); \
152 (void)((val2) = (u32)(__val >> 32)); \
Joe Perchesabb0ade2008-03-23 01:02:51 -0700153} while (0)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200154
Glauber de Oliveira Costac9dcda52008-01-30 13:31:07 +0100155static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200156{
Glauber de Oliveira Costac9dcda52008-01-30 13:31:07 +0100157 native_write_msr(msr, low, high);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200158}
159
Joe Perchesabb0ade2008-03-23 01:02:51 -0700160#define rdmsrl(msr, val) \
161 ((val) = native_read_msr((msr)))
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200162
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +0100163#define wrmsrl(msr, val) \
Joe Perchesabb0ade2008-03-23 01:02:51 -0700164 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200165
166/* wrmsr with exception handling */
Glauber de Oliveira Costac9dcda52008-01-30 13:31:07 +0100167static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200168{
Glauber de Oliveira Costac9dcda52008-01-30 13:31:07 +0100169 return native_write_msr_safe(msr, low, high);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200170}
171
172/* rdmsr with exception handling */
Joe Perchesabb0ade2008-03-23 01:02:51 -0700173#define rdmsr_safe(msr, p1, p2) \
174({ \
175 int __err; \
176 u64 __val = native_read_msr_safe((msr), &__err); \
177 (*p1) = (u32)__val; \
178 (*p2) = (u32)(__val >> 32); \
179 __err; \
180})
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200181
Andi Kleen1de87bd2008-03-22 10:59:28 +0100182static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
183{
184 int err;
185
186 *p = native_read_msr_safe(msr, &err);
187 return err;
188}
Borislav Petkov177fed12009-08-31 09:50:10 +0200189
Yinghai Lub05f78f2008-08-22 01:32:50 -0700190static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
191{
Borislav Petkov177fed12009-08-31 09:50:10 +0200192 u32 gprs[8] = { 0 };
Yinghai Lub05f78f2008-08-22 01:32:50 -0700193 int err;
194
Borislav Petkov177fed12009-08-31 09:50:10 +0200195 gprs[1] = msr;
196 gprs[7] = 0x9c5a203a;
197
198 err = native_rdmsr_safe_regs(gprs);
199
200 *p = gprs[0] | ((u64)gprs[2] << 32);
201
Yinghai Lub05f78f2008-08-22 01:32:50 -0700202 return err;
203}
Andi Kleen1de87bd2008-03-22 10:59:28 +0100204
Borislav Petkov177fed12009-08-31 09:50:10 +0200205static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
206{
207 u32 gprs[8] = { 0 };
208
209 gprs[0] = (u32)val;
210 gprs[1] = msr;
211 gprs[2] = val >> 32;
212 gprs[7] = 0x9c5a203a;
213
214 return native_wrmsr_safe_regs(gprs);
215}
216
H. Peter Anvin8b956bf2009-08-31 14:13:48 -0700217static inline int rdmsr_safe_regs(u32 regs[8])
Borislav Petkov132ec922009-08-31 09:50:09 +0200218{
219 return native_rdmsr_safe_regs(regs);
220}
221
H. Peter Anvin8b956bf2009-08-31 14:13:48 -0700222static inline int wrmsr_safe_regs(u32 regs[8])
Borislav Petkov132ec922009-08-31 09:50:09 +0200223{
224 return native_wrmsr_safe_regs(regs);
225}
226
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200227#define rdtscl(low) \
Ken Chen205516c2008-12-16 00:32:21 -0800228 ((low) = (u32)__native_read_tsc())
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200229
230#define rdtscll(val) \
Ken Chen205516c2008-12-16 00:32:21 -0800231 ((val) = __native_read_tsc())
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200232
Joe Perchesabb0ade2008-03-23 01:02:51 -0700233#define rdpmc(counter, low, high) \
234do { \
235 u64 _l = native_read_pmc((counter)); \
236 (low) = (u32)_l; \
237 (high) = (u32)(_l >> 32); \
238} while (0)
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +0100239
Joe Perchesabb0ade2008-03-23 01:02:51 -0700240#define rdtscp(low, high, aux) \
241do { \
242 unsigned long long _val = native_read_tscp(&(aux)); \
243 (low) = (u32)_val; \
244 (high) = (u32)(_val >> 32); \
245} while (0)
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +0100246
247#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
248
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200249#endif /* !CONFIG_PARAVIRT */
250
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200251
Joe Perchesabb0ade2008-03-23 01:02:51 -0700252#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \
253 (u32)((val) >> 32))
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200254
Sheng Yang5df97402009-12-16 13:48:04 +0800255#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200256
Sheng Yang5df97402009-12-16 13:48:04 +0800257#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200258
Borislav Petkov50542252009-12-11 18:14:40 +0100259struct msr *msrs_alloc(void);
260void msrs_free(struct msr *msrs);
261
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200262#ifdef CONFIG_SMP
H. Peter Anvinc6f31932008-08-25 17:27:21 -0700263int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
264int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
Borislav Petkovb8a47542009-07-30 11:10:02 +0200265void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
266void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200267int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
268int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
H. Peter Anvin8b956bf2009-08-31 14:13:48 -0700269int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
270int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200271#else /* CONFIG_SMP */
H. Peter Anvinc6f31932008-08-25 17:27:21 -0700272static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200273{
274 rdmsr(msr_no, *l, *h);
H. Peter Anvinc6f31932008-08-25 17:27:21 -0700275 return 0;
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200276}
H. Peter Anvinc6f31932008-08-25 17:27:21 -0700277static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200278{
279 wrmsr(msr_no, l, h);
H. Peter Anvinc6f31932008-08-25 17:27:21 -0700280 return 0;
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200281}
Rusty Russell0d0fbbd2009-11-05 22:45:41 +1030282static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
Borislav Petkovb034c192009-05-22 13:52:19 +0200283 struct msr *msrs)
284{
285 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
286}
Rusty Russell0d0fbbd2009-11-05 22:45:41 +1030287static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
Borislav Petkovb034c192009-05-22 13:52:19 +0200288 struct msr *msrs)
289{
290 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
291}
Joe Perchesabb0ade2008-03-23 01:02:51 -0700292static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
293 u32 *l, u32 *h)
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200294{
295 return rdmsr_safe(msr_no, l, h);
296}
297static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
298{
299 return wrmsr_safe(msr_no, l, h);
300}
H. Peter Anvin8b956bf2009-08-31 14:13:48 -0700301static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
302{
303 return rdmsr_safe_regs(regs);
304}
305static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
306{
307 return wrmsr_safe_regs(regs);
308}
Thomas Gleixnerbe7baf82007-10-23 22:37:24 +0200309#endif /* CONFIG_SMP */
Glauber de Oliveira Costac210d242008-01-30 13:31:07 +0100310#endif /* __KERNEL__ */
H. Peter Anvinff55df52009-08-31 14:16:57 -0700311#endif /* __ASSEMBLY__ */
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700312#endif /* _ASM_X86_MSR_H */