David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 6 | * Copyright (C) 2004-2011 Cavium Networks |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 7 | * Copyright (C) 2008 Wind River Systems |
| 8 | */ |
| 9 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 10 | #include <linux/delay.h> |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 11 | #include <linux/init.h> |
| 12 | #include <linux/irq.h> |
David Daney | d957705 | 2010-01-07 11:54:21 -0800 | [diff] [blame] | 13 | #include <linux/i2c.h> |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 14 | #include <linux/usb.h> |
David Daney | f129907 | 2010-10-01 13:27:27 -0700 | [diff] [blame] | 15 | #include <linux/dma-mapping.h> |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 16 | #include <linux/module.h> |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 17 | #include <linux/mutex.h> |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 18 | #include <linux/slab.h> |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 19 | #include <linux/platform_device.h> |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 20 | #include <linux/of_platform.h> |
| 21 | #include <linux/of_fdt.h> |
| 22 | #include <linux/libfdt.h> |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 23 | #include <linux/usb/ehci_pdriver.h> |
| 24 | #include <linux/usb/ohci_pdriver.h> |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 25 | |
| 26 | #include <asm/octeon/octeon.h> |
| 27 | #include <asm/octeon/cvmx-rnm-defs.h> |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 28 | #include <asm/octeon/cvmx-helper.h> |
| 29 | #include <asm/octeon/cvmx-helper-board.h> |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 30 | #include <asm/octeon/cvmx-uctlx-defs.h> |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 31 | |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 32 | /* Octeon Random Number Generator. */ |
| 33 | static int __init octeon_rng_device_init(void) |
| 34 | { |
| 35 | struct platform_device *pd; |
| 36 | int ret = 0; |
| 37 | |
| 38 | struct resource rng_resources[] = { |
| 39 | { |
| 40 | .flags = IORESOURCE_MEM, |
| 41 | .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), |
| 42 | .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf |
| 43 | }, { |
| 44 | .flags = IORESOURCE_MEM, |
| 45 | .start = cvmx_build_io_address(8, 0), |
| 46 | .end = cvmx_build_io_address(8, 0) + 0x7 |
| 47 | } |
| 48 | }; |
| 49 | |
| 50 | pd = platform_device_alloc("octeon_rng", -1); |
| 51 | if (!pd) { |
| 52 | ret = -ENOMEM; |
| 53 | goto out; |
| 54 | } |
| 55 | |
| 56 | ret = platform_device_add_resources(pd, rng_resources, |
| 57 | ARRAY_SIZE(rng_resources)); |
| 58 | if (ret) |
| 59 | goto fail; |
| 60 | |
| 61 | ret = platform_device_add(pd); |
| 62 | if (ret) |
| 63 | goto fail; |
| 64 | |
| 65 | return ret; |
| 66 | fail: |
| 67 | platform_device_put(pd); |
| 68 | |
| 69 | out: |
| 70 | return ret; |
| 71 | } |
| 72 | device_initcall(octeon_rng_device_init); |
| 73 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 74 | #ifdef CONFIG_USB |
| 75 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 76 | static DEFINE_MUTEX(octeon2_usb_clocks_mutex); |
| 77 | |
| 78 | static int octeon2_usb_clock_start_cnt; |
| 79 | |
| 80 | static void octeon2_usb_clocks_start(void) |
| 81 | { |
| 82 | u64 div; |
| 83 | union cvmx_uctlx_if_ena if_ena; |
| 84 | union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; |
| 85 | union cvmx_uctlx_uphy_ctl_status uphy_ctl_status; |
| 86 | union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status; |
| 87 | int i; |
| 88 | unsigned long io_clk_64_to_ns; |
| 89 | |
| 90 | |
| 91 | mutex_lock(&octeon2_usb_clocks_mutex); |
| 92 | |
| 93 | octeon2_usb_clock_start_cnt++; |
| 94 | if (octeon2_usb_clock_start_cnt != 1) |
| 95 | goto exit; |
| 96 | |
| 97 | io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate(); |
| 98 | |
| 99 | /* |
| 100 | * Step 1: Wait for voltages stable. That surely happened |
| 101 | * before starting the kernel. |
| 102 | * |
| 103 | * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1 |
| 104 | */ |
| 105 | if_ena.u64 = 0; |
| 106 | if_ena.s.en = 1; |
| 107 | cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); |
| 108 | |
| 109 | /* Step 3: Configure the reference clock, PHY, and HCLK */ |
| 110 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
| 111 | |
| 112 | /* |
| 113 | * If the UCTL looks like it has already been started, skip |
| 114 | * the initialization, otherwise bus errors are obtained. |
| 115 | */ |
| 116 | if (clk_rst_ctl.s.hrst) |
| 117 | goto end_clock; |
| 118 | /* 3a */ |
| 119 | clk_rst_ctl.s.p_por = 1; |
| 120 | clk_rst_ctl.s.hrst = 0; |
| 121 | clk_rst_ctl.s.p_prst = 0; |
| 122 | clk_rst_ctl.s.h_clkdiv_rst = 0; |
| 123 | clk_rst_ctl.s.o_clkdiv_rst = 0; |
| 124 | clk_rst_ctl.s.h_clkdiv_en = 0; |
| 125 | clk_rst_ctl.s.o_clkdiv_en = 0; |
| 126 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 127 | |
| 128 | /* 3b */ |
| 129 | /* 12MHz crystal. */ |
| 130 | clk_rst_ctl.s.p_refclk_sel = 0; |
| 131 | clk_rst_ctl.s.p_refclk_div = 0; |
| 132 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 133 | |
| 134 | /* 3c */ |
| 135 | div = octeon_get_io_clock_rate() / 130000000ull; |
| 136 | |
| 137 | switch (div) { |
| 138 | case 0: |
| 139 | div = 1; |
| 140 | break; |
| 141 | case 1: |
| 142 | case 2: |
| 143 | case 3: |
| 144 | case 4: |
| 145 | break; |
| 146 | case 5: |
| 147 | div = 4; |
| 148 | break; |
| 149 | case 6: |
| 150 | case 7: |
| 151 | div = 6; |
| 152 | break; |
| 153 | case 8: |
| 154 | case 9: |
| 155 | case 10: |
| 156 | case 11: |
| 157 | div = 8; |
| 158 | break; |
| 159 | default: |
| 160 | div = 12; |
| 161 | break; |
| 162 | } |
| 163 | clk_rst_ctl.s.h_div = div; |
| 164 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 165 | /* Read it back, */ |
| 166 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
| 167 | clk_rst_ctl.s.h_clkdiv_en = 1; |
| 168 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 169 | /* 3d */ |
| 170 | clk_rst_ctl.s.h_clkdiv_rst = 1; |
| 171 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 172 | |
| 173 | /* 3e: delay 64 io clocks */ |
| 174 | ndelay(io_clk_64_to_ns); |
| 175 | |
| 176 | /* |
| 177 | * Step 4: Program the power-on reset field in the UCTL |
| 178 | * clock-reset-control register. |
| 179 | */ |
| 180 | clk_rst_ctl.s.p_por = 0; |
| 181 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 182 | |
| 183 | /* Step 5: Wait 1 ms for the PHY clock to start. */ |
| 184 | mdelay(1); |
| 185 | |
| 186 | /* |
| 187 | * Step 6: Program the reset input from automatic test |
| 188 | * equipment field in the UPHY CSR |
| 189 | */ |
| 190 | uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0)); |
| 191 | uphy_ctl_status.s.ate_reset = 1; |
| 192 | cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); |
| 193 | |
| 194 | /* Step 7: Wait for at least 10ns. */ |
| 195 | ndelay(10); |
| 196 | |
| 197 | /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */ |
| 198 | uphy_ctl_status.s.ate_reset = 0; |
| 199 | cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); |
| 200 | |
| 201 | /* |
| 202 | * Step 9: Wait for at least 20ns for UPHY to output PHY clock |
| 203 | * signals and OHCI_CLK48 |
| 204 | */ |
| 205 | ndelay(20); |
| 206 | |
| 207 | /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */ |
| 208 | /* 10a */ |
| 209 | clk_rst_ctl.s.o_clkdiv_rst = 1; |
| 210 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 211 | |
| 212 | /* 10b */ |
| 213 | clk_rst_ctl.s.o_clkdiv_en = 1; |
| 214 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 215 | |
| 216 | /* 10c */ |
| 217 | ndelay(io_clk_64_to_ns); |
| 218 | |
| 219 | /* |
| 220 | * Step 11: Program the PHY reset field: |
| 221 | * UCTL0_CLK_RST_CTL[P_PRST] = 1 |
| 222 | */ |
| 223 | clk_rst_ctl.s.p_prst = 1; |
| 224 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 225 | |
| 226 | /* Step 12: Wait 1 uS. */ |
| 227 | udelay(1); |
| 228 | |
| 229 | /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */ |
| 230 | clk_rst_ctl.s.hrst = 1; |
| 231 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
| 232 | |
| 233 | end_clock: |
| 234 | /* Now we can set some other registers. */ |
| 235 | |
| 236 | for (i = 0; i <= 1; i++) { |
| 237 | port_ctl_status.u64 = |
| 238 | cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); |
| 239 | /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */ |
| 240 | port_ctl_status.s.txvreftune = 15; |
| 241 | port_ctl_status.s.txrisetune = 1; |
| 242 | port_ctl_status.s.txpreemphasistune = 1; |
| 243 | cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), |
| 244 | port_ctl_status.u64); |
| 245 | } |
| 246 | |
| 247 | /* Set uSOF cycle period to 60,000 bits. */ |
| 248 | cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); |
| 249 | exit: |
| 250 | mutex_unlock(&octeon2_usb_clocks_mutex); |
| 251 | } |
| 252 | |
| 253 | static void octeon2_usb_clocks_stop(void) |
| 254 | { |
| 255 | mutex_lock(&octeon2_usb_clocks_mutex); |
| 256 | octeon2_usb_clock_start_cnt--; |
| 257 | mutex_unlock(&octeon2_usb_clocks_mutex); |
| 258 | } |
| 259 | |
| 260 | static int octeon_ehci_power_on(struct platform_device *pdev) |
| 261 | { |
| 262 | octeon2_usb_clocks_start(); |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static void octeon_ehci_power_off(struct platform_device *pdev) |
| 267 | { |
| 268 | octeon2_usb_clocks_stop(); |
| 269 | } |
| 270 | |
| 271 | static struct usb_ehci_pdata octeon_ehci_pdata = { |
| 272 | /* Octeon EHCI matches CPU endianness. */ |
| 273 | #ifdef __BIG_ENDIAN |
| 274 | .big_endian_mmio = 1, |
| 275 | #endif |
| 276 | .power_on = octeon_ehci_power_on, |
| 277 | .power_off = octeon_ehci_power_off, |
| 278 | }; |
| 279 | |
| 280 | static void __init octeon_ehci_hw_start(void) |
| 281 | { |
| 282 | union cvmx_uctlx_ehci_ctl ehci_ctl; |
| 283 | |
| 284 | octeon2_usb_clocks_start(); |
| 285 | |
| 286 | ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); |
| 287 | /* Use 64-bit addressing. */ |
| 288 | ehci_ctl.s.ehci_64b_addr_en = 1; |
| 289 | ehci_ctl.s.l2c_addr_msb = 0; |
| 290 | ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ |
| 291 | ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ |
| 292 | cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); |
| 293 | |
| 294 | octeon2_usb_clocks_stop(); |
| 295 | } |
| 296 | |
| 297 | static u64 octeon_ehci_dma_mask = DMA_BIT_MASK(64); |
| 298 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 299 | static int __init octeon_ehci_device_init(void) |
| 300 | { |
| 301 | struct platform_device *pd; |
| 302 | int ret = 0; |
| 303 | |
| 304 | struct resource usb_resources[] = { |
| 305 | { |
| 306 | .flags = IORESOURCE_MEM, |
| 307 | }, { |
| 308 | .flags = IORESOURCE_IRQ, |
| 309 | } |
| 310 | }; |
| 311 | |
| 312 | /* Only Octeon2 has ehci/ohci */ |
| 313 | if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) |
| 314 | return 0; |
| 315 | |
| 316 | if (octeon_is_simulation() || usb_disabled()) |
| 317 | return 0; /* No USB in the simulator. */ |
| 318 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 319 | pd = platform_device_alloc("ehci-platform", 0); |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 320 | if (!pd) { |
| 321 | ret = -ENOMEM; |
| 322 | goto out; |
| 323 | } |
| 324 | |
| 325 | usb_resources[0].start = 0x00016F0000000000ULL; |
| 326 | usb_resources[0].end = usb_resources[0].start + 0x100; |
| 327 | |
| 328 | usb_resources[1].start = OCTEON_IRQ_USB0; |
| 329 | usb_resources[1].end = OCTEON_IRQ_USB0; |
| 330 | |
| 331 | ret = platform_device_add_resources(pd, usb_resources, |
| 332 | ARRAY_SIZE(usb_resources)); |
| 333 | if (ret) |
| 334 | goto fail; |
| 335 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 336 | pd->dev.dma_mask = &octeon_ehci_dma_mask; |
| 337 | pd->dev.platform_data = &octeon_ehci_pdata; |
| 338 | octeon_ehci_hw_start(); |
| 339 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 340 | ret = platform_device_add(pd); |
| 341 | if (ret) |
| 342 | goto fail; |
| 343 | |
| 344 | return ret; |
| 345 | fail: |
| 346 | platform_device_put(pd); |
| 347 | out: |
| 348 | return ret; |
| 349 | } |
| 350 | device_initcall(octeon_ehci_device_init); |
| 351 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 352 | static int octeon_ohci_power_on(struct platform_device *pdev) |
| 353 | { |
| 354 | octeon2_usb_clocks_start(); |
| 355 | return 0; |
| 356 | } |
| 357 | |
| 358 | static void octeon_ohci_power_off(struct platform_device *pdev) |
| 359 | { |
| 360 | octeon2_usb_clocks_stop(); |
| 361 | } |
| 362 | |
| 363 | static struct usb_ohci_pdata octeon_ohci_pdata = { |
| 364 | /* Octeon OHCI matches CPU endianness. */ |
| 365 | #ifdef __BIG_ENDIAN |
| 366 | .big_endian_mmio = 1, |
| 367 | #endif |
| 368 | .power_on = octeon_ohci_power_on, |
| 369 | .power_off = octeon_ohci_power_off, |
| 370 | }; |
| 371 | |
| 372 | static void __init octeon_ohci_hw_start(void) |
| 373 | { |
| 374 | union cvmx_uctlx_ohci_ctl ohci_ctl; |
| 375 | |
| 376 | octeon2_usb_clocks_start(); |
| 377 | |
| 378 | ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); |
| 379 | ohci_ctl.s.l2c_addr_msb = 0; |
| 380 | ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ |
| 381 | ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ |
| 382 | cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); |
| 383 | |
| 384 | octeon2_usb_clocks_stop(); |
| 385 | } |
| 386 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 387 | static int __init octeon_ohci_device_init(void) |
| 388 | { |
| 389 | struct platform_device *pd; |
| 390 | int ret = 0; |
| 391 | |
| 392 | struct resource usb_resources[] = { |
| 393 | { |
| 394 | .flags = IORESOURCE_MEM, |
| 395 | }, { |
| 396 | .flags = IORESOURCE_IRQ, |
| 397 | } |
| 398 | }; |
| 399 | |
| 400 | /* Only Octeon2 has ehci/ohci */ |
| 401 | if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) |
| 402 | return 0; |
| 403 | |
| 404 | if (octeon_is_simulation() || usb_disabled()) |
| 405 | return 0; /* No USB in the simulator. */ |
| 406 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 407 | pd = platform_device_alloc("ohci-platform", 0); |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 408 | if (!pd) { |
| 409 | ret = -ENOMEM; |
| 410 | goto out; |
| 411 | } |
| 412 | |
| 413 | usb_resources[0].start = 0x00016F0000000400ULL; |
| 414 | usb_resources[0].end = usb_resources[0].start + 0x100; |
| 415 | |
| 416 | usb_resources[1].start = OCTEON_IRQ_USB0; |
| 417 | usb_resources[1].end = OCTEON_IRQ_USB0; |
| 418 | |
| 419 | ret = platform_device_add_resources(pd, usb_resources, |
| 420 | ARRAY_SIZE(usb_resources)); |
| 421 | if (ret) |
| 422 | goto fail; |
| 423 | |
Alan Stern | 2193dda | 2014-11-25 12:28:46 +0100 | [diff] [blame] | 424 | pd->dev.platform_data = &octeon_ohci_pdata; |
| 425 | octeon_ohci_hw_start(); |
| 426 | |
David Daney | 340fbb8 | 2010-10-08 14:47:53 -0700 | [diff] [blame] | 427 | ret = platform_device_add(pd); |
| 428 | if (ret) |
| 429 | goto fail; |
| 430 | |
| 431 | return ret; |
| 432 | fail: |
| 433 | platform_device_put(pd); |
| 434 | out: |
| 435 | return ret; |
| 436 | } |
| 437 | device_initcall(octeon_ohci_device_init); |
| 438 | |
| 439 | #endif /* CONFIG_USB */ |
| 440 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 441 | static struct of_device_id __initdata octeon_ids[] = { |
| 442 | { .compatible = "simple-bus", }, |
| 443 | { .compatible = "cavium,octeon-6335-uctl", }, |
David Daney | d617f9e | 2013-12-03 11:46:51 -0800 | [diff] [blame] | 444 | { .compatible = "cavium,octeon-5750-usbn", }, |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 445 | { .compatible = "cavium,octeon-3860-bootbus", }, |
| 446 | { .compatible = "cavium,mdio-mux", }, |
| 447 | { .compatible = "gpio-leds", }, |
| 448 | {}, |
| 449 | }; |
| 450 | |
| 451 | static bool __init octeon_has_88e1145(void) |
| 452 | { |
| 453 | return !OCTEON_IS_MODEL(OCTEON_CN52XX) && |
| 454 | !OCTEON_IS_MODEL(OCTEON_CN6XXX) && |
| 455 | !OCTEON_IS_MODEL(OCTEON_CN56XX); |
| 456 | } |
| 457 | |
| 458 | static void __init octeon_fdt_set_phy(int eth, int phy_addr) |
| 459 | { |
| 460 | const __be32 *phy_handle; |
| 461 | const __be32 *alt_phy_handle; |
| 462 | const __be32 *reg; |
| 463 | u32 phandle; |
| 464 | int phy; |
| 465 | int alt_phy; |
| 466 | const char *p; |
| 467 | int current_len; |
| 468 | char new_name[20]; |
| 469 | |
| 470 | phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); |
| 471 | if (!phy_handle) |
| 472 | return; |
| 473 | |
| 474 | phandle = be32_to_cpup(phy_handle); |
| 475 | phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); |
| 476 | |
| 477 | alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); |
| 478 | if (alt_phy_handle) { |
| 479 | u32 alt_phandle = be32_to_cpup(alt_phy_handle); |
| 480 | alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); |
| 481 | } else { |
| 482 | alt_phy = -1; |
| 483 | } |
| 484 | |
| 485 | if (phy_addr < 0 || phy < 0) { |
| 486 | /* Delete the PHY things */ |
| 487 | fdt_nop_property(initial_boot_params, eth, "phy-handle"); |
| 488 | /* This one may fail */ |
| 489 | fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); |
| 490 | if (phy >= 0) |
| 491 | fdt_nop_node(initial_boot_params, phy); |
| 492 | if (alt_phy >= 0) |
| 493 | fdt_nop_node(initial_boot_params, alt_phy); |
| 494 | return; |
| 495 | } |
| 496 | |
| 497 | if (phy_addr >= 256 && alt_phy > 0) { |
| 498 | const struct fdt_property *phy_prop; |
| 499 | struct fdt_property *alt_prop; |
| 500 | u32 phy_handle_name; |
| 501 | |
| 502 | /* Use the alt phy node instead.*/ |
| 503 | phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); |
| 504 | phy_handle_name = phy_prop->nameoff; |
| 505 | fdt_nop_node(initial_boot_params, phy); |
| 506 | fdt_nop_property(initial_boot_params, eth, "phy-handle"); |
| 507 | alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); |
| 508 | alt_prop->nameoff = phy_handle_name; |
| 509 | phy = alt_phy; |
| 510 | } |
| 511 | |
| 512 | phy_addr &= 0xff; |
| 513 | |
| 514 | if (octeon_has_88e1145()) { |
| 515 | fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); |
| 516 | memset(new_name, 0, sizeof(new_name)); |
| 517 | strcpy(new_name, "marvell,88e1145"); |
| 518 | p = fdt_getprop(initial_boot_params, phy, "compatible", |
| 519 | ¤t_len); |
| 520 | if (p && current_len >= strlen(new_name)) |
| 521 | fdt_setprop_inplace(initial_boot_params, phy, |
| 522 | "compatible", new_name, current_len); |
| 523 | } |
| 524 | |
| 525 | reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); |
| 526 | if (phy_addr == be32_to_cpup(reg)) |
| 527 | return; |
| 528 | |
| 529 | fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); |
| 530 | |
| 531 | snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); |
| 532 | |
| 533 | p = fdt_get_name(initial_boot_params, phy, ¤t_len); |
| 534 | if (p && current_len == strlen(new_name)) |
| 535 | fdt_set_name(initial_boot_params, phy, new_name); |
| 536 | else |
| 537 | pr_err("Error: could not rename ethernet phy: <%s>", p); |
| 538 | } |
| 539 | |
| 540 | static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) |
| 541 | { |
| 542 | u8 new_mac[6]; |
| 543 | u64 mac = *pmac; |
| 544 | int r; |
| 545 | |
| 546 | new_mac[0] = (mac >> 40) & 0xff; |
| 547 | new_mac[1] = (mac >> 32) & 0xff; |
| 548 | new_mac[2] = (mac >> 24) & 0xff; |
| 549 | new_mac[3] = (mac >> 16) & 0xff; |
| 550 | new_mac[4] = (mac >> 8) & 0xff; |
| 551 | new_mac[5] = mac & 0xff; |
| 552 | |
| 553 | r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", |
| 554 | new_mac, sizeof(new_mac)); |
| 555 | |
| 556 | if (r) { |
| 557 | pr_err("Setting \"local-mac-address\" failed %d", r); |
| 558 | return; |
| 559 | } |
| 560 | *pmac = mac + 1; |
| 561 | } |
| 562 | |
| 563 | static void __init octeon_fdt_rm_ethernet(int node) |
| 564 | { |
| 565 | const __be32 *phy_handle; |
| 566 | |
| 567 | phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); |
| 568 | if (phy_handle) { |
| 569 | u32 ph = be32_to_cpup(phy_handle); |
| 570 | int p = fdt_node_offset_by_phandle(initial_boot_params, ph); |
| 571 | if (p >= 0) |
| 572 | fdt_nop_node(initial_boot_params, p); |
| 573 | } |
| 574 | fdt_nop_node(initial_boot_params, node); |
| 575 | } |
| 576 | |
| 577 | static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac) |
| 578 | { |
| 579 | char name_buffer[20]; |
| 580 | int eth; |
| 581 | int phy_addr; |
| 582 | int ipd_port; |
| 583 | |
| 584 | snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); |
| 585 | eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); |
| 586 | if (eth < 0) |
| 587 | return; |
| 588 | if (p > max) { |
| 589 | pr_debug("Deleting port %x:%x\n", i, p); |
| 590 | octeon_fdt_rm_ethernet(eth); |
| 591 | return; |
| 592 | } |
| 593 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
| 594 | ipd_port = (0x100 * i) + (0x10 * p) + 0x800; |
| 595 | else |
| 596 | ipd_port = 16 * i + p; |
| 597 | |
| 598 | phy_addr = cvmx_helper_board_get_mii_address(ipd_port); |
| 599 | octeon_fdt_set_phy(eth, phy_addr); |
| 600 | octeon_fdt_set_mac_addr(eth, pmac); |
| 601 | } |
| 602 | |
| 603 | static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) |
| 604 | { |
| 605 | char name_buffer[20]; |
| 606 | int iface; |
| 607 | int p; |
Faidon Liambotis | ab2bb14 | 2013-07-11 21:08:09 +0000 | [diff] [blame] | 608 | int count = 0; |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 609 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 610 | snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); |
| 611 | iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); |
| 612 | if (iface < 0) |
| 613 | return; |
| 614 | |
Aaro Koskinen | b2e4f15 | 2013-11-01 17:06:04 +0200 | [diff] [blame] | 615 | if (cvmx_helper_interface_enumerate(idx) == 0) |
| 616 | count = cvmx_helper_ports_on_interface(idx); |
| 617 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 618 | for (p = 0; p < 16; p++) |
| 619 | octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); |
| 620 | } |
| 621 | |
| 622 | int __init octeon_prune_device_tree(void) |
| 623 | { |
| 624 | int i, max_port, uart_mask; |
| 625 | const char *pip_path; |
| 626 | const char *alias_prop; |
| 627 | char name_buffer[20]; |
| 628 | int aliases; |
| 629 | u64 mac_addr_base; |
| 630 | |
| 631 | if (fdt_check_header(initial_boot_params)) |
| 632 | panic("Corrupt Device Tree."); |
| 633 | |
| 634 | aliases = fdt_path_offset(initial_boot_params, "/aliases"); |
| 635 | if (aliases < 0) { |
| 636 | pr_err("Error: No /aliases node in device tree."); |
| 637 | return -EINVAL; |
| 638 | } |
| 639 | |
| 640 | |
| 641 | mac_addr_base = |
| 642 | ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | |
| 643 | ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | |
| 644 | ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | |
| 645 | ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | |
| 646 | ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | |
| 647 | (octeon_bootinfo->mac_addr_base[5] & 0xffull); |
| 648 | |
| 649 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) |
| 650 | max_port = 2; |
| 651 | else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) |
| 652 | max_port = 1; |
| 653 | else |
| 654 | max_port = 0; |
| 655 | |
| 656 | if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) |
| 657 | max_port = 0; |
| 658 | |
| 659 | for (i = 0; i < 2; i++) { |
| 660 | int mgmt; |
| 661 | snprintf(name_buffer, sizeof(name_buffer), |
| 662 | "mix%d", i); |
| 663 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 664 | name_buffer, NULL); |
| 665 | if (alias_prop) { |
| 666 | mgmt = fdt_path_offset(initial_boot_params, alias_prop); |
| 667 | if (mgmt < 0) |
| 668 | continue; |
| 669 | if (i >= max_port) { |
| 670 | pr_debug("Deleting mix%d\n", i); |
| 671 | octeon_fdt_rm_ethernet(mgmt); |
| 672 | fdt_nop_property(initial_boot_params, aliases, |
| 673 | name_buffer); |
| 674 | } else { |
| 675 | int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); |
| 676 | octeon_fdt_set_phy(mgmt, phy_addr); |
| 677 | octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); |
| 678 | } |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); |
| 683 | if (pip_path) { |
| 684 | int pip = fdt_path_offset(initial_boot_params, pip_path); |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 685 | if (pip >= 0) |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 686 | for (i = 0; i <= 4; i++) |
| 687 | octeon_fdt_pip_iface(pip, i, &mac_addr_base); |
| 688 | } |
| 689 | |
| 690 | /* I2C */ |
| 691 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || |
| 692 | OCTEON_IS_MODEL(OCTEON_CN63XX) || |
| 693 | OCTEON_IS_MODEL(OCTEON_CN68XX) || |
| 694 | OCTEON_IS_MODEL(OCTEON_CN56XX)) |
| 695 | max_port = 2; |
| 696 | else |
| 697 | max_port = 1; |
| 698 | |
| 699 | for (i = 0; i < 2; i++) { |
| 700 | int i2c; |
| 701 | snprintf(name_buffer, sizeof(name_buffer), |
| 702 | "twsi%d", i); |
| 703 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 704 | name_buffer, NULL); |
| 705 | |
| 706 | if (alias_prop) { |
| 707 | i2c = fdt_path_offset(initial_boot_params, alias_prop); |
| 708 | if (i2c < 0) |
| 709 | continue; |
| 710 | if (i >= max_port) { |
| 711 | pr_debug("Deleting twsi%d\n", i); |
| 712 | fdt_nop_node(initial_boot_params, i2c); |
| 713 | fdt_nop_property(initial_boot_params, aliases, |
| 714 | name_buffer); |
| 715 | } |
| 716 | } |
| 717 | } |
| 718 | |
| 719 | /* SMI/MDIO */ |
| 720 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
| 721 | max_port = 4; |
| 722 | else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || |
| 723 | OCTEON_IS_MODEL(OCTEON_CN63XX) || |
| 724 | OCTEON_IS_MODEL(OCTEON_CN56XX)) |
| 725 | max_port = 2; |
| 726 | else |
| 727 | max_port = 1; |
| 728 | |
| 729 | for (i = 0; i < 2; i++) { |
| 730 | int i2c; |
| 731 | snprintf(name_buffer, sizeof(name_buffer), |
| 732 | "smi%d", i); |
| 733 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 734 | name_buffer, NULL); |
| 735 | |
| 736 | if (alias_prop) { |
| 737 | i2c = fdt_path_offset(initial_boot_params, alias_prop); |
| 738 | if (i2c < 0) |
| 739 | continue; |
| 740 | if (i >= max_port) { |
| 741 | pr_debug("Deleting smi%d\n", i); |
| 742 | fdt_nop_node(initial_boot_params, i2c); |
| 743 | fdt_nop_property(initial_boot_params, aliases, |
| 744 | name_buffer); |
| 745 | } |
| 746 | } |
| 747 | } |
| 748 | |
| 749 | /* Serial */ |
| 750 | uart_mask = 3; |
| 751 | |
| 752 | /* Right now CN52XX is the only chip with a third uart */ |
| 753 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) |
| 754 | uart_mask |= 4; /* uart2 */ |
| 755 | |
| 756 | for (i = 0; i < 3; i++) { |
| 757 | int uart; |
| 758 | snprintf(name_buffer, sizeof(name_buffer), |
| 759 | "uart%d", i); |
| 760 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 761 | name_buffer, NULL); |
| 762 | |
| 763 | if (alias_prop) { |
| 764 | uart = fdt_path_offset(initial_boot_params, alias_prop); |
David Daney | 5219343 | 2013-06-19 20:37:26 +0000 | [diff] [blame] | 765 | if (uart_mask & (1 << i)) { |
| 766 | __be32 f; |
| 767 | |
| 768 | f = cpu_to_be32(octeon_get_io_clock_rate()); |
| 769 | fdt_setprop_inplace(initial_boot_params, |
| 770 | uart, "clock-frequency", |
| 771 | &f, sizeof(f)); |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 772 | continue; |
David Daney | 5219343 | 2013-06-19 20:37:26 +0000 | [diff] [blame] | 773 | } |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 774 | pr_debug("Deleting uart%d\n", i); |
| 775 | fdt_nop_node(initial_boot_params, uart); |
| 776 | fdt_nop_property(initial_boot_params, aliases, |
| 777 | name_buffer); |
| 778 | } |
| 779 | } |
| 780 | |
| 781 | /* Compact Flash */ |
| 782 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 783 | "cf0", NULL); |
| 784 | if (alias_prop) { |
| 785 | union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; |
| 786 | unsigned long base_ptr, region_base, region_size; |
| 787 | unsigned long region1_base = 0; |
| 788 | unsigned long region1_size = 0; |
| 789 | int cs, bootbus; |
| 790 | bool is_16bit = false; |
| 791 | bool is_true_ide = false; |
| 792 | __be32 new_reg[6]; |
| 793 | __be32 *ranges; |
| 794 | int len; |
| 795 | |
| 796 | int cf = fdt_path_offset(initial_boot_params, alias_prop); |
| 797 | base_ptr = 0; |
| 798 | if (octeon_bootinfo->major_version == 1 |
| 799 | && octeon_bootinfo->minor_version >= 1) { |
| 800 | if (octeon_bootinfo->compact_flash_common_base_addr) |
| 801 | base_ptr = octeon_bootinfo->compact_flash_common_base_addr; |
| 802 | } else { |
| 803 | base_ptr = 0x1d000800; |
| 804 | } |
| 805 | |
| 806 | if (!base_ptr) |
| 807 | goto no_cf; |
| 808 | |
| 809 | /* Find CS0 region. */ |
| 810 | for (cs = 0; cs < 8; cs++) { |
| 811 | mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
| 812 | region_base = mio_boot_reg_cfg.s.base << 16; |
| 813 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
| 814 | if (mio_boot_reg_cfg.s.en && base_ptr >= region_base |
| 815 | && base_ptr < region_base + region_size) { |
| 816 | is_16bit = mio_boot_reg_cfg.s.width; |
| 817 | break; |
| 818 | } |
| 819 | } |
| 820 | if (cs >= 7) { |
| 821 | /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ |
| 822 | goto no_cf; |
| 823 | } |
| 824 | |
| 825 | if (!(base_ptr & 0xfffful)) { |
| 826 | /* |
| 827 | * Boot loader signals availability of DMA (true_ide |
| 828 | * mode) by setting low order bits of base_ptr to |
| 829 | * zero. |
| 830 | */ |
| 831 | |
| 832 | /* Asume that CS1 immediately follows. */ |
| 833 | mio_boot_reg_cfg.u64 = |
| 834 | cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); |
| 835 | region1_base = mio_boot_reg_cfg.s.base << 16; |
| 836 | region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
| 837 | if (!mio_boot_reg_cfg.s.en) |
| 838 | goto no_cf; |
| 839 | is_true_ide = true; |
| 840 | |
| 841 | } else { |
| 842 | fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); |
| 843 | fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); |
| 844 | if (!is_16bit) { |
| 845 | __be32 width = cpu_to_be32(8); |
| 846 | fdt_setprop_inplace(initial_boot_params, cf, |
| 847 | "cavium,bus-width", &width, sizeof(width)); |
| 848 | } |
| 849 | } |
| 850 | new_reg[0] = cpu_to_be32(cs); |
| 851 | new_reg[1] = cpu_to_be32(0); |
| 852 | new_reg[2] = cpu_to_be32(0x10000); |
| 853 | new_reg[3] = cpu_to_be32(cs + 1); |
| 854 | new_reg[4] = cpu_to_be32(0); |
| 855 | new_reg[5] = cpu_to_be32(0x10000); |
| 856 | fdt_setprop_inplace(initial_boot_params, cf, |
| 857 | "reg", new_reg, sizeof(new_reg)); |
| 858 | |
| 859 | bootbus = fdt_parent_offset(initial_boot_params, cf); |
| 860 | if (bootbus < 0) |
| 861 | goto no_cf; |
| 862 | ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); |
| 863 | if (!ranges || len < (5 * 8 * sizeof(__be32))) |
| 864 | goto no_cf; |
| 865 | |
| 866 | ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); |
| 867 | ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); |
| 868 | ranges[(cs * 5) + 4] = cpu_to_be32(region_size); |
| 869 | if (is_true_ide) { |
| 870 | cs++; |
| 871 | ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); |
| 872 | ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); |
| 873 | ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); |
| 874 | } |
| 875 | goto end_cf; |
| 876 | no_cf: |
| 877 | fdt_nop_node(initial_boot_params, cf); |
| 878 | |
| 879 | end_cf: |
| 880 | ; |
| 881 | } |
| 882 | |
| 883 | /* 8 char LED */ |
| 884 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 885 | "led0", NULL); |
| 886 | if (alias_prop) { |
| 887 | union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; |
| 888 | unsigned long base_ptr, region_base, region_size; |
| 889 | int cs, bootbus; |
| 890 | __be32 new_reg[6]; |
| 891 | __be32 *ranges; |
| 892 | int len; |
| 893 | int led = fdt_path_offset(initial_boot_params, alias_prop); |
| 894 | |
| 895 | base_ptr = octeon_bootinfo->led_display_base_addr; |
| 896 | if (base_ptr == 0) |
| 897 | goto no_led; |
| 898 | /* Find CS0 region. */ |
| 899 | for (cs = 0; cs < 8; cs++) { |
| 900 | mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
| 901 | region_base = mio_boot_reg_cfg.s.base << 16; |
| 902 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
| 903 | if (mio_boot_reg_cfg.s.en && base_ptr >= region_base |
| 904 | && base_ptr < region_base + region_size) |
| 905 | break; |
| 906 | } |
| 907 | |
| 908 | if (cs > 7) |
| 909 | goto no_led; |
| 910 | |
| 911 | new_reg[0] = cpu_to_be32(cs); |
| 912 | new_reg[1] = cpu_to_be32(0x20); |
| 913 | new_reg[2] = cpu_to_be32(0x20); |
| 914 | new_reg[3] = cpu_to_be32(cs); |
| 915 | new_reg[4] = cpu_to_be32(0); |
| 916 | new_reg[5] = cpu_to_be32(0x20); |
| 917 | fdt_setprop_inplace(initial_boot_params, led, |
| 918 | "reg", new_reg, sizeof(new_reg)); |
| 919 | |
| 920 | bootbus = fdt_parent_offset(initial_boot_params, led); |
| 921 | if (bootbus < 0) |
| 922 | goto no_led; |
| 923 | ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); |
| 924 | if (!ranges || len < (5 * 8 * sizeof(__be32))) |
| 925 | goto no_led; |
| 926 | |
| 927 | ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); |
| 928 | ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); |
| 929 | ranges[(cs * 5) + 4] = cpu_to_be32(region_size); |
| 930 | goto end_led; |
| 931 | |
| 932 | no_led: |
| 933 | fdt_nop_node(initial_boot_params, led); |
| 934 | end_led: |
| 935 | ; |
| 936 | } |
| 937 | |
| 938 | /* OHCI/UHCI USB */ |
| 939 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 940 | "uctl", NULL); |
| 941 | if (alias_prop) { |
| 942 | int uctl = fdt_path_offset(initial_boot_params, alias_prop); |
| 943 | |
| 944 | if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || |
| 945 | octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { |
| 946 | pr_debug("Deleting uctl\n"); |
| 947 | fdt_nop_node(initial_boot_params, uctl); |
| 948 | fdt_nop_property(initial_boot_params, aliases, "uctl"); |
| 949 | } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || |
| 950 | octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { |
| 951 | /* Missing "refclk-type" defaults to crystal. */ |
| 952 | fdt_nop_property(initial_boot_params, uctl, "refclk-type"); |
| 953 | } |
| 954 | } |
| 955 | |
David Daney | d617f9e | 2013-12-03 11:46:51 -0800 | [diff] [blame] | 956 | /* DWC2 USB */ |
| 957 | alias_prop = fdt_getprop(initial_boot_params, aliases, |
| 958 | "usbn", NULL); |
| 959 | if (alias_prop) { |
| 960 | int usbn = fdt_path_offset(initial_boot_params, alias_prop); |
| 961 | |
| 962 | if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 || |
| 963 | !octeon_has_feature(OCTEON_FEATURE_USB))) { |
| 964 | pr_debug("Deleting usbn\n"); |
| 965 | fdt_nop_node(initial_boot_params, usbn); |
| 966 | fdt_nop_property(initial_boot_params, aliases, "usbn"); |
| 967 | } else { |
| 968 | __be32 new_f[1]; |
| 969 | enum cvmx_helper_board_usb_clock_types c; |
| 970 | c = __cvmx_helper_board_usb_get_clock_type(); |
| 971 | switch (c) { |
| 972 | case USB_CLOCK_TYPE_REF_48: |
| 973 | new_f[0] = cpu_to_be32(48000000); |
| 974 | fdt_setprop_inplace(initial_boot_params, usbn, |
| 975 | "refclk-frequency", new_f, sizeof(new_f)); |
| 976 | /* Fall through ...*/ |
| 977 | case USB_CLOCK_TYPE_REF_12: |
| 978 | /* Missing "refclk-type" defaults to external. */ |
| 979 | fdt_nop_property(initial_boot_params, usbn, "refclk-type"); |
| 980 | break; |
| 981 | default: |
| 982 | break; |
| 983 | } |
| 984 | } |
| 985 | } |
| 986 | |
David Daney | 7ed1815 | 2012-07-05 18:12:38 +0200 | [diff] [blame] | 987 | return 0; |
| 988 | } |
| 989 | |
| 990 | static int __init octeon_publish_devices(void) |
| 991 | { |
| 992 | return of_platform_bus_probe(NULL, octeon_ids, NULL); |
| 993 | } |
| 994 | device_initcall(octeon_publish_devices); |
| 995 | |
David Daney | 512254b | 2009-09-16 14:54:18 -0700 | [diff] [blame] | 996 | MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); |
| 997 | MODULE_LICENSE("GPL"); |
| 998 | MODULE_DESCRIPTION("Platform driver for Octeon SOC"); |