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Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -08001/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __H_VIDC_HFI_HELPER_H__
15#define __H_VIDC_HFI_HELPER_H__
16
17#define HFI_COMMON_BASE (0)
18#define HFI_OX_BASE (0x01000000)
19
20#define HFI_VIDEO_DOMAIN_ENCODER (HFI_COMMON_BASE + 0x1)
21#define HFI_VIDEO_DOMAIN_DECODER (HFI_COMMON_BASE + 0x2)
22#define HFI_VIDEO_DOMAIN_VPE (HFI_COMMON_BASE + 0x4)
23#define HFI_VIDEO_DOMAIN_MBI (HFI_COMMON_BASE + 0x8)
24
25#define HFI_DOMAIN_BASE_COMMON (HFI_COMMON_BASE + 0)
26#define HFI_DOMAIN_BASE_VDEC (HFI_COMMON_BASE + 0x01000000)
27#define HFI_DOMAIN_BASE_VENC (HFI_COMMON_BASE + 0x02000000)
28#define HFI_DOMAIN_BASE_VPE (HFI_COMMON_BASE + 0x03000000)
29
30#define HFI_VIDEO_ARCH_OX (HFI_COMMON_BASE + 0x1)
31
32#define HFI_ARCH_COMMON_OFFSET (0)
33#define HFI_ARCH_OX_OFFSET (0x00200000)
34
35#define HFI_CMD_START_OFFSET (0x00010000)
36#define HFI_MSG_START_OFFSET (0x00020000)
37
38#define HFI_ERR_NONE HFI_COMMON_BASE
39#define HFI_ERR_SYS_FATAL (HFI_COMMON_BASE + 0x1)
40#define HFI_ERR_SYS_INVALID_PARAMETER (HFI_COMMON_BASE + 0x2)
41#define HFI_ERR_SYS_VERSION_MISMATCH (HFI_COMMON_BASE + 0x3)
42#define HFI_ERR_SYS_INSUFFICIENT_RESOURCES (HFI_COMMON_BASE + 0x4)
43#define HFI_ERR_SYS_MAX_SESSIONS_REACHED (HFI_COMMON_BASE + 0x5)
44#define HFI_ERR_SYS_UNSUPPORTED_CODEC (HFI_COMMON_BASE + 0x6)
45#define HFI_ERR_SYS_SESSION_IN_USE (HFI_COMMON_BASE + 0x7)
46#define HFI_ERR_SYS_SESSION_ID_OUT_OF_RANGE (HFI_COMMON_BASE + 0x8)
47#define HFI_ERR_SYS_UNSUPPORTED_DOMAIN (HFI_COMMON_BASE + 0x9)
48
49#define HFI_ERR_SESSION_FATAL (HFI_COMMON_BASE + 0x1001)
50#define HFI_ERR_SESSION_INVALID_PARAMETER (HFI_COMMON_BASE + 0x1002)
51#define HFI_ERR_SESSION_BAD_POINTER (HFI_COMMON_BASE + 0x1003)
52#define HFI_ERR_SESSION_INVALID_SESSION_ID (HFI_COMMON_BASE + 0x1004)
53#define HFI_ERR_SESSION_INVALID_STREAM_ID (HFI_COMMON_BASE + 0x1005)
54#define HFI_ERR_SESSION_INCORRECT_STATE_OPERATION \
55 (HFI_COMMON_BASE + 0x1006)
56#define HFI_ERR_SESSION_UNSUPPORTED_PROPERTY (HFI_COMMON_BASE + 0x1007)
57
58#define HFI_ERR_SESSION_UNSUPPORTED_SETTING (HFI_COMMON_BASE + 0x1008)
59
60#define HFI_ERR_SESSION_INSUFFICIENT_RESOURCES (HFI_COMMON_BASE + 0x1009)
61
62#define HFI_ERR_SESSION_STREAM_CORRUPT_OUTPUT_STALLED \
63 (HFI_COMMON_BASE + 0x100A)
64
65#define HFI_ERR_SESSION_STREAM_CORRUPT (HFI_COMMON_BASE + 0x100B)
66#define HFI_ERR_SESSION_ENC_OVERFLOW (HFI_COMMON_BASE + 0x100C)
67#define HFI_ERR_SESSION_UNSUPPORTED_STREAM (HFI_COMMON_BASE + 0x100D)
68#define HFI_ERR_SESSION_CMDSIZE (HFI_COMMON_BASE + 0x100E)
69#define HFI_ERR_SESSION_UNSUPPORT_CMD (HFI_COMMON_BASE + 0x100F)
70#define HFI_ERR_SESSION_UNSUPPORT_BUFFERTYPE (HFI_COMMON_BASE + 0x1010)
71#define HFI_ERR_SESSION_BUFFERCOUNT_TOOSMALL (HFI_COMMON_BASE + 0x1011)
72#define HFI_ERR_SESSION_INVALID_SCALE_FACTOR (HFI_COMMON_BASE + 0x1012)
73#define HFI_ERR_SESSION_UPSCALE_NOT_SUPPORTED (HFI_COMMON_BASE + 0x1013)
74
75#define HFI_EVENT_SYS_ERROR (HFI_COMMON_BASE + 0x1)
76#define HFI_EVENT_SESSION_ERROR (HFI_COMMON_BASE + 0x2)
77
78#define HFI_VIDEO_CODEC_H264 0x00000002
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080079#define HFI_VIDEO_CODEC_MPEG1 0x00000008
80#define HFI_VIDEO_CODEC_MPEG2 0x00000010
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080081#define HFI_VIDEO_CODEC_VP8 0x00001000
82#define HFI_VIDEO_CODEC_HEVC 0x00002000
83#define HFI_VIDEO_CODEC_VP9 0x00004000
84#define HFI_VIDEO_CODEC_HEVC_HYBRID 0x80000000
85
86#define HFI_H264_PROFILE_BASELINE 0x00000001
87#define HFI_H264_PROFILE_MAIN 0x00000002
88#define HFI_H264_PROFILE_HIGH 0x00000004
89#define HFI_H264_PROFILE_STEREO_HIGH 0x00000008
90#define HFI_H264_PROFILE_MULTIVIEW_HIGH 0x00000010
91#define HFI_H264_PROFILE_CONSTRAINED_BASE 0x00000020
92#define HFI_H264_PROFILE_CONSTRAINED_HIGH 0x00000040
93
94#define HFI_H264_LEVEL_1 0x00000001
95#define HFI_H264_LEVEL_1b 0x00000002
96#define HFI_H264_LEVEL_11 0x00000004
97#define HFI_H264_LEVEL_12 0x00000008
98#define HFI_H264_LEVEL_13 0x00000010
99#define HFI_H264_LEVEL_2 0x00000020
100#define HFI_H264_LEVEL_21 0x00000040
101#define HFI_H264_LEVEL_22 0x00000080
102#define HFI_H264_LEVEL_3 0x00000100
103#define HFI_H264_LEVEL_31 0x00000200
104#define HFI_H264_LEVEL_32 0x00000400
105#define HFI_H264_LEVEL_4 0x00000800
106#define HFI_H264_LEVEL_41 0x00001000
107#define HFI_H264_LEVEL_42 0x00002000
108#define HFI_H264_LEVEL_5 0x00004000
109#define HFI_H264_LEVEL_51 0x00008000
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800110#define HFI_H264_LEVEL_52 0x00010000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800111
112#define HFI_MPEG2_PROFILE_SIMPLE 0x00000001
113#define HFI_MPEG2_PROFILE_MAIN 0x00000002
114#define HFI_MPEG2_PROFILE_422 0x00000004
115#define HFI_MPEG2_PROFILE_SNR 0x00000008
116#define HFI_MPEG2_PROFILE_SPATIAL 0x00000010
117#define HFI_MPEG2_PROFILE_HIGH 0x00000020
118
119#define HFI_MPEG2_LEVEL_LL 0x00000001
120#define HFI_MPEG2_LEVEL_ML 0x00000002
121#define HFI_MPEG2_LEVEL_H14 0x00000004
122#define HFI_MPEG2_LEVEL_HL 0x00000008
123
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800124#define HFI_VPX_PROFILE_SIMPLE 0x00000001
125#define HFI_VPX_PROFILE_ADVANCED 0x00000002
126#define HFI_VPX_PROFILE_VERSION_0 0x00000004
127#define HFI_VPX_PROFILE_VERSION_1 0x00000008
128#define HFI_VPX_PROFILE_VERSION_2 0x00000010
129#define HFI_VPX_PROFILE_VERSION_3 0x00000020
130
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800131#define HFI_HEVC_PROFILE_MAIN 0x00000001
132#define HFI_HEVC_PROFILE_MAIN10 0x00000002
133#define HFI_HEVC_PROFILE_MAIN_STILL_PIC 0x00000004
134
135#define HFI_HEVC_LEVEL_1 0x00000001
136#define HFI_HEVC_LEVEL_2 0x00000002
137#define HFI_HEVC_LEVEL_21 0x00000004
138#define HFI_HEVC_LEVEL_3 0x00000008
139#define HFI_HEVC_LEVEL_31 0x00000010
140#define HFI_HEVC_LEVEL_4 0x00000020
141#define HFI_HEVC_LEVEL_41 0x00000040
142#define HFI_HEVC_LEVEL_5 0x00000080
143#define HFI_HEVC_LEVEL_51 0x00000100
144#define HFI_HEVC_LEVEL_52 0x00000200
145#define HFI_HEVC_LEVEL_6 0x00000400
146#define HFI_HEVC_LEVEL_61 0x00000800
147#define HFI_HEVC_LEVEL_62 0x00001000
148
149#define HFI_HEVC_TIER_MAIN 0x1
150#define HFI_HEVC_TIER_HIGH0 0x2
151
152#define HFI_BUFFER_INPUT (HFI_COMMON_BASE + 0x1)
153#define HFI_BUFFER_OUTPUT (HFI_COMMON_BASE + 0x2)
154#define HFI_BUFFER_OUTPUT2 (HFI_COMMON_BASE + 0x3)
155#define HFI_BUFFER_INTERNAL_PERSIST (HFI_COMMON_BASE + 0x4)
156#define HFI_BUFFER_INTERNAL_PERSIST_1 (HFI_COMMON_BASE + 0x5)
157
158#define HFI_BITDEPTH_8 (HFI_COMMON_BASE + 0x0)
159#define HFI_BITDEPTH_9 (HFI_COMMON_BASE + 0x1)
160#define HFI_BITDEPTH_10 (HFI_COMMON_BASE + 0x2)
161
162#define HFI_VENC_PERFMODE_MAX_QUALITY 0x1
163#define HFI_VENC_PERFMODE_POWER_SAVE 0x2
164
165struct hfi_buffer_info {
166 u32 buffer_addr;
167 u32 extra_data_addr;
168};
169
170#define HFI_PROPERTY_SYS_COMMON_START \
171 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x0000)
172#define HFI_PROPERTY_SYS_DEBUG_CONFIG \
173 (HFI_PROPERTY_SYS_COMMON_START + 0x001)
174#define HFI_PROPERTY_SYS_RESOURCE_OCMEM_REQUIREMENT_INFO \
175 (HFI_PROPERTY_SYS_COMMON_START + 0x002)
176#define HFI_PROPERTY_SYS_CONFIG_VCODEC_CLKFREQ \
177 (HFI_PROPERTY_SYS_COMMON_START + 0x003)
178#define HFI_PROPERTY_SYS_IDLE_INDICATOR \
179 (HFI_PROPERTY_SYS_COMMON_START + 0x004)
180#define HFI_PROPERTY_SYS_CODEC_POWER_PLANE_CTRL \
181 (HFI_PROPERTY_SYS_COMMON_START + 0x005)
182#define HFI_PROPERTY_SYS_IMAGE_VERSION \
183 (HFI_PROPERTY_SYS_COMMON_START + 0x006)
184#define HFI_PROPERTY_SYS_CONFIG_COVERAGE \
185 (HFI_PROPERTY_SYS_COMMON_START + 0x007)
186
187#define HFI_PROPERTY_PARAM_COMMON_START \
188 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000)
189#define HFI_PROPERTY_PARAM_FRAME_SIZE \
190 (HFI_PROPERTY_PARAM_COMMON_START + 0x001)
191#define HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO \
192 (HFI_PROPERTY_PARAM_COMMON_START + 0x002)
193#define HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT \
194 (HFI_PROPERTY_PARAM_COMMON_START + 0x003)
195#define HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SUPPORTED \
196 (HFI_PROPERTY_PARAM_COMMON_START + 0x004)
197#define HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT \
198 (HFI_PROPERTY_PARAM_COMMON_START + 0x005)
199#define HFI_PROPERTY_PARAM_PROFILE_LEVEL_SUPPORTED \
200 (HFI_PROPERTY_PARAM_COMMON_START + 0x006)
201#define HFI_PROPERTY_PARAM_CAPABILITY_SUPPORTED \
202 (HFI_PROPERTY_PARAM_COMMON_START + 0x007)
203#define HFI_PROPERTY_PARAM_PROPERTIES_SUPPORTED \
204 (HFI_PROPERTY_PARAM_COMMON_START + 0x008)
205#define HFI_PROPERTY_PARAM_CODEC_SUPPORTED \
206 (HFI_PROPERTY_PARAM_COMMON_START + 0x009)
207#define HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SUPPORTED \
208 (HFI_PROPERTY_PARAM_COMMON_START + 0x00A)
209#define HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SELECT \
210 (HFI_PROPERTY_PARAM_COMMON_START + 0x00B)
211#define HFI_PROPERTY_PARAM_MULTI_VIEW_FORMAT \
212 (HFI_PROPERTY_PARAM_COMMON_START + 0x00C)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800213#define HFI_PROPERTY_PARAM_CODEC_MASK_SUPPORTED \
214 (HFI_PROPERTY_PARAM_COMMON_START + 0x00E)
215#define HFI_PROPERTY_PARAM_MVC_BUFFER_LAYOUT \
216 (HFI_PROPERTY_PARAM_COMMON_START + 0x00F)
217#define HFI_PROPERTY_PARAM_MAX_SESSIONS_SUPPORTED \
218 (HFI_PROPERTY_PARAM_COMMON_START + 0x010)
219
220#define HFI_PROPERTY_CONFIG_COMMON_START \
221 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x2000)
222#define HFI_PROPERTY_CONFIG_FRAME_RATE \
223 (HFI_PROPERTY_CONFIG_COMMON_START + 0x001)
224
225#define HFI_PROPERTY_PARAM_VDEC_COMMON_START \
226 (HFI_DOMAIN_BASE_VDEC + HFI_ARCH_COMMON_OFFSET + 0x3000)
227#define HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM \
228 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x001)
229#define HFI_PROPERTY_PARAM_VDEC_CONCEAL_COLOR \
230 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x002)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800231#define HFI_PROPERTY_PARAM_VDEC_PIXEL_BITDEPTH \
232 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x007)
233#define HFI_PROPERTY_PARAM_VDEC_PIC_STRUCT \
234 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x009)
235#define HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE \
236 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x00A)
237
238
239#define HFI_PROPERTY_CONFIG_VDEC_COMMON_START \
240 (HFI_DOMAIN_BASE_VDEC + HFI_ARCH_COMMON_OFFSET + 0x4000)
241
242#define HFI_PROPERTY_PARAM_VENC_COMMON_START \
243 (HFI_DOMAIN_BASE_VENC + HFI_ARCH_COMMON_OFFSET + 0x5000)
244#define HFI_PROPERTY_PARAM_VENC_SLICE_DELIVERY_MODE \
245 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x001)
246#define HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL \
247 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x002)
248#define HFI_PROPERTY_PARAM_VENC_H264_DEBLOCK_CONTROL \
249 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x003)
250#define HFI_PROPERTY_PARAM_VENC_RATE_CONTROL \
251 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x004)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800252#define HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE \
253 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x008)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800254#define HFI_PROPERTY_PARAM_VENC_OPEN_GOP \
255 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00C)
256#define HFI_PROPERTY_PARAM_VENC_INTRA_REFRESH \
257 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00D)
258#define HFI_PROPERTY_PARAM_VENC_MULTI_SLICE_CONTROL \
259 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00E)
260#define HFI_PROPERTY_PARAM_VENC_VBV_HRD_BUF_SIZE \
261 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00F)
262#define HFI_PROPERTY_PARAM_VENC_QUALITY_VS_SPEED \
263 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x010)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800264#define HFI_PROPERTY_PARAM_VENC_H264_SPS_ID \
265 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x014)
266#define HFI_PROPERTY_PARAM_VENC_H264_PPS_ID \
267 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x015)
268#define HFI_PROPERTY_PARAM_VENC_H264_GENERATE_AUDNAL \
269 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x016)
270#define HFI_PROPERTY_PARAM_VENC_ASPECT_RATIO \
271 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x017)
272#define HFI_PROPERTY_PARAM_VENC_NUMREF \
273 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x018)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800274#define HFI_PROPERTY_PARAM_VENC_H264_NAL_SVC_EXT \
275 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01B)
276#define HFI_PROPERTY_PARAM_VENC_LTRMODE \
277 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01C)
278#define HFI_PROPERTY_PARAM_VENC_VIDEO_SIGNAL_INFO \
279 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01D)
280#define HFI_PROPERTY_PARAM_VENC_H264_VUI_TIMING_INFO \
281 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01E)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800282#define HFI_PROPERTY_PARAM_VENC_MAX_NUM_B_FRAMES \
283 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x020)
284#define HFI_PROPERTY_PARAM_VENC_H264_VUI_BITSTREAM_RESTRC \
285 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x021)
286#define HFI_PROPERTY_PARAM_VENC_LOW_LATENCY_MODE \
287 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x022)
288#define HFI_PROPERTY_PARAM_VENC_PRESERVE_TEXT_QUALITY \
289 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x023)
290#define HFI_PROPERTY_PARAM_VENC_H264_8X8_TRANSFORM \
291 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x025)
292#define HFI_PROPERTY_PARAM_VENC_HIER_P_MAX_NUM_ENH_LAYER \
293 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x026)
294#define HFI_PROPERTY_PARAM_VENC_DISABLE_RC_TIMESTAMP \
295 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x027)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800296#define HFI_PROPERTY_PARAM_VENC_VPX_ERROR_RESILIENCE_MODE \
297 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x029)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800298#define HFI_PROPERTY_PARAM_VENC_HIER_B_MAX_NUM_ENH_LAYER \
299 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x02C)
300#define HFI_PROPERTY_PARAM_VENC_HIER_P_HYBRID_MODE \
301 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x02F)
302#define HFI_PROPERTY_PARAM_VENC_BITRATE_TYPE \
303 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x031)
304#define HFI_PROPERTY_PARAM_VENC_VQZIP_SEI_TYPE \
305 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x033)
306#define HFI_PROPERTY_PARAM_VENC_IFRAMESIZE \
307 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x034)
308
309#define HFI_PROPERTY_CONFIG_VENC_COMMON_START \
310 (HFI_DOMAIN_BASE_VENC + HFI_ARCH_COMMON_OFFSET + 0x6000)
311#define HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE \
312 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x001)
313#define HFI_PROPERTY_CONFIG_VENC_IDR_PERIOD \
314 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x002)
315#define HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD \
316 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x003)
317#define HFI_PROPERTY_CONFIG_VENC_REQUEST_SYNC_FRAME \
318 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x004)
319#define HFI_PROPERTY_CONFIG_VENC_SLICE_SIZE \
320 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x005)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800321#define HFI_PROPERTY_PARAM_VPE_COMMON_START \
322 (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x7000)
323#define HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER \
324 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x008)
325#define HFI_PROPERTY_CONFIG_VENC_MARKLTRFRAME \
326 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x009)
327#define HFI_PROPERTY_CONFIG_VENC_USELTRFRAME \
328 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00A)
329#define HFI_PROPERTY_CONFIG_VENC_HIER_P_ENH_LAYER \
330 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00B)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800331#define HFI_PROPERTY_CONFIG_VENC_PERF_MODE \
332 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00E)
333#define HFI_PROPERTY_CONFIG_VENC_BASELAYER_PRIORITYID \
334 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00F)
335
336#define HFI_PROPERTY_CONFIG_VPE_COMMON_START \
337 (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x8000)
338#define HFI_PROPERTY_CONFIG_VENC_BLUR_FRAME_SIZE \
339 (HFI_PROPERTY_CONFIG_COMMON_START + 0x010)
340#define HFI_PROPERTY_CONFIG_VPE_DEINTERLACE \
341 (HFI_PROPERTY_CONFIG_VPE_COMMON_START + 0x001)
342#define HFI_PROPERTY_CONFIG_VPE_OPERATIONS \
343 (HFI_PROPERTY_CONFIG_VPE_COMMON_START + 0x002)
344
345struct hfi_pic_struct {
346 u32 progressive_only;
347};
348
349struct hfi_bitrate {
350 u32 bit_rate;
351 u32 layer_id;
352};
353
354struct hfi_colour_space {
355 u32 colour_space;
356};
357
358#define HFI_CAPABILITY_FRAME_WIDTH (HFI_COMMON_BASE + 0x1)
359#define HFI_CAPABILITY_FRAME_HEIGHT (HFI_COMMON_BASE + 0x2)
360#define HFI_CAPABILITY_MBS_PER_FRAME (HFI_COMMON_BASE + 0x3)
361#define HFI_CAPABILITY_MBS_PER_SECOND (HFI_COMMON_BASE + 0x4)
362#define HFI_CAPABILITY_FRAMERATE (HFI_COMMON_BASE + 0x5)
363#define HFI_CAPABILITY_SCALE_X (HFI_COMMON_BASE + 0x6)
364#define HFI_CAPABILITY_SCALE_Y (HFI_COMMON_BASE + 0x7)
365#define HFI_CAPABILITY_BITRATE (HFI_COMMON_BASE + 0x8)
366#define HFI_CAPABILITY_BFRAME (HFI_COMMON_BASE + 0x9)
367#define HFI_CAPABILITY_PEAKBITRATE (HFI_COMMON_BASE + 0xa)
368#define HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x10)
369#define HFI_CAPABILITY_ENC_LTR_COUNT (HFI_COMMON_BASE + 0x11)
370#define HFI_CAPABILITY_CP_OUTPUT2_THRESH (HFI_COMMON_BASE + 0x12)
371#define HFI_CAPABILITY_HIER_B_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x13)
372#define HFI_CAPABILITY_LCU_SIZE (HFI_COMMON_BASE + 0x14)
373#define HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x15)
374#define HFI_CAPABILITY_MBS_PER_SECOND_POWERSAVE (HFI_COMMON_BASE + 0x16)
375
376struct hfi_capability_supported {
377 u32 capability_type;
378 u32 min;
379 u32 max;
380 u32 step_size;
381};
382
383struct hfi_capability_supported_info {
384 u32 num_capabilities;
385 struct hfi_capability_supported rg_data[1];
386};
387
388#define HFI_DEBUG_MSG_LOW 0x00000001
389#define HFI_DEBUG_MSG_MEDIUM 0x00000002
390#define HFI_DEBUG_MSG_HIGH 0x00000004
391#define HFI_DEBUG_MSG_ERROR 0x00000008
392#define HFI_DEBUG_MSG_FATAL 0x00000010
393#define HFI_DEBUG_MSG_PERF 0x00000020
394
395#define HFI_DEBUG_MODE_QUEUE 0x00000001
396#define HFI_DEBUG_MODE_QDSS 0x00000002
397
398struct hfi_debug_config {
399 u32 debug_config;
400 u32 debug_mode;
401};
402
403struct hfi_enable {
404 u32 enable;
405};
406
407#define HFI_H264_DB_MODE_DISABLE (HFI_COMMON_BASE + 0x1)
408#define HFI_H264_DB_MODE_SKIP_SLICE_BOUNDARY \
409 (HFI_COMMON_BASE + 0x2)
410#define HFI_H264_DB_MODE_ALL_BOUNDARY (HFI_COMMON_BASE + 0x3)
411
412struct hfi_h264_db_control {
413 u32 mode;
414 u32 slice_alpha_offset;
415 u32 slice_beta_offset;
416};
417
418#define HFI_H264_ENTROPY_CAVLC (HFI_COMMON_BASE + 0x1)
419#define HFI_H264_ENTROPY_CABAC (HFI_COMMON_BASE + 0x2)
420
421#define HFI_H264_CABAC_MODEL_0 (HFI_COMMON_BASE + 0x1)
422#define HFI_H264_CABAC_MODEL_1 (HFI_COMMON_BASE + 0x2)
423#define HFI_H264_CABAC_MODEL_2 (HFI_COMMON_BASE + 0x3)
424
425struct hfi_h264_entropy_control {
426 u32 entropy_mode;
427 u32 cabac_model;
428};
429
430struct hfi_frame_rate {
431 u32 buffer_type;
432 u32 frame_rate;
433};
434
435#define HFI_INTRA_REFRESH_NONE (HFI_COMMON_BASE + 0x1)
436#define HFI_INTRA_REFRESH_CYCLIC (HFI_COMMON_BASE + 0x2)
437#define HFI_INTRA_REFRESH_ADAPTIVE (HFI_COMMON_BASE + 0x3)
438#define HFI_INTRA_REFRESH_CYCLIC_ADAPTIVE (HFI_COMMON_BASE + 0x4)
439#define HFI_INTRA_REFRESH_RANDOM (HFI_COMMON_BASE + 0x5)
440
441struct hfi_intra_refresh {
442 u32 mode;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800443 u32 mbs;
444};
445
446struct hfi_idr_period {
447 u32 idr_period;
448};
449
450struct hfi_operations_type {
451 u32 rotation;
452 u32 flip;
453};
454
455struct hfi_max_num_b_frames {
456 u32 max_num_b_frames;
457};
458
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800459struct hfi_conceal_color {
460 u32 conceal_color;
461};
462
463struct hfi_intra_period {
464 u32 pframes;
465 u32 bframes;
466};
467
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800468struct hfi_multi_stream {
469 u32 buffer_type;
470 u32 enable;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800471};
472
473struct hfi_multi_view_format {
474 u32 views;
475 u32 rg_view_order[1];
476};
477
478#define HFI_MULTI_SLICE_OFF (HFI_COMMON_BASE + 0x1)
479#define HFI_MULTI_SLICE_BY_MB_COUNT (HFI_COMMON_BASE + 0x2)
480#define HFI_MULTI_SLICE_BY_BYTE_COUNT (HFI_COMMON_BASE + 0x3)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800481
482struct hfi_multi_slice_control {
483 u32 multi_slice;
484 u32 slice_size;
485};
486
487#define HFI_NAL_FORMAT_STARTCODES 0x00000001
488#define HFI_NAL_FORMAT_ONE_NAL_PER_BUFFER 0x00000002
489#define HFI_NAL_FORMAT_ONE_BYTE_LENGTH 0x00000004
490#define HFI_NAL_FORMAT_TWO_BYTE_LENGTH 0x00000008
491#define HFI_NAL_FORMAT_FOUR_BYTE_LENGTH 0x00000010
492
493struct hfi_nal_stream_format_supported {
494 u32 nal_stream_format_supported;
495};
496
497struct hfi_nal_stream_format_select {
498 u32 nal_stream_format_select;
499};
500#define HFI_PICTURE_TYPE_I 0x01
501#define HFI_PICTURE_TYPE_P 0x02
502#define HFI_PICTURE_TYPE_B 0x04
503#define HFI_PICTURE_TYPE_IDR 0x08
504#define HFI_PICTURE_TYPE_CRA 0x10
505
506struct hfi_profile_level {
507 u32 profile;
508 u32 level;
509};
510
511struct hfi_profile_level_supported {
512 u32 profile_count;
513 struct hfi_profile_level rg_profile_level[1];
514};
515
516struct hfi_quality_vs_speed {
517 u32 quality_vs_speed;
518};
519
520struct hfi_quantization {
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800521 u32 qp_packed;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800522 u32 layer_id;
523};
524
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800525struct hfi_quantization_range {
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800526 struct hfi_quantization min_qp;
527 struct hfi_quantization max_qp;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800528};
529
530#define HFI_LTR_MODE_DISABLE 0x0
531#define HFI_LTR_MODE_MANUAL 0x1
532#define HFI_LTR_MODE_PERIODIC 0x2
533
534struct hfi_ltr_mode {
535 u32 ltr_mode;
536 u32 ltr_count;
537 u32 trust_mode;
538};
539
540struct hfi_ltr_use {
541 u32 ref_ltr;
542 u32 use_constrnt;
543 u32 frames;
544};
545
546struct hfi_ltr_mark {
547 u32 mark_frame;
548};
549
550struct hfi_frame_size {
551 u32 buffer_type;
552 u32 width;
553 u32 height;
554};
555
556struct hfi_video_signal_metadata {
557 u32 enable;
558 u32 video_format;
559 u32 video_full_range;
560 u32 color_description;
561 u32 color_primaries;
562 u32 transfer_characteristics;
563 u32 matrix_coeffs;
564};
565
566struct hfi_h264_vui_timing_info {
567 u32 enable;
568 u32 fixed_frame_rate;
569 u32 time_scale;
570};
571
572struct hfi_bit_depth {
573 u32 buffer_type;
574 u32 bit_depth;
575};
576
577struct hfi_picture_type {
578 u32 is_sync_frame;
579 u32 picture_type;
580};
581
582/* Base Offset for UBWC color formats */
583#define HFI_COLOR_FORMAT_UBWC_BASE (0x8000)
584/* Base Offset for 10-bit color formats */
585#define HFI_COLOR_FORMAT_10_BIT_BASE (0x4000)
586
587#define HFI_COLOR_FORMAT_MONOCHROME (HFI_COMMON_BASE + 0x1)
588#define HFI_COLOR_FORMAT_NV12 (HFI_COMMON_BASE + 0x2)
589#define HFI_COLOR_FORMAT_NV21 (HFI_COMMON_BASE + 0x3)
590#define HFI_COLOR_FORMAT_NV12_4x4TILE (HFI_COMMON_BASE + 0x4)
591#define HFI_COLOR_FORMAT_NV21_4x4TILE (HFI_COMMON_BASE + 0x5)
592#define HFI_COLOR_FORMAT_YUYV (HFI_COMMON_BASE + 0x6)
593#define HFI_COLOR_FORMAT_YVYU (HFI_COMMON_BASE + 0x7)
594#define HFI_COLOR_FORMAT_UYVY (HFI_COMMON_BASE + 0x8)
595#define HFI_COLOR_FORMAT_VYUY (HFI_COMMON_BASE + 0x9)
596#define HFI_COLOR_FORMAT_RGB565 (HFI_COMMON_BASE + 0xA)
597#define HFI_COLOR_FORMAT_BGR565 (HFI_COMMON_BASE + 0xB)
598#define HFI_COLOR_FORMAT_RGB888 (HFI_COMMON_BASE + 0xC)
599#define HFI_COLOR_FORMAT_BGR888 (HFI_COMMON_BASE + 0xD)
600#define HFI_COLOR_FORMAT_YUV444 (HFI_COMMON_BASE + 0xE)
601#define HFI_COLOR_FORMAT_RGBA8888 (HFI_COMMON_BASE + 0x10)
602
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800603#define HFI_COLOR_FORMAT_P010 \
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800604 (HFI_COLOR_FORMAT_10_BIT_BASE + HFI_COLOR_FORMAT_NV12)
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800605#define HFI_COLOR_FORMAT_YUV420_TP10 \
606 (HFI_COLOR_FORMAT_10_BIT_BASE + HFI_COLOR_FORMAT_NV12_4x4TILE)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800607
608#define HFI_COLOR_FORMAT_NV12_UBWC \
609 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_NV12)
610
611#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC \
612 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_YUV420_TP10)
613
614#define HFI_COLOR_FORMAT_RGBA8888_UBWC \
615 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_RGBA8888)
616
617#define HFI_MAX_MATRIX_COEFFS 9
618#define HFI_MAX_BIAS_COEFFS 3
619#define HFI_MAX_LIMIT_COEFFS 6
620
621#define HFI_STATISTICS_MODE_DEFAULT 0x10
622#define HFI_STATISTICS_MODE_1 0x11
623#define HFI_STATISTICS_MODE_2 0x12
624#define HFI_STATISTICS_MODE_3 0x13
625
626struct hfi_uncompressed_format_select {
627 u32 buffer_type;
628 u32 format;
629};
630
631struct hfi_uncompressed_format_supported {
632 u32 buffer_type;
633 u32 format_entries;
634 u32 rg_format_info[1];
635};
636
637struct hfi_uncompressed_plane_actual {
638 u32 actual_stride;
639 u32 actual_plane_buffer_height;
640};
641
642struct hfi_uncompressed_plane_actual_info {
643 u32 buffer_type;
644 u32 num_planes;
645 struct hfi_uncompressed_plane_actual rg_plane_format[1];
646};
647
648struct hfi_uncompressed_plane_constraints {
649 u32 stride_multiples;
650 u32 max_stride;
651 u32 min_plane_buffer_height_multiple;
652 u32 buffer_alignment;
653};
654
655struct hfi_uncompressed_plane_info {
656 u32 format;
657 u32 num_planes;
658 struct hfi_uncompressed_plane_constraints rg_plane_format[1];
659};
660
661struct hfi_codec_supported {
662 u32 decoder_codec_supported;
663 u32 encoder_codec_supported;
664};
665
666struct hfi_properties_supported {
667 u32 num_properties;
668 u32 rg_properties[1];
669};
670
671struct hfi_max_sessions_supported {
672 u32 max_sessions;
673};
674
675struct hfi_vpe_color_space_conversion {
676 u32 csc_matrix[HFI_MAX_MATRIX_COEFFS];
677 u32 csc_bias[HFI_MAX_BIAS_COEFFS];
678 u32 csc_limit[HFI_MAX_LIMIT_COEFFS];
679};
680
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800681#define HFI_ROTATE_NONE (HFI_COMMON_BASE + 0x1)
682#define HFI_ROTATE_90 (HFI_COMMON_BASE + 0x2)
683#define HFI_ROTATE_180 (HFI_COMMON_BASE + 0x3)
684#define HFI_ROTATE_270 (HFI_COMMON_BASE + 0x4)
685
686#define HFI_FLIP_NONE (HFI_COMMON_BASE + 0x1)
687#define HFI_FLIP_HORIZONTAL (HFI_COMMON_BASE + 0x2)
688#define HFI_FLIP_VERTICAL (HFI_COMMON_BASE + 0x3)
689
690struct hfi_operations {
691 u32 rotate;
692 u32 flip;
693};
694
695#define HFI_RESOURCE_OCMEM 0x00000001
696
697struct hfi_resource_ocmem {
698 u32 size;
699 u32 mem;
700};
701
702struct hfi_resource_ocmem_requirement {
703 u32 session_domain;
704 u32 width;
705 u32 height;
706 u32 size;
707};
708
709struct hfi_resource_ocmem_requirement_info {
710 u32 num_entries;
711 struct hfi_resource_ocmem_requirement rg_requirements[1];
712};
713
714struct hfi_property_sys_image_version_info_type {
715 u32 string_size;
716 u8 str_image_version[1];
717};
718
719struct hfi_venc_config_advanced {
720 u8 pipe2d;
721 u8 hw_mode;
722 u8 low_delay_enforce;
723 u8 worker_vppsg_delay;
724 u32 close_gop;
725 u32 h264_constrain_intra_pred;
726 u32 h264_transform_8x8_flag;
727 u32 mpeg4_qpel_enable;
728 u32 multi_refp_en;
729 u32 qmatrix_en;
730 u8 vpp_info_packet_mode;
731 u8 ref_tile_mode;
732 u8 bitstream_flush_mode;
733 u32 vppsg_vspap_fb_sync_delay;
734 u32 rc_initial_delay;
735 u32 peak_bitrate_constraint;
736 u32 ds_display_frame_width;
737 u32 ds_display_frame_height;
738 u32 perf_tune_param_ptr;
739 u32 input_x_offset;
740 u32 input_y_offset;
741 u32 input_roi_width;
742 u32 input_roi_height;
743 u32 vsp_fifo_dma_sel;
744 u32 h264_num_ref_frames;
745};
746
747struct hfi_vbv_hrd_bufsize {
748 u32 buffer_size;
749};
750
751struct hfi_codec_mask_supported {
752 u32 codecs;
753 u32 video_domains;
754};
755
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800756struct hfi_aspect_ratio {
757 u32 aspect_width;
758 u32 aspect_height;
759};
760
761#define HFI_IFRAME_SIZE_DEFAULT (HFI_COMMON_BASE + 0x1)
762#define HFI_IFRAME_SIZE_MEDIUM (HFI_COMMON_BASE + 0x2)
763#define HFI_IFRAME_SIZE_HIGH (HFI_COMMON_BASE + 0x3)
764#define HFI_IFRAME_SIZE_UNLIMITED (HFI_COMMON_BASE + 0x4)
765struct hfi_iframe_size {
766 u32 type;
767};
768
769#define HFI_MVC_BUFFER_LAYOUT_TOP_BOTTOM (0)
770#define HFI_MVC_BUFFER_LAYOUT_SIDEBYSIDE (1)
771#define HFI_MVC_BUFFER_LAYOUT_SEQ (2)
772struct hfi_mvc_buffer_layout_descp_type {
773 u32 layout_type;
774 u32 bright_view_first;
775 u32 ngap;
776};
777
778
779#define HFI_CMD_SYS_COMMON_START \
780(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + HFI_CMD_START_OFFSET \
781 + 0x0000)
782#define HFI_CMD_SYS_INIT (HFI_CMD_SYS_COMMON_START + 0x001)
783#define HFI_CMD_SYS_PC_PREP (HFI_CMD_SYS_COMMON_START + 0x002)
784#define HFI_CMD_SYS_SET_RESOURCE (HFI_CMD_SYS_COMMON_START + 0x003)
785#define HFI_CMD_SYS_RELEASE_RESOURCE (HFI_CMD_SYS_COMMON_START + 0x004)
786#define HFI_CMD_SYS_SET_PROPERTY (HFI_CMD_SYS_COMMON_START + 0x005)
787#define HFI_CMD_SYS_GET_PROPERTY (HFI_CMD_SYS_COMMON_START + 0x006)
788#define HFI_CMD_SYS_SESSION_INIT (HFI_CMD_SYS_COMMON_START + 0x007)
789#define HFI_CMD_SYS_SESSION_END (HFI_CMD_SYS_COMMON_START + 0x008)
790#define HFI_CMD_SYS_SET_BUFFERS (HFI_CMD_SYS_COMMON_START + 0x009)
791#define HFI_CMD_SYS_TEST_START (HFI_CMD_SYS_COMMON_START + 0x100)
792
793#define HFI_CMD_SESSION_COMMON_START \
794 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
795 HFI_CMD_START_OFFSET + 0x1000)
796#define HFI_CMD_SESSION_SET_PROPERTY \
797 (HFI_CMD_SESSION_COMMON_START + 0x001)
798#define HFI_CMD_SESSION_SET_BUFFERS \
799 (HFI_CMD_SESSION_COMMON_START + 0x002)
800#define HFI_CMD_SESSION_GET_SEQUENCE_HEADER \
801 (HFI_CMD_SESSION_COMMON_START + 0x003)
802
803#define HFI_MSG_SYS_COMMON_START \
804 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
805 HFI_MSG_START_OFFSET + 0x0000)
806#define HFI_MSG_SYS_INIT_DONE (HFI_MSG_SYS_COMMON_START + 0x1)
807#define HFI_MSG_SYS_PC_PREP_DONE (HFI_MSG_SYS_COMMON_START + 0x2)
808#define HFI_MSG_SYS_RELEASE_RESOURCE (HFI_MSG_SYS_COMMON_START + 0x3)
809#define HFI_MSG_SYS_DEBUG (HFI_MSG_SYS_COMMON_START + 0x4)
810#define HFI_MSG_SYS_SESSION_INIT_DONE (HFI_MSG_SYS_COMMON_START + 0x6)
811#define HFI_MSG_SYS_SESSION_END_DONE (HFI_MSG_SYS_COMMON_START + 0x7)
812#define HFI_MSG_SYS_IDLE (HFI_MSG_SYS_COMMON_START + 0x8)
813#define HFI_MSG_SYS_COV (HFI_MSG_SYS_COMMON_START + 0x9)
814#define HFI_MSG_SYS_PROPERTY_INFO (HFI_MSG_SYS_COMMON_START + 0xA)
815#define HFI_MSG_SESSION_SYNC_DONE (HFI_MSG_SESSION_OX_START + 0xD)
816
817#define HFI_MSG_SESSION_COMMON_START \
818 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
819 HFI_MSG_START_OFFSET + 0x1000)
820#define HFI_MSG_EVENT_NOTIFY (HFI_MSG_SESSION_COMMON_START + 0x1)
821#define HFI_MSG_SESSION_GET_SEQUENCE_HEADER_DONE \
822 (HFI_MSG_SESSION_COMMON_START + 0x2)
823
824#define HFI_CMD_SYS_TEST_SSR (HFI_CMD_SYS_TEST_START + 0x1)
825#define HFI_TEST_SSR_SW_ERR_FATAL 0x1
826#define HFI_TEST_SSR_SW_DIV_BY_ZERO 0x2
827#define HFI_TEST_SSR_HW_WDOG_IRQ 0x3
828
829struct vidc_hal_cmd_pkt_hdr {
830 u32 size;
831 u32 packet_type;
832};
833
834struct vidc_hal_msg_pkt_hdr {
835 u32 size;
836 u32 packet;
837};
838
839struct vidc_hal_session_cmd_pkt {
840 u32 size;
841 u32 packet_type;
842 u32 session_id;
843};
844
845struct hfi_cmd_sys_init_packet {
846 u32 size;
847 u32 packet_type;
848 u32 arch_type;
849};
850
851struct hfi_cmd_sys_pc_prep_packet {
852 u32 size;
853 u32 packet_type;
854};
855
856struct hfi_cmd_sys_set_resource_packet {
857 u32 size;
858 u32 packet_type;
859 u32 resource_handle;
860 u32 resource_type;
861 u32 rg_resource_data[1];
862};
863
864struct hfi_cmd_sys_release_resource_packet {
865 u32 size;
866 u32 packet_type;
867 u32 resource_type;
868 u32 resource_handle;
869};
870
871struct hfi_cmd_sys_set_property_packet {
872 u32 size;
873 u32 packet_type;
874 u32 num_properties;
875 u32 rg_property_data[1];
876};
877
878struct hfi_cmd_sys_get_property_packet {
879 u32 size;
880 u32 packet_type;
881 u32 num_properties;
882 u32 rg_property_data[1];
883};
884
885struct hfi_cmd_sys_session_init_packet {
886 u32 size;
887 u32 packet_type;
888 u32 session_id;
889 u32 session_domain;
890 u32 session_codec;
891};
892
893struct hfi_cmd_sys_session_end_packet {
894 u32 size;
895 u32 packet_type;
896 u32 session_id;
897};
898
899struct hfi_cmd_sys_set_buffers_packet {
900 u32 size;
901 u32 packet_type;
902 u32 buffer_type;
903 u32 buffer_size;
904 u32 num_buffers;
905 u32 rg_buffer_addr[1];
906};
907
908struct hfi_cmd_session_set_property_packet {
909 u32 size;
910 u32 packet_type;
911 u32 session_id;
912 u32 num_properties;
913 u32 rg_property_data[0];
914};
915
916struct hfi_cmd_session_set_buffers_packet {
917 u32 size;
918 u32 packet_type;
919 u32 session_id;
920 u32 buffer_type;
921 u32 buffer_size;
922 u32 extra_data_size;
923 u32 min_buffer_size;
924 u32 num_buffers;
925 u32 rg_buffer_info[1];
926};
927
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800928struct hfi_cmd_session_sync_process_packet {
929 u32 size;
930 u32 packet_type;
931 u32 session_id;
932 u32 sync_id;
933 u32 rg_data[1];
934};
935
936struct hfi_msg_event_notify_packet {
937 u32 size;
938 u32 packet_type;
939 u32 session_id;
940 u32 event_id;
941 u32 event_data1;
942 u32 event_data2;
943 u32 rg_ext_event_data[1];
944};
945
946struct hfi_msg_release_buffer_ref_event_packet {
947 u32 packet_buffer;
948 u32 extra_data_buffer;
949 u32 output_tag;
950};
951
952struct hfi_msg_sys_init_done_packet {
953 u32 size;
954 u32 packet_type;
955 u32 error_type;
956 u32 num_properties;
957 u32 rg_property_data[1];
958};
959
960struct hfi_msg_sys_pc_prep_done_packet {
961 u32 size;
962 u32 packet_type;
963 u32 error_type;
964};
965
966struct hfi_msg_sys_release_resource_done_packet {
967 u32 size;
968 u32 packet_type;
969 u32 resource_handle;
970 u32 error_type;
971};
972
973struct hfi_msg_sys_session_init_done_packet {
974 u32 size;
975 u32 packet_type;
976 u32 session_id;
977 u32 error_type;
978 u32 num_properties;
979 u32 rg_property_data[1];
980};
981
982struct hfi_msg_sys_session_end_done_packet {
983 u32 size;
984 u32 packet_type;
985 u32 session_id;
986 u32 error_type;
987};
988
989struct hfi_msg_session_get_sequence_header_done_packet {
990 u32 size;
991 u32 packet_type;
992 u32 session_id;
993 u32 error_type;
994 u32 header_len;
995 u32 sequence_header;
996};
997
998struct hfi_msg_sys_debug_packet {
999 u32 size;
1000 u32 packet_type;
1001 u32 msg_type;
1002 u32 msg_size;
1003 u32 time_stamp_hi;
1004 u32 time_stamp_lo;
1005 u8 rg_msg_data[1];
1006};
1007
1008struct hfi_msg_sys_coverage_packet {
1009 u32 size;
1010 u32 packet_type;
1011 u32 msg_size;
1012 u32 time_stamp_hi;
1013 u32 time_stamp_lo;
1014 u8 rg_msg_data[1];
1015};
1016
1017enum HFI_VENUS_QTBL_STATUS {
1018 HFI_VENUS_QTBL_DISABLED = 0x00,
1019 HFI_VENUS_QTBL_ENABLED = 0x01,
1020 HFI_VENUS_QTBL_INITIALIZING = 0x02,
1021 HFI_VENUS_QTBL_DEINITIALIZING = 0x03
1022};
1023
1024enum HFI_VENUS_CTRL_INIT_STATUS {
1025 HFI_VENUS_CTRL_NOT_INIT = 0x0,
1026 HFI_VENUS_CTRL_READY = 0x1,
1027 HFI_VENUS_CTRL_ERROR_FATAL = 0x2
1028};
1029
1030struct hfi_sfr_struct {
1031 u32 bufSize;
1032 u8 rg_data[1];
1033};
1034
1035struct hfi_cmd_sys_test_ssr_packet {
1036 u32 size;
1037 u32 packet_type;
1038 u32 trigger_type;
1039};
1040#endif