Blame - drivers/gpu/drm/radeon/r600d.h - kernel/msm-4.9

2009-09-08 10:10:24 +1000

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/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Dave Airlie

* Alex Deucher

* Jerome Glisse

*/

#ifndef R600D_H

#define R600D_H

#define CP_PACKET2 0x80000000

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#define PACKET2_PAD_SHIFT 0

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#define PACKET2_PAD_MASK (0x3fffffff << 0)

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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

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#define R6XX_MAX_SH_GPRS 256

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#define R6XX_MAX_TEMP_GPRS 16

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#define R6XX_MAX_SH_THREADS 256

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#define R6XX_MAX_SH_STACK_ENTRIES 4096

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#define R6XX_MAX_BACKENDS 8

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#define R6XX_MAX_BACKENDS_MASK 0xff

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#define R6XX_MAX_SIMDS 8

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#define R6XX_MAX_SIMDS_MASK 0xff

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#define R6XX_MAX_PIPES 8

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#define R6XX_MAX_PIPES_MASK 0xff

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/* PTE flags */

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#define PTE_VALID (1 << 0)

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#define PTE_SYSTEM (1 << 1)

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#define PTE_SNOOPED (1 << 2)

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#define PTE_READABLE (1 << 5)

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#define PTE_WRITEABLE (1 << 6)

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/* tiling bits */

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#define ARRAY_LINEAR_GENERAL 0x00000000

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#define ARRAY_LINEAR_ALIGNED 0x00000001

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#define ARRAY_1D_TILED_THIN1 0x00000002

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#define ARRAY_2D_TILED_THIN1 0x00000004

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/* Registers */

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#define ARB_POP 0x2418

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#define ENABLE_TC128 (1 << 30)

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#define ARB_GDEC_RD_CNTL 0x246C

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#define CC_GC_SHADER_PIPE_CONFIG 0x8950

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#define CC_RB_BACKEND_DISABLE 0x98F4

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#define BACKEND_DISABLE(x) ((x) << 16)

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#define CB_COLOR0_BASE 0x28040

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#define CB_COLOR1_BASE 0x28044

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#define CB_COLOR2_BASE 0x28048

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#define CB_COLOR3_BASE 0x2804C

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#define CB_COLOR4_BASE 0x28050

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#define CB_COLOR5_BASE 0x28054

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#define CB_COLOR6_BASE 0x28058

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#define CB_COLOR7_BASE 0x2805C

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#define CB_COLOR7_FRAG 0x280FC

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#define CB_COLOR0_SIZE 0x28060

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#define CB_COLOR0_VIEW 0x28080

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#define R_028080_CB_COLOR0_VIEW 0x028080

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#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)

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#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)

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#define C_028080_SLICE_START 0xFFFFF800

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#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)

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#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

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#define C_028080_SLICE_MAX 0xFF001FFF

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#define R_028084_CB_COLOR1_VIEW 0x028084

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#define R_028088_CB_COLOR2_VIEW 0x028088

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#define R_02808C_CB_COLOR3_VIEW 0x02808C

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#define R_028090_CB_COLOR4_VIEW 0x028090

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#define R_028094_CB_COLOR5_VIEW 0x028094

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#define R_028098_CB_COLOR6_VIEW 0x028098

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#define R_02809C_CB_COLOR7_VIEW 0x02809C

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#define CB_COLOR0_INFO 0x280a0

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# define CB_FORMAT(x) ((x) << 2)

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# define CB_ARRAY_MODE(x) ((x) << 8)

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# define CB_SOURCE_FORMAT(x) ((x) << 27)

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# define CB_SF_EXPORT_FULL 0

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# define CB_SF_EXPORT_NORM 1

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#define CB_COLOR0_TILE 0x280c0

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#define CB_COLOR0_FRAG 0x280e0

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#define CB_COLOR0_MASK 0x28100

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#define SQ_ALU_CONST_CACHE_PS_0 0x28940

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#define SQ_ALU_CONST_CACHE_PS_1 0x28944

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#define SQ_ALU_CONST_CACHE_PS_2 0x28948

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#define SQ_ALU_CONST_CACHE_PS_3 0x2894c

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#define SQ_ALU_CONST_CACHE_PS_4 0x28950

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#define SQ_ALU_CONST_CACHE_PS_5 0x28954

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#define SQ_ALU_CONST_CACHE_PS_6 0x28958

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#define SQ_ALU_CONST_CACHE_PS_7 0x2895c

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#define SQ_ALU_CONST_CACHE_PS_8 0x28960

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#define SQ_ALU_CONST_CACHE_PS_9 0x28964

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#define SQ_ALU_CONST_CACHE_PS_10 0x28968

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#define SQ_ALU_CONST_CACHE_PS_11 0x2896c

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#define SQ_ALU_CONST_CACHE_PS_12 0x28970

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#define SQ_ALU_CONST_CACHE_PS_13 0x28974

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#define SQ_ALU_CONST_CACHE_PS_14 0x28978

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#define SQ_ALU_CONST_CACHE_PS_15 0x2897c

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#define SQ_ALU_CONST_CACHE_VS_0 0x28980

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#define SQ_ALU_CONST_CACHE_VS_1 0x28984

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#define SQ_ALU_CONST_CACHE_VS_2 0x28988

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#define SQ_ALU_CONST_CACHE_VS_3 0x2898c

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#define SQ_ALU_CONST_CACHE_VS_4 0x28990

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#define SQ_ALU_CONST_CACHE_VS_5 0x28994

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#define SQ_ALU_CONST_CACHE_VS_6 0x28998

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#define SQ_ALU_CONST_CACHE_VS_7 0x2899c

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#define SQ_ALU_CONST_CACHE_VS_8 0x289a0

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#define SQ_ALU_CONST_CACHE_VS_9 0x289a4

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#define SQ_ALU_CONST_CACHE_VS_10 0x289a8

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#define SQ_ALU_CONST_CACHE_VS_11 0x289ac

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#define SQ_ALU_CONST_CACHE_VS_12 0x289b0

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#define SQ_ALU_CONST_CACHE_VS_13 0x289b4

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#define SQ_ALU_CONST_CACHE_VS_14 0x289b8

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#define SQ_ALU_CONST_CACHE_VS_15 0x289bc

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#define SQ_ALU_CONST_CACHE_GS_0 0x289c0

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#define SQ_ALU_CONST_CACHE_GS_1 0x289c4

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#define SQ_ALU_CONST_CACHE_GS_2 0x289c8

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#define SQ_ALU_CONST_CACHE_GS_3 0x289cc

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#define SQ_ALU_CONST_CACHE_GS_4 0x289d0

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#define SQ_ALU_CONST_CACHE_GS_5 0x289d4

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#define SQ_ALU_CONST_CACHE_GS_6 0x289d8

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#define SQ_ALU_CONST_CACHE_GS_7 0x289dc

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#define SQ_ALU_CONST_CACHE_GS_8 0x289e0

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#define SQ_ALU_CONST_CACHE_GS_9 0x289e4

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#define SQ_ALU_CONST_CACHE_GS_10 0x289e8

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#define SQ_ALU_CONST_CACHE_GS_11 0x289ec

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#define SQ_ALU_CONST_CACHE_GS_12 0x289f0

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#define SQ_ALU_CONST_CACHE_GS_13 0x289f4

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#define SQ_ALU_CONST_CACHE_GS_14 0x289f8

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#define SQ_ALU_CONST_CACHE_GS_15 0x289fc

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#define CONFIG_MEMSIZE 0x5428

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#define CONFIG_CNTL 0x5424

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#define CP_STALLED_STAT1 0x8674

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#define CP_STALLED_STAT2 0x8678

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#define CP_BUSY_STAT 0x867C

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#define CP_STAT 0x8680

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#define CP_COHER_BASE 0x85F8

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#define CP_DEBUG 0xC1FC

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#define R_0086D8_CP_ME_CNTL 0x86D8

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#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)

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#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)

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#define CP_ME_RAM_DATA 0xC160

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#define CP_ME_RAM_RADDR 0xC158

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#define CP_ME_RAM_WADDR 0xC15C

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#define CP_MEQ_THRESHOLDS 0x8764

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#define MEQ_END(x) ((x) << 16)

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#define ROQ_END(x) ((x) << 24)

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#define CP_PERFMON_CNTL 0x87FC

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#define CP_PFP_UCODE_ADDR 0xC150

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#define CP_PFP_UCODE_DATA 0xC154

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#define CP_QUEUE_THRESHOLDS 0x8760

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#define ROQ_IB1_START(x) ((x) << 0)

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#define ROQ_IB2_START(x) ((x) << 8)

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#define CP_RB_BASE 0xC100

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#define CP_RB_CNTL 0xC104

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#define RB_BUFSZ(x) ((x) << 0)

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#define RB_BLKSZ(x) ((x) << 8)

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#define RB_NO_UPDATE (1 << 27)

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#define RB_RPTR_WR_ENA (1 << 31)

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#define BUF_SWAP_32BIT (2 << 16)

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#define CP_RB_RPTR 0x8700

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#define CP_RB_RPTR_ADDR 0xC10C

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#define RB_RPTR_SWAP(x) ((x) << 0)

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#define CP_RB_RPTR_ADDR_HI 0xC110

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#define CP_RB_RPTR_WR 0xC108

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#define CP_RB_WPTR 0xC114

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#define CP_RB_WPTR_ADDR 0xC118

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#define CP_RB_WPTR_ADDR_HI 0xC11C

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#define CP_RB_WPTR_DELAY 0x8704

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#define CP_ROQ_IB1_STAT 0x8784

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#define CP_ROQ_IB2_STAT 0x8788

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#define CP_SEM_WAIT_TIMER 0x85BC

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#define DB_DEBUG 0x9830

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#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)

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#define DB_DEPTH_BASE 0x2800C

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#define DB_HTILE_DATA_BASE 0x28014

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#define DB_HTILE_SURFACE 0x28D24

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#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)

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#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)

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#define C_028D24_HTILE_WIDTH 0xFFFFFFFE

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#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)

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#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)

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#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD

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#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)

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#define DB_WATERMARKS 0x9838

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#define DEPTH_FREE(x) ((x) << 0)

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#define DEPTH_FLUSH(x) ((x) << 5)

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#define DEPTH_PENDING_FREE(x) ((x) << 15)

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#define DEPTH_CACHELINE_FREE(x) ((x) << 20)

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#define DCP_TILING_CONFIG 0x6CA0

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#define PIPE_TILING(x) ((x) << 1)

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#define BANK_TILING(x) ((x) << 4)

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#define GROUP_SIZE(x) ((x) << 6)

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#define ROW_TILING(x) ((x) << 8)

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#define BANK_SWAPS(x) ((x) << 11)

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#define SAMPLE_SPLIT(x) ((x) << 14)

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#define BACKEND_MAP(x) ((x) << 16)

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#define GB_TILING_CONFIG 0x98F0

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#define PIPE_TILING__SHIFT 1

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#define PIPE_TILING__MASK 0x0000000e

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#define GC_USER_SHADER_PIPE_CONFIG 0x8954

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#define INACTIVE_QD_PIPES(x) ((x) << 8)

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#define INACTIVE_QD_PIPES_MASK 0x0000FF00

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#define INACTIVE_SIMDS(x) ((x) << 16)

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#define INACTIVE_SIMDS_MASK 0x00FF0000

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#define SQ_CONFIG 0x8c00

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# define VC_ENABLE (1 << 0)

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# define EXPORT_SRC_C (1 << 1)

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# define DX9_CONSTS (1 << 2)

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# define ALU_INST_PREFER_VECTOR (1 << 3)

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# define DX10_CLAMP (1 << 4)

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# define CLAUSE_SEQ_PRIO(x) ((x) << 8)

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# define PS_PRIO(x) ((x) << 24)

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# define VS_PRIO(x) ((x) << 26)

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# define GS_PRIO(x) ((x) << 28)

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# define ES_PRIO(x) ((x) << 30)

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#define SQ_GPR_RESOURCE_MGMT_1 0x8c04

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# define NUM_PS_GPRS(x) ((x) << 0)

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# define NUM_VS_GPRS(x) ((x) << 16)

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# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)

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#define SQ_GPR_RESOURCE_MGMT_2 0x8c08

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# define NUM_GS_GPRS(x) ((x) << 0)

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# define NUM_ES_GPRS(x) ((x) << 16)

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#define SQ_THREAD_RESOURCE_MGMT 0x8c0c

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# define NUM_PS_THREADS(x) ((x) << 0)

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# define NUM_VS_THREADS(x) ((x) << 8)

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# define NUM_GS_THREADS(x) ((x) << 16)

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# define NUM_ES_THREADS(x) ((x) << 24)

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#define SQ_STACK_RESOURCE_MGMT_1 0x8c10

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# define NUM_PS_STACK_ENTRIES(x) ((x) << 0)

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# define NUM_VS_STACK_ENTRIES(x) ((x) << 16)

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#define SQ_STACK_RESOURCE_MGMT_2 0x8c14

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# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)

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# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)

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#define SQ_ESGS_RING_BASE 0x8c40

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#define SQ_GSVS_RING_BASE 0x8c48

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#define SQ_ESTMP_RING_BASE 0x8c50

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#define SQ_GSTMP_RING_BASE 0x8c58

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#define SQ_VSTMP_RING_BASE 0x8c60

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#define SQ_PSTMP_RING_BASE 0x8c68

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#define SQ_FBUF_RING_BASE 0x8c70

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#define SQ_REDUC_RING_BASE 0x8c78

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#define GRBM_CNTL 0x8000

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# define GRBM_READ_TIMEOUT(x) ((x) << 0)

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#define GRBM_STATUS 0x8010

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#define CMDFIFO_AVAIL_MASK 0x0000001F

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#define GUI_ACTIVE (1<<31)

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#define GRBM_STATUS2 0x8014

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#define GRBM_SOFT_RESET 0x8020

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#define SOFT_RESET_CP (1<<0)

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#define CG_THERMAL_STATUS 0x7F4

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#define ASIC_T(x) ((x) << 0)

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#define ASIC_T_MASK 0x1FF

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#define ASIC_T_SHIFT 0

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#define HDP_HOST_PATH_CNTL 0x2C00

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#define HDP_NONSURFACE_BASE 0x2C04

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#define HDP_NONSURFACE_INFO 0x2C08

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#define HDP_NONSURFACE_SIZE 0x2C0C

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#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

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#define HDP_TILING_CONFIG 0x2F3C

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#define HDP_DEBUG1 0x2F34

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#define MC_VM_AGP_TOP 0x2184

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#define MC_VM_AGP_BOT 0x2188

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#define MC_VM_AGP_BASE 0x218C

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#define MC_VM_FB_LOCATION 0x2180

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#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C

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#define ENABLE_L1_TLB (1 << 0)

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#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

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#define ENABLE_L1_STRICT_ORDERING (1 << 2)

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#define SYSTEM_ACCESS_MODE_MASK 0x000000C0

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#define SYSTEM_ACCESS_MODE_SHIFT 6

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#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)

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#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)

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#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)

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#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)

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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)

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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)

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#define ENABLE_SEMAPHORE_MODE (1 << 10)

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#define ENABLE_WAIT_L2_QUERY (1 << 11)

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#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)

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#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000

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#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12

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#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)

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#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000

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#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15

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#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0

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#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC

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#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204

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#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208

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#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C

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#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200

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#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4

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#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8

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#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210

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#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218

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#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C

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#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220

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#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214

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#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190

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#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF

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#define LOGICAL_PAGE_NUMBER_SHIFT 0

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#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194

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#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198

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#define PA_CL_ENHANCE 0x8A14

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#define CLIP_VTX_REORDER_ENA (1 << 0)

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#define NUM_CLIP_SEQ(x) ((x) << 1)

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#define PA_SC_AA_CONFIG 0x28C04

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#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40

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#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44

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#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48

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#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C

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#define S0_X(x) ((x) << 0)

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#define S0_Y(x) ((x) << 4)

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#define S1_X(x) ((x) << 8)

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#define S1_Y(x) ((x) << 12)

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#define S2_X(x) ((x) << 16)

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#define S2_Y(x) ((x) << 20)

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#define S3_X(x) ((x) << 24)

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#define S3_Y(x) ((x) << 28)

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#define S4_X(x) ((x) << 0)

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#define S4_Y(x) ((x) << 4)

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#define S5_X(x) ((x) << 8)

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#define S5_Y(x) ((x) << 12)

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#define S6_X(x) ((x) << 16)

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#define S6_Y(x) ((x) << 20)

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#define S7_X(x) ((x) << 24)

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#define S7_Y(x) ((x) << 28)

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#define PA_SC_CLIPRECT_RULE 0x2820c

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#define PA_SC_ENHANCE 0x8BF0

363

#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

364

#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)

365

#define PA_SC_LINE_STIPPLE 0x28A0C

366

#define PA_SC_LINE_STIPPLE_STATE 0x8B10

367

#define PA_SC_MODE_CNTL 0x28A4C

368

#define PA_SC_MULTI_CHIP_CNTL 0x8B20

369

370

#define PA_SC_SCREEN_SCISSOR_TL 0x28030

371

#define PA_SC_GENERIC_SCISSOR_TL 0x28240

372

#define PA_SC_WINDOW_SCISSOR_TL 0x28204

373

374

#define PCIE_PORT_INDEX 0x0038

375

#define PCIE_PORT_DATA 0x003C

376

Alex Deucher

5885b7a

2009-10-19 17:23:33 -0400

[diff] [blame]

377

#define CHMAP 0x2004

378

#define NOOFCHAN_SHIFT 12

379

#define NOOFCHAN_MASK 0x00003000

380

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

381

#define RAMCFG 0x2408

382

#define NOOFBANK_SHIFT 0

383

#define NOOFBANK_MASK 0x00000001

384

#define NOOFRANK_SHIFT 1

385

#define NOOFRANK_MASK 0x00000002

386

#define NOOFROWS_SHIFT 2

387

#define NOOFROWS_MASK 0x0000001C

388

#define NOOFCOLS_SHIFT 5

389

#define NOOFCOLS_MASK 0x00000060

390

#define CHANSIZE_SHIFT 7

391

#define CHANSIZE_MASK 0x00000080

392

#define BURSTLENGTH_SHIFT 8

393

#define BURSTLENGTH_MASK 0x00000100

394

#define CHANSIZE_OVERRIDE (1 << 10)

395

396

#define SCRATCH_REG0 0x8500

397

#define SCRATCH_REG1 0x8504

398

#define SCRATCH_REG2 0x8508

399

#define SCRATCH_REG3 0x850C

400

#define SCRATCH_REG4 0x8510

401

#define SCRATCH_REG5 0x8514

402

#define SCRATCH_REG6 0x8518

403

#define SCRATCH_REG7 0x851C

404

#define SCRATCH_UMSK 0x8540

405

#define SCRATCH_ADDR 0x8544

406

407

#define SPI_CONFIG_CNTL 0x9100

408

#define GPR_WRITE_PRIORITY(x) ((x) << 0)

409

#define DISABLE_INTERP_1 (1 << 5)

410

#define SPI_CONFIG_CNTL_1 0x913C

411

#define VTX_DONE_DELAY(x) ((x) << 0)

412

#define INTERP_ONE_PRIM_PER_ROW (1 << 4)

413

#define SPI_INPUT_Z 0x286D8

414

#define SPI_PS_IN_CONTROL_0 0x286CC

415

#define NUM_INTERP(x) ((x)<<0)

416

#define POSITION_ENA (1<<8)

417

#define POSITION_CENTROID (1<<9)

418

#define POSITION_ADDR(x) ((x)<<10)

419

#define PARAM_GEN(x) ((x)<<15)

420

#define PARAM_GEN_ADDR(x) ((x)<<19)

421

#define BARYC_SAMPLE_CNTL(x) ((x)<<26)

422

#define PERSP_GRADIENT_ENA (1<<28)

423

#define LINEAR_GRADIENT_ENA (1<<29)

424

#define POSITION_SAMPLE (1<<30)

425

#define BARYC_AT_SAMPLE_ENA (1<<31)

426

#define SPI_PS_IN_CONTROL_1 0x286D0

427

#define GEN_INDEX_PIX (1<<0)

428

#define GEN_INDEX_PIX_ADDR(x) ((x)<<1)

429

#define FRONT_FACE_ENA (1<<8)

430

#define FRONT_FACE_CHAN(x) ((x)<<9)

431

#define FRONT_FACE_ALL_BITS (1<<11)

432

#define FRONT_FACE_ADDR(x) ((x)<<12)

433

#define FOG_ADDR(x) ((x)<<17)

434

#define FIXED_PT_POSITION_ENA (1<<24)

435

#define FIXED_PT_POSITION_ADDR(x) ((x)<<25)

436

437

#define SQ_MS_FIFO_SIZES 0x8CF0

438

#define CACHE_FIFO_SIZE(x) ((x) << 0)

439

#define FETCH_FIFO_HIWATER(x) ((x) << 8)

440

#define DONE_FIFO_HIWATER(x) ((x) << 16)

441

#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)

442

#define SQ_PGM_START_ES 0x28880

443

#define SQ_PGM_START_FS 0x28894

444

#define SQ_PGM_START_GS 0x2886C

445

#define SQ_PGM_START_PS 0x28840

446

#define SQ_PGM_RESOURCES_PS 0x28850

447

#define SQ_PGM_EXPORTS_PS 0x28854

448

#define SQ_PGM_CF_OFFSET_PS 0x288cc

449

#define SQ_PGM_START_VS 0x28858

450

#define SQ_PGM_RESOURCES_VS 0x28868

451

#define SQ_PGM_CF_OFFSET_VS 0x288d0

Ilija Hadzic

3a38612

2011-10-12 23:29:37 -0400

[diff] [blame]

452

453

#define SQ_VTX_CONSTANT_WORD0_0 0x30000

454

#define SQ_VTX_CONSTANT_WORD1_0 0x30004

455

#define SQ_VTX_CONSTANT_WORD2_0 0x30008

456

# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)

457

# define SQ_VTXC_STRIDE(x) ((x) << 8)

458

# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)

459

# define SQ_ENDIAN_NONE 0

460

# define SQ_ENDIAN_8IN16 1

461

# define SQ_ENDIAN_8IN32 2

462

#define SQ_VTX_CONSTANT_WORD3_0 0x3000c

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

463

#define SQ_VTX_CONSTANT_WORD6_0 0x38018

464

#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)

465

#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)

466

#define SQ_TEX_VTX_INVALID_TEXTURE 0x0

467

#define SQ_TEX_VTX_INVALID_BUFFER 0x1

468

#define SQ_TEX_VTX_VALID_TEXTURE 0x2

469

#define SQ_TEX_VTX_VALID_BUFFER 0x3

470

471

472

#define SX_MISC 0x28350

Alex Deucher

a39533b

2009-11-09 16:41:21 -0500

[diff] [blame]

473

#define SX_MEMORY_EXPORT_BASE 0x9010

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

474

#define SX_DEBUG_1 0x9054

475

#define SMX_EVENT_RELEASE (1 << 0)

476

#define ENABLE_NEW_SMX_ADDRESS (1 << 16)

477

478

#define TA_CNTL_AUX 0x9508

479

#define DISABLE_CUBE_WRAP (1 << 0)

480

#define DISABLE_CUBE_ANISO (1 << 1)

481

#define SYNC_GRADIENT (1 << 24)

482

#define SYNC_WALKER (1 << 25)

483

#define SYNC_ALIGNER (1 << 26)

484

#define BILINEAR_PRECISION_6_BIT (0 << 31)

485

#define BILINEAR_PRECISION_8_BIT (1 << 31)

486

487

#define TC_CNTL 0x9608

488

#define TC_L2_SIZE(x) ((x)<<5)

489

#define L2_DISABLE_LATE_HIT (1<<9)

490

Alex Deucher

b866d13

2012-06-14 22:06:36 +0200

[diff] [blame]

491

#define VC_ENHANCE 0x9714

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

492

493

#define VGT_CACHE_INVALIDATION 0x88C4

494

#define CACHE_INVALIDATION(x) ((x)<<0)

#define VC_ONLY 0

#define TC_ONLY 1

#define VC_AND_TC 2

#define VGT_DMA_BASE 0x287E8

499

#define VGT_DMA_BASE_HI 0x287E4

500

#define VGT_ES_PER_GS 0x88CC

501

#define VGT_GS_PER_ES 0x88C8

502

#define VGT_GS_PER_VS 0x88E8

503

#define VGT_GS_VERTEX_REUSE 0x88D4

504

#define VGT_PRIMITIVE_TYPE 0x8958

505

#define VGT_NUM_INSTANCES 0x8974

506

#define VGT_OUT_DEALLOC_CNTL 0x28C5C

507

#define DEALLOC_DIST_MASK 0x0000007F

508

#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10

509

#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14

510

#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18

511

#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c

512

#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44

513

#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48

514

#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c

515

#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50

516

#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8

517

#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8

518

#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8

519

#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08

520

#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC

521

#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC

522

#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC

523

#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

524

#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0

525

#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0

526

#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0

527

#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00

528

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

529

#define VGT_STRMOUT_EN 0x28AB0

530

#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58

531

#define VTX_REUSE_DEPTH_MASK 0x000000FF

532

#define VGT_EVENT_INITIATOR 0x28a90

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

533

# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

534

# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)

535

536

#define VM_CONTEXT0_CNTL 0x1410

537

#define ENABLE_CONTEXT (1 << 0)

538

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

539

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

540

#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490

541

#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0

542

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574

543

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594

544

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4

545

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554

546

#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470

547

#define REQUEST_TYPE(x) (((x) & 0xf) << 0)

548

#define RESPONSE_TYPE_MASK 0x000000F0

549

#define RESPONSE_TYPE_SHIFT 4

550

#define VM_L2_CNTL 0x1400

551

#define ENABLE_L2_CACHE (1 << 0)

552

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

553

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

554

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)

555

#define VM_L2_CNTL2 0x1404

556

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

557

#define INVALIDATE_L2_CACHE (1 << 1)

558

#define VM_L2_CNTL3 0x1408

559

#define BANK_SELECT_0(x) (((x) & 0x1f) << 0)

560

#define BANK_SELECT_1(x) (((x) & 0x1f) << 5)

561

#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)

562

#define VM_L2_STATUS 0x140C

563

#define L2_BUSY (1 << 0)

564

565

#define WAIT_UNTIL 0x8040

566

#define WAIT_2D_IDLE_bit (1 << 14)

567

#define WAIT_3D_IDLE_bit (1 << 15)

568

#define WAIT_2D_IDLECLEAN_bit (1 << 16)

569

#define WAIT_3D_IDLECLEAN_bit (1 << 17)

570

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

571

#define IH_RB_CNTL 0x3e00

572

# define IH_RB_ENABLE (1 << 0)

573

# define IH_IB_SIZE(x) ((x) << 1) /* log2 */

574

# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)

575

# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)

576

# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */

577

# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)

578

# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)

579

#define IH_RB_BASE 0x3e04

580

#define IH_RB_RPTR 0x3e08

581

#define IH_RB_WPTR 0x3e0c

582

# define RB_OVERFLOW (1 << 0)

583

# define WPTR_OFFSET_MASK 0x3fffc

584

#define IH_RB_WPTR_ADDR_HI 0x3e10

585

#define IH_RB_WPTR_ADDR_LO 0x3e14

586

#define IH_CNTL 0x3e18

587

# define ENABLE_INTR (1 << 0)

Alex Deucher

fcb857a

2011-07-06 19:52:27 +0000

[diff] [blame]

588

# define IH_MC_SWAP(x) ((x) << 1)

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

589

# define IH_MC_SWAP_NONE 0

590

# define IH_MC_SWAP_16BIT 1

591

# define IH_MC_SWAP_32BIT 2

592

# define IH_MC_SWAP_64BIT 3

593

# define RPTR_REARM (1 << 4)

594

# define MC_WRREQ_CREDIT(x) ((x) << 15)

595

# define MC_WR_CLEAN_CNT(x) ((x) << 20)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

596

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

597

#define RLC_CNTL 0x3f00

598

# define RLC_ENABLE (1 << 0)

599

#define RLC_HB_BASE 0x3f10

600

#define RLC_HB_CNTL 0x3f0c

601

#define RLC_HB_RPTR 0x3f20

602

#define RLC_HB_WPTR 0x3f1c

603

#define RLC_HB_WPTR_LSB_ADDR 0x3f14

604

#define RLC_HB_WPTR_MSB_ADDR 0x3f18

605

#define RLC_MC_CNTL 0x3f44

606

#define RLC_UCODE_CNTL 0x3f48

607

#define RLC_UCODE_ADDR 0x3f2c

608

#define RLC_UCODE_DATA 0x3f30

609

Alex Deucher

c420c74

2012-03-20 17:18:39 -0400

[diff] [blame]

610

/* new for TN */

611

#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10

612

#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20

613

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

614

#define SRBM_SOFT_RESET 0xe60

615

# define SOFT_RESET_RLC (1 << 13)

616

617

#define CP_INT_CNTL 0xc124

618

# define CNTX_BUSY_INT_ENABLE (1 << 19)

619

# define CNTX_EMPTY_INT_ENABLE (1 << 20)

620

# define SCRATCH_INT_ENABLE (1 << 25)

621

# define TIME_STAMP_INT_ENABLE (1 << 26)

622

# define IB2_INT_ENABLE (1 << 29)

623

# define IB1_INT_ENABLE (1 << 30)

624

# define RB_INT_ENABLE (1 << 31)

625

#define CP_INT_STATUS 0xc128

626

# define SCRATCH_INT_STAT (1 << 25)

627

# define TIME_STAMP_INT_STAT (1 << 26)

628

# define IB2_INT_STAT (1 << 29)

629

# define IB1_INT_STAT (1 << 30)

630

# define RB_INT_STAT (1 << 31)

631

632

#define GRBM_INT_CNTL 0x8060

633

# define RDERR_INT_ENABLE (1 << 0)

634

# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)

635

# define GUI_IDLE_INT_ENABLE (1 << 19)

636

637

#define INTERRUPT_CNTL 0x5468

638

# define IH_DUMMY_RD_OVERRIDE (1 << 0)

639

# define IH_DUMMY_RD_EN (1 << 1)

640

# define IH_REQ_NONSNOOP_EN (1 << 3)

641

# define GEN_IH_INT_EN (1 << 8)

642

#define INTERRUPT_CNTL2 0x546c

643

644

#define D1MODE_VBLANK_STATUS 0x6534

645

#define D2MODE_VBLANK_STATUS 0x6d34

646

# define DxMODE_VBLANK_OCCURRED (1 << 0)

647

# define DxMODE_VBLANK_ACK (1 << 4)

648

# define DxMODE_VBLANK_STAT (1 << 12)

649

# define DxMODE_VBLANK_INTERRUPT (1 << 16)

650

# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)

651

#define D1MODE_VLINE_STATUS 0x653c

652

#define D2MODE_VLINE_STATUS 0x6d3c

653

# define DxMODE_VLINE_OCCURRED (1 << 0)

654

# define DxMODE_VLINE_ACK (1 << 4)

655

# define DxMODE_VLINE_STAT (1 << 12)

656

# define DxMODE_VLINE_INTERRUPT (1 << 16)

657

# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)

658

#define DxMODE_INT_MASK 0x6540

659

# define D1MODE_VBLANK_INT_MASK (1 << 0)

660

# define D1MODE_VLINE_INT_MASK (1 << 4)

661

# define D2MODE_VBLANK_INT_MASK (1 << 8)

662

# define D2MODE_VLINE_INT_MASK (1 << 12)

663

#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc

664

# define DC_HPD1_INTERRUPT (1 << 18)

665

# define DC_HPD2_INTERRUPT (1 << 19)

666

#define DISP_INTERRUPT_STATUS 0x7edc

667

# define LB_D1_VLINE_INTERRUPT (1 << 2)

668

# define LB_D2_VLINE_INTERRUPT (1 << 3)

669

# define LB_D1_VBLANK_INTERRUPT (1 << 4)

670

# define LB_D2_VBLANK_INTERRUPT (1 << 5)

671

# define DACA_AUTODETECT_INTERRUPT (1 << 16)

672

# define DACB_AUTODETECT_INTERRUPT (1 << 17)

673

# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)

674

# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)

675

# define DC_I2C_SW_DONE_INTERRUPT (1 << 20)

676

# define DC_I2C_HW_DONE_INTERRUPT (1 << 21)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

677

#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

678

#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8

679

# define DC_HPD4_INTERRUPT (1 << 14)

680

# define DC_HPD4_RX_INTERRUPT (1 << 15)

681

# define DC_HPD3_INTERRUPT (1 << 28)

682

# define DC_HPD1_RX_INTERRUPT (1 << 29)

683

# define DC_HPD2_RX_INTERRUPT (1 << 30)

684

#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec

685

# define DC_HPD3_RX_INTERRUPT (1 << 0)

686

# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)

687

# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)

688

# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)

689

# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)

690

# define AUX1_SW_DONE_INTERRUPT (1 << 5)

691

# define AUX1_LS_DONE_INTERRUPT (1 << 6)

692

# define AUX2_SW_DONE_INTERRUPT (1 << 7)

693

# define AUX2_LS_DONE_INTERRUPT (1 << 8)

694

# define AUX3_SW_DONE_INTERRUPT (1 << 9)

695

# define AUX3_LS_DONE_INTERRUPT (1 << 10)

696

# define AUX4_SW_DONE_INTERRUPT (1 << 11)

697

# define AUX4_LS_DONE_INTERRUPT (1 << 12)

698

# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)

699

# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)

700

/* DCE 3.2 */

701

# define AUX5_SW_DONE_INTERRUPT (1 << 15)

702

# define AUX5_LS_DONE_INTERRUPT (1 << 16)

703

# define AUX6_SW_DONE_INTERRUPT (1 << 17)

704

# define AUX6_LS_DONE_INTERRUPT (1 << 18)

705

# define DC_HPD5_INTERRUPT (1 << 19)

706

# define DC_HPD5_RX_INTERRUPT (1 << 20)

707

# define DC_HPD6_INTERRUPT (1 << 21)

708

# define DC_HPD6_RX_INTERRUPT (1 << 22)

709

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

710

#define DACA_AUTO_DETECT_CONTROL 0x7828

711

#define DACB_AUTO_DETECT_CONTROL 0x7a28

712

#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028

713

#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128

714

# define DACx_AUTODETECT_MODE(x) ((x) << 0)

715

# define DACx_AUTODETECT_MODE_NONE 0

716

# define DACx_AUTODETECT_MODE_CONNECT 1

717

# define DACx_AUTODETECT_MODE_DISCONNECT 2

718

# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)

719

/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */

720

# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)

721

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

722

#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038

723

#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138

724

#define DACA_AUTODETECT_INT_CONTROL 0x7838

725

#define DACB_AUTODETECT_INT_CONTROL 0x7a38

726

# define DACx_AUTODETECT_ACK (1 << 0)

727

# define DACx_AUTODETECT_INT_ENABLE (1 << 16)

728

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

729

#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00

730

#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10

731

#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24

732

# define DC_HOT_PLUG_DETECTx_EN (1 << 0)

733

734

#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04

735

#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14

736

#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28

737

# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)

738

# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)

739

740

/* DCE 3.0 */

741

#define DC_HPD1_INT_STATUS 0x7d00

742

#define DC_HPD2_INT_STATUS 0x7d0c

743

#define DC_HPD3_INT_STATUS 0x7d18

744

#define DC_HPD4_INT_STATUS 0x7d24

745

/* DCE 3.2 */

746

#define DC_HPD5_INT_STATUS 0x7dc0

747

#define DC_HPD6_INT_STATUS 0x7df4

748

# define DC_HPDx_INT_STATUS (1 << 0)

749

# define DC_HPDx_SENSE (1 << 1)

750

# define DC_HPDx_RX_INT_STATUS (1 << 8)

751

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

752

#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08

753

#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18

754

#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c

755

# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)

756

# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)

757

# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

758

/* DCE 3.0 */

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

759

#define DC_HPD1_INT_CONTROL 0x7d04

760

#define DC_HPD2_INT_CONTROL 0x7d10

761

#define DC_HPD3_INT_CONTROL 0x7d1c

762

#define DC_HPD4_INT_CONTROL 0x7d28

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

763

/* DCE 3.2 */

764

#define DC_HPD5_INT_CONTROL 0x7dc4

765

#define DC_HPD6_INT_CONTROL 0x7df8

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

766

# define DC_HPDx_INT_ACK (1 << 0)

767

# define DC_HPDx_INT_POLARITY (1 << 8)

768

# define DC_HPDx_INT_EN (1 << 16)

769

# define DC_HPDx_RX_INT_ACK (1 << 20)

770

# define DC_HPDx_RX_INT_EN (1 << 24)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

771

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

772

/* DCE 3.0 */

773

#define DC_HPD1_CONTROL 0x7d08

774

#define DC_HPD2_CONTROL 0x7d14

775

#define DC_HPD3_CONTROL 0x7d20

776

#define DC_HPD4_CONTROL 0x7d2c

777

/* DCE 3.2 */

778

#define DC_HPD5_CONTROL 0x7dc8

779

#define DC_HPD6_CONTROL 0x7dfc

780

# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)

781

# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)

782

/* DCE 3.2 */

783

# define DC_HPDx_EN (1 << 28)

784

Alex Deucher

6f34be5

2010-11-21 10:59:01 -0500

[diff] [blame]

785

#define D1GRPH_INTERRUPT_STATUS 0x6158

786

#define D2GRPH_INTERRUPT_STATUS 0x6958

787

# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)

788

# define DxGRPH_PFLIP_INT_CLEAR (1 << 8)

789

#define D1GRPH_INTERRUPT_CONTROL 0x615c

790

#define D2GRPH_INTERRUPT_CONTROL 0x695c

791

# define DxGRPH_PFLIP_INT_MASK (1 << 0)

792

# define DxGRPH_PFLIP_INT_TYPE (1 << 8)

793

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

794

/* PCIE link stuff */

795

#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */

796

# define LC_POINT_7_PLUS_EN (1 << 6)

797

#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */

798

# define LC_LINK_WIDTH_SHIFT 0

799

# define LC_LINK_WIDTH_MASK 0x7

800

# define LC_LINK_WIDTH_X0 0

801

# define LC_LINK_WIDTH_X1 1

802

# define LC_LINK_WIDTH_X2 2

803

# define LC_LINK_WIDTH_X4 3

804

# define LC_LINK_WIDTH_X8 4

805

# define LC_LINK_WIDTH_X16 6

806

# define LC_LINK_WIDTH_RD_SHIFT 4

807

# define LC_LINK_WIDTH_RD_MASK 0x70

808

# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

809

# define LC_RECONFIG_NOW (1 << 8)

810

# define LC_RENEGOTIATION_SUPPORT (1 << 9)

811

# define LC_RENEGOTIATE_EN (1 << 10)

812

# define LC_SHORT_RECONFIG_EN (1 << 11)

813

# define LC_UPCONFIGURE_SUPPORT (1 << 12)

814

# define LC_UPCONFIGURE_DIS (1 << 13)

815

#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */

816

# define LC_GEN2_EN_STRAP (1 << 0)

817

# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)

818

# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)

819

# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)

820

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)

821

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3

822

# define LC_CURRENT_DATA_RATE (1 << 11)

823

# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)

824

# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)

825

# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)

826

# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)

827

#define MM_CFGREGS_CNTL 0x544c

828

# define MM_WR_TO_CFG_EN (1 << 3)

829

#define LINK_CNTL2 0x88 /* F0 */

830

# define TARGET_LINK_SPEED_MASK (0xf << 0)

831

# define SELECTABLE_DEEMPHASIS (1 << 6)

832

Alex Deucher

3a2a67a

2012-03-28 13:19:06 -0400

[diff] [blame]

833

/* Audio clocks */

834

#define DCCG_AUDIO_DTO0_PHASE 0x0514

835

#define DCCG_AUDIO_DTO0_MODULE 0x0518

836

#define DCCG_AUDIO_DTO0_LOAD 0x051c

837

# define DTO_LOAD (1 << 31)

838

#define DCCG_AUDIO_DTO0_CNTL 0x0520

839

840

#define DCCG_AUDIO_DTO1_PHASE 0x0524

841

#define DCCG_AUDIO_DTO1_MODULE 0x0528

842

#define DCCG_AUDIO_DTO1_LOAD 0x052c

843

#define DCCG_AUDIO_DTO1_CNTL 0x0530

844

845

#define DCCG_AUDIO_DTO_SELECT 0x0534

846

847

/* digital blocks */

848

#define TMDSA_CNTL 0x7880

849

# define TMDSA_HDMI_EN (1 << 2)

850

#define LVTMA_CNTL 0x7a80

851

# define LVTMA_HDMI_EN (1 << 2)

852

#define DDIA_CNTL 0x7200

853

# define DDIA_HDMI_EN (1 << 2)

854

#define DIG0_CNTL 0x75a0

855

# define DIG_MODE(x) (((x) & 7) << 8)

856

# define DIG_MODE_DP 0

857

# define DIG_MODE_LVDS 1

858

# define DIG_MODE_TMDS_DVI 2

859

# define DIG_MODE_TMDS_HDMI 3

860

# define DIG_MODE_SDVO 4

861

#define DIG1_CNTL 0x79a0

862

863

/* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one

864

* instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly

865

* different due to the new DIG blocks, but also have 2 instances.

866

* DCE 3.0 HDMI blocks are part of each DIG encoder.

867

*/

868

869

/* rs6xx/rs740/r6xx/dce3 */

870

#define HDMI0_CONTROL 0x7400

871

/* rs6xx/rs740/r6xx */

872

# define HDMI0_ENABLE (1 << 0)

873

# define HDMI0_STREAM(x) (((x) & 3) << 2)

874

# define HDMI0_STREAM_TMDSA 0

875

# define HDMI0_STREAM_LVTMA 1

876

# define HDMI0_STREAM_DVOA 2

877

# define HDMI0_STREAM_DDIA 3

878

/* rs6xx/r6xx/dce3 */

879

# define HDMI0_ERROR_ACK (1 << 8)

880

# define HDMI0_ERROR_MASK (1 << 9)

881

#define HDMI0_STATUS 0x7404

882

# define HDMI0_ACTIVE_AVMUTE (1 << 0)

883

# define HDMI0_AUDIO_ENABLE (1 << 4)

884

# define HDMI0_AZ_FORMAT_WTRIG (1 << 28)

885

# define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)

886

#define HDMI0_AUDIO_PACKET_CONTROL 0x7408

887

# define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)

888

# define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)

889

# define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)

890

# define HDMI0_AUDIO_TEST_EN (1 << 12)

891

# define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)

892

# define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)

893

# define HDMI0_60958_CS_UPDATE (1 << 26)

894

# define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)

895

# define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29)

896

#define HDMI0_AUDIO_CRC_CONTROL 0x740c

897

# define HDMI0_AUDIO_CRC_EN (1 << 0)

898

#define HDMI0_VBI_PACKET_CONTROL 0x7410

899

# define HDMI0_NULL_SEND (1 << 0)

900

# define HDMI0_GC_SEND (1 << 4)

901

# define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */

902

#define HDMI0_INFOFRAME_CONTROL0 0x7414

903

# define HDMI0_AVI_INFO_SEND (1 << 0)

904

# define HDMI0_AVI_INFO_CONT (1 << 1)

905

# define HDMI0_AUDIO_INFO_SEND (1 << 4)

906

# define HDMI0_AUDIO_INFO_CONT (1 << 5)

907

# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */

908

# define HDMI0_AUDIO_INFO_UPDATE (1 << 7)

909

# define HDMI0_MPEG_INFO_SEND (1 << 8)

910

# define HDMI0_MPEG_INFO_CONT (1 << 9)

911

# define HDMI0_MPEG_INFO_UPDATE (1 << 10)

912

#define HDMI0_INFOFRAME_CONTROL1 0x7418

913

# define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)

914

# define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)

915

# define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)

916

#define HDMI0_GENERIC_PACKET_CONTROL 0x741c

917

# define HDMI0_GENERIC0_SEND (1 << 0)

918

# define HDMI0_GENERIC0_CONT (1 << 1)

919

# define HDMI0_GENERIC0_UPDATE (1 << 2)

920

# define HDMI0_GENERIC1_SEND (1 << 4)

921

# define HDMI0_GENERIC1_CONT (1 << 5)

922

# define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)

923

# define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)

924

#define HDMI0_GC 0x7428

925

# define HDMI0_GC_AVMUTE (1 << 0)

926

#define HDMI0_AVI_INFO0 0x7454

927

# define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

928

# define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8)

929

# define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10)

930

# define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12)

931

# define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13)

932

# define HDMI0_AVI_INFO_Y_RGB 0

933

# define HDMI0_AVI_INFO_Y_YCBCR422 1

934

# define HDMI0_AVI_INFO_Y_YCBCR444 2

935

# define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)

936

# define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16)

937

# define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20)

938

# define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22)

939

# define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)

940

# define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24)

941

# define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)

942

#define HDMI0_AVI_INFO1 0x7458

943

# define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */

944

# define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */

945

# define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)

946

#define HDMI0_AVI_INFO2 0x745c

947

# define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)

948

# define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)

949

#define HDMI0_AVI_INFO3 0x7460

950

# define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)

951

# define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24)

952

#define HDMI0_MPEG_INFO0 0x7464

953

# define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

954

# define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)

955

# define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)

956

# define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)

957

#define HDMI0_MPEG_INFO1 0x7468

958

# define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)

959

# define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8)

960

# define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12)

961

#define HDMI0_GENERIC0_HDR 0x746c

962

#define HDMI0_GENERIC0_0 0x7470

963

#define HDMI0_GENERIC0_1 0x7474

964

#define HDMI0_GENERIC0_2 0x7478

965

#define HDMI0_GENERIC0_3 0x747c

966

#define HDMI0_GENERIC0_4 0x7480

967

#define HDMI0_GENERIC0_5 0x7484

968

#define HDMI0_GENERIC0_6 0x7488

969

#define HDMI0_GENERIC1_HDR 0x748c

970

#define HDMI0_GENERIC1_0 0x7490

971

#define HDMI0_GENERIC1_1 0x7494

972

#define HDMI0_GENERIC1_2 0x7498

973

#define HDMI0_GENERIC1_3 0x749c

974

#define HDMI0_GENERIC1_4 0x74a0

975

#define HDMI0_GENERIC1_5 0x74a4

976

#define HDMI0_GENERIC1_6 0x74a8

977

#define HDMI0_ACR_32_0 0x74ac

978

# define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)

979

#define HDMI0_ACR_32_1 0x74b0

980

# define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)

981

#define HDMI0_ACR_44_0 0x74b4

982

# define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)

983

#define HDMI0_ACR_44_1 0x74b8

984

# define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)

985

#define HDMI0_ACR_48_0 0x74bc

986

# define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)

987

#define HDMI0_ACR_48_1 0x74c0

988

# define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)

989

#define HDMI0_ACR_STATUS_0 0x74c4

990

#define HDMI0_ACR_STATUS_1 0x74c8

991

#define HDMI0_AUDIO_INFO0 0x74cc

992

# define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

993

# define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8)

994

#define HDMI0_AUDIO_INFO1 0x74d0

995

# define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)

996

# define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)

997

# define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)

998

# define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)

999

#define HDMI0_60958_0 0x74d4

1000

# define HDMI0_60958_CS_A(x) (((x) & 1) << 0)

1001

# define HDMI0_60958_CS_B(x) (((x) & 1) << 1)

1002

# define HDMI0_60958_CS_C(x) (((x) & 1) << 2)

1003

# define HDMI0_60958_CS_D(x) (((x) & 3) << 3)

1004

# define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6)

1005

# define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)

1006

# define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)

1007

# define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)

1008

# define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)

1009

# define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)

1010

#define HDMI0_60958_1 0x74d8

1011

# define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)

1012

# define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)

1013

# define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)

1014

# define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)

1015

# define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)

1016

#define HDMI0_ACR_PACKET_CONTROL 0x74dc

1017

# define HDMI0_ACR_SEND (1 << 0)

1018

# define HDMI0_ACR_CONT (1 << 1)

1019

# define HDMI0_ACR_SELECT(x) (((x) & 3) << 4)

1020

# define HDMI0_ACR_HW 0

1021

# define HDMI0_ACR_32 1

1022

# define HDMI0_ACR_44 2

1023

# define HDMI0_ACR_48 3

1024

# define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */

1025

# define HDMI0_ACR_AUTO_SEND (1 << 12)

1026

#define HDMI0_RAMP_CONTROL0 0x74e0

1027

# define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)

1028

#define HDMI0_RAMP_CONTROL1 0x74e4

1029

# define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)

1030

#define HDMI0_RAMP_CONTROL2 0x74e8

1031

# define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)

1032

#define HDMI0_RAMP_CONTROL3 0x74ec

1033

# define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)

1034

/* HDMI0_60958_2 is r7xx only */

1035

#define HDMI0_60958_2 0x74f0

1036

# define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)

1037

# define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)

1038

# define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)

1039

# define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)

1040

# define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)

1041

# define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)

1042

/* r6xx only; second instance starts at 0x7700 */

1043

#define HDMI1_CONTROL 0x7700

1044

#define HDMI1_STATUS 0x7704

1045

#define HDMI1_AUDIO_PACKET_CONTROL 0x7708

1046

/* DCE3; second instance starts at 0x7800 NOT 0x7700 */

1047

#define DCE3_HDMI1_CONTROL 0x7800

1048

#define DCE3_HDMI1_STATUS 0x7804

1049

#define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808

1050

/* DCE3.2 (for interrupts) */

1051

#define AFMT_STATUS 0x7600

1052

# define AFMT_AUDIO_ENABLE (1 << 4)

1053

# define AFMT_AZ_FORMAT_WTRIG (1 << 28)

1054

# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)

1055

# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)

1056

#define AFMT_AUDIO_PACKET_CONTROL 0x7604

1057

# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)

1058

# define AFMT_AUDIO_TEST_EN (1 << 12)

1059

# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)

1060

# define AFMT_60958_CS_UPDATE (1 << 26)

1061

# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)

1062

# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)

1063

# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)

1064

# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)

Rafał Miłecki

c6543a6

2012-04-28 23:35:24 +0200

[diff] [blame]

1065

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

/*

* PM4

*/

#define PACKET_TYPE0 0

1070

#define PACKET_TYPE1 1

1071

#define PACKET_TYPE2 2

1072

#define PACKET_TYPE3 3

1073

1074

#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)

1075

#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)

1076

#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)

1077

#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)

1078

#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \

1079

(((reg) >> 2) & 0xFFFF) | \

1080

((n) & 0x3FFF) << 16)

1081

#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \

1082

(((op) & 0xFF) << 8) | \

1083

((n) & 0x3FFF) << 16)

1084

1085

/* Packet 3 types */

1086

#define PACKET3_NOP 0x10

1087

#define PACKET3_INDIRECT_BUFFER_END 0x17

1088

#define PACKET3_SET_PREDICATION 0x20

1089

#define PACKET3_REG_RMW 0x21

1090

#define PACKET3_COND_EXEC 0x22

1091

#define PACKET3_PRED_EXEC 0x23

1092

#define PACKET3_START_3D_CMDBUF 0x24

1093

#define PACKET3_DRAW_INDEX_2 0x27

1094

#define PACKET3_CONTEXT_CONTROL 0x28

1095

#define PACKET3_DRAW_INDEX_IMMD_BE 0x29

1096

#define PACKET3_INDEX_TYPE 0x2A

1097

#define PACKET3_DRAW_INDEX 0x2B

1098

#define PACKET3_DRAW_INDEX_AUTO 0x2D

1099

#define PACKET3_DRAW_INDEX_IMMD 0x2E

1100

#define PACKET3_NUM_INSTANCES 0x2F

1101

#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34

1102

#define PACKET3_INDIRECT_BUFFER_MP 0x38

1103

#define PACKET3_MEM_SEMAPHORE 0x39

Christian König

0be7043

2012-03-07 11:28:57 +0100

[diff] [blame]

1104

# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)

Christian König

15d3332

2011-09-15 19:02:22 +0200

[diff] [blame]

1105

# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)

1106

# define PACKET3_SEM_SEL_WAIT (0x7 << 29)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1107

#define PACKET3_MPEG_INDEX 0x3A

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

1108

#define PACKET3_COPY_DW 0x3B

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1109

#define PACKET3_WAIT_REG_MEM 0x3C

1110

#define PACKET3_MEM_WRITE 0x3D

1111

#define PACKET3_INDIRECT_BUFFER 0x32

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1112

#define PACKET3_SURFACE_SYNC 0x43

1113

# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)

1114

# define PACKET3_TC_ACTION_ENA (1 << 23)

1115

# define PACKET3_VC_ACTION_ENA (1 << 24)

1116

# define PACKET3_CB_ACTION_ENA (1 << 25)

1117

# define PACKET3_DB_ACTION_ENA (1 << 26)

1118

# define PACKET3_SH_ACTION_ENA (1 << 27)

1119

# define PACKET3_SMX_ACTION_ENA (1 << 28)

1120

#define PACKET3_ME_INITIALIZE 0x44

1121

#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

1122

#define PACKET3_COND_WRITE 0x45

1123

#define PACKET3_EVENT_WRITE 0x46

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

1124

#define EVENT_TYPE(x) ((x) << 0)

1125

#define EVENT_INDEX(x) ((x) << 8)

1126

/* 0 - any non-TS event

1127

* 1 - ZPASS_DONE

1128

* 2 - SAMPLE_PIPELINESTAT

1129

* 3 - SAMPLE_STREAMOUTSTAT*

1130

* 4 - *S_PARTIAL_FLUSH

1131

* 5 - TS events

1132

*/

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1133

#define PACKET3_EVENT_WRITE_EOP 0x47

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

1134

#define DATA_SEL(x) ((x) << 29)

1135

/* 0 - discard

1136

* 1 - send low 32bit data

1137

* 2 - send 64bit data

1138

* 3 - send 64bit counter value

1139

*/

1140

#define INT_SEL(x) ((x) << 24)

1141

/* 0 - none

1142

* 1 - interrupt only (DATA_SEL = 0)

1143

* 2 - interrupt when data write is confirmed

1144

*/

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1145

#define PACKET3_ONE_REG_WRITE 0x57

1146

#define PACKET3_SET_CONFIG_REG 0x68

1147

#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000

1148

#define PACKET3_SET_CONFIG_REG_END 0x0000ac00

1149

#define PACKET3_SET_CONTEXT_REG 0x69

1150

#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000

1151

#define PACKET3_SET_CONTEXT_REG_END 0x00029000

1152

#define PACKET3_SET_ALU_CONST 0x6A

1153

#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000

1154

#define PACKET3_SET_ALU_CONST_END 0x00032000

1155

#define PACKET3_SET_BOOL_CONST 0x6B

1156

#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380

1157

#define PACKET3_SET_BOOL_CONST_END 0x00040000

1158

#define PACKET3_SET_LOOP_CONST 0x6C

1159

#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200

1160

#define PACKET3_SET_LOOP_CONST_END 0x0003e380

1161

#define PACKET3_SET_RESOURCE 0x6D

1162

#define PACKET3_SET_RESOURCE_OFFSET 0x00038000

1163

#define PACKET3_SET_RESOURCE_END 0x0003c000

1164

#define PACKET3_SET_SAMPLER 0x6E

1165

#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000

1166

#define PACKET3_SET_SAMPLER_END 0x0003cff0

1167

#define PACKET3_SET_CTL_CONST 0x6F

1168

#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0

1169

#define PACKET3_SET_CTL_CONST_END 0x0003e200

Alex Deucher

7c77bf2

2012-06-14 22:06:37 +0200

[diff] [blame]

1170

#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1171

#define PACKET3_SURFACE_BASE_UPDATE 0x73

1172

1173

1174

#define R_008020_GRBM_SOFT_RESET 0x8020

1175

#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)

1176

#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)

1177

#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)

1178

#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)

1179

#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)

1180

#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)

1181

#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)

1182

#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)

1183

#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)

1184

#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)

1185

#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)

1186

#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)

1187

#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)

1188

#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)

1189

#define R_008010_GRBM_STATUS 0x8010

1190

#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)

1191

#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)

1192

#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)

1193

#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)

1194

#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)

1195

#define S_008010_VC_BUSY(x) (((x) & 1) << 11)

1196

#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)

1197

#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)

1198

#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)

1199

#define S_008010_VGT_BUSY(x) (((x) & 1) << 17)

1200

#define S_008010_TA03_BUSY(x) (((x) & 1) << 18)

1201

#define S_008010_TC_BUSY(x) (((x) & 1) << 19)

1202

#define S_008010_SX_BUSY(x) (((x) & 1) << 20)

1203

#define S_008010_SH_BUSY(x) (((x) & 1) << 21)

1204

#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)

1205

#define S_008010_SMX_BUSY(x) (((x) & 1) << 23)

1206

#define S_008010_SC_BUSY(x) (((x) & 1) << 24)

1207

#define S_008010_PA_BUSY(x) (((x) & 1) << 25)

1208

#define S_008010_DB03_BUSY(x) (((x) & 1) << 26)

1209

#define S_008010_CR_BUSY(x) (((x) & 1) << 27)

1210

#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)

1211

#define S_008010_CP_BUSY(x) (((x) & 1) << 29)

1212

#define S_008010_CB03_BUSY(x) (((x) & 1) << 30)

1213

#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)

1214

#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)

1215

#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)

1216

#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)

1217

#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)

1218

#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)

1219

#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)

1220

#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)

1221

#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)

1222

#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)

1223

#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)

1224

#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)

1225

#define G_008010_TC_BUSY(x) (((x) >> 19) & 1)

1226

#define G_008010_SX_BUSY(x) (((x) >> 20) & 1)

1227

#define G_008010_SH_BUSY(x) (((x) >> 21) & 1)

1228

#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)

1229

#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)

1230

#define G_008010_SC_BUSY(x) (((x) >> 24) & 1)

1231

#define G_008010_PA_BUSY(x) (((x) >> 25) & 1)

1232

#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)

1233

#define G_008010_CR_BUSY(x) (((x) >> 27) & 1)

1234

#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)

1235

#define G_008010_CP_BUSY(x) (((x) >> 29) & 1)

1236

#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)

1237

#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)

1238

#define R_008014_GRBM_STATUS2 0x8014

1239

#define S_008014_CR_CLEAN(x) (((x) & 1) << 0)

1240

#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)

1241

#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)

1242

#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)

1243

#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)

1244

#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)

1245

#define S_008014_TA0_BUSY(x) (((x) & 1) << 12)

1246

#define S_008014_TA1_BUSY(x) (((x) & 1) << 13)

1247

#define S_008014_TA2_BUSY(x) (((x) & 1) << 14)

1248

#define S_008014_TA3_BUSY(x) (((x) & 1) << 15)

1249

#define S_008014_DB0_BUSY(x) (((x) & 1) << 16)

1250

#define S_008014_DB1_BUSY(x) (((x) & 1) << 17)

1251

#define S_008014_DB2_BUSY(x) (((x) & 1) << 18)

1252

#define S_008014_DB3_BUSY(x) (((x) & 1) << 19)

1253

#define S_008014_CB0_BUSY(x) (((x) & 1) << 20)

1254

#define S_008014_CB1_BUSY(x) (((x) & 1) << 21)

1255

#define S_008014_CB2_BUSY(x) (((x) & 1) << 22)

1256

#define S_008014_CB3_BUSY(x) (((x) & 1) << 23)

1257

#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)

1258

#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)

1259

#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)

1260

#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)

1261

#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)

1262

#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)

1263

#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)

1264

#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)

1265

#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)

1266

#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)

1267

#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)

1268

#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)

1269

#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)

1270

#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)

1271

#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)

1272

#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)

1273

#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)

1274

#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)

1275

#define R_000E50_SRBM_STATUS 0x0E50

1276

#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)

1277

#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)

1278

#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)

1279

#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)

1280

#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)

1281

#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)

1282

#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)

1283

#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)

1284

#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)

1285

#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)

1286

#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)

1287

#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)

1288

#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)

Jerome Glisse

1a029b7

2009-10-06 19:04:30 +0200

[diff] [blame]

1289

#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1290

#define R_000E60_SRBM_SOFT_RESET 0x0E60

1291

#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)

1292

#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)

1293

#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)

1294

#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)

1295

#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)

1296

#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)

1297

#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)

1298

#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)

1299

#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)

1300

#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)

1301

#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)

1302

#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)

1303

#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)

1304

#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)

1305

Dave Airlie

23956df

2009-11-23 12:01:09 +1000

[diff] [blame]

1306

#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1307

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1308

#define R_028C04_PA_SC_AA_CONFIG 0x028C04

1309

#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)

1310

#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)

1311

#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC

1312

#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)

1313

#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)

1314

#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF

1315

#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)

1316

#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)

1317

#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1318

#define R_0280E0_CB_COLOR0_FRAG 0x0280E0

1319

#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)

1320

#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)

1321

#define C_0280E0_BASE_256B 0x00000000

1322

#define R_0280E4_CB_COLOR1_FRAG 0x0280E4

1323

#define R_0280E8_CB_COLOR2_FRAG 0x0280E8

1324

#define R_0280EC_CB_COLOR3_FRAG 0x0280EC

1325

#define R_0280F0_CB_COLOR4_FRAG 0x0280F0

1326

#define R_0280F4_CB_COLOR5_FRAG 0x0280F4

1327

#define R_0280F8_CB_COLOR6_FRAG 0x0280F8

1328

#define R_0280FC_CB_COLOR7_FRAG 0x0280FC

1329

#define R_0280C0_CB_COLOR0_TILE 0x0280C0

1330

#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)

1331

#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)

1332

#define C_0280C0_BASE_256B 0x00000000

1333

#define R_0280C4_CB_COLOR1_TILE 0x0280C4

1334

#define R_0280C8_CB_COLOR2_TILE 0x0280C8

1335

#define R_0280CC_CB_COLOR3_TILE 0x0280CC

1336

#define R_0280D0_CB_COLOR4_TILE 0x0280D0

1337

#define R_0280D4_CB_COLOR5_TILE 0x0280D4

1338

#define R_0280D8_CB_COLOR6_TILE 0x0280D8

1339

#define R_0280DC_CB_COLOR7_TILE 0x0280DC

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1340

#define R_0280A0_CB_COLOR0_INFO 0x0280A0

1341

#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)

1342

#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)

1343

#define C_0280A0_ENDIAN 0xFFFFFFFC

1344

#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)

1345

#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)

1346

#define C_0280A0_FORMAT 0xFFFFFF03

1347

#define V_0280A0_COLOR_INVALID 0x00000000

1348

#define V_0280A0_COLOR_8 0x00000001

1349

#define V_0280A0_COLOR_4_4 0x00000002

1350

#define V_0280A0_COLOR_3_3_2 0x00000003

1351

#define V_0280A0_COLOR_16 0x00000005

1352

#define V_0280A0_COLOR_16_FLOAT 0x00000006

1353

#define V_0280A0_COLOR_8_8 0x00000007

1354

#define V_0280A0_COLOR_5_6_5 0x00000008

1355

#define V_0280A0_COLOR_6_5_5 0x00000009

1356

#define V_0280A0_COLOR_1_5_5_5 0x0000000A

1357

#define V_0280A0_COLOR_4_4_4_4 0x0000000B

1358

#define V_0280A0_COLOR_5_5_5_1 0x0000000C

1359

#define V_0280A0_COLOR_32 0x0000000D

1360

#define V_0280A0_COLOR_32_FLOAT 0x0000000E

1361

#define V_0280A0_COLOR_16_16 0x0000000F

1362

#define V_0280A0_COLOR_16_16_FLOAT 0x00000010

1363

#define V_0280A0_COLOR_8_24 0x00000011

1364

#define V_0280A0_COLOR_8_24_FLOAT 0x00000012

1365

#define V_0280A0_COLOR_24_8 0x00000013

1366

#define V_0280A0_COLOR_24_8_FLOAT 0x00000014

1367

#define V_0280A0_COLOR_10_11_11 0x00000015

1368

#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016

1369

#define V_0280A0_COLOR_11_11_10 0x00000017

1370

#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018

1371

#define V_0280A0_COLOR_2_10_10_10 0x00000019

1372

#define V_0280A0_COLOR_8_8_8_8 0x0000001A

1373

#define V_0280A0_COLOR_10_10_10_2 0x0000001B

1374

#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C

1375

#define V_0280A0_COLOR_32_32 0x0000001D

1376

#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E

1377

#define V_0280A0_COLOR_16_16_16_16 0x0000001F

1378

#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020

1379

#define V_0280A0_COLOR_32_32_32_32 0x00000022

1380

#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023

1381

#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)

1382

#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)

1383

#define C_0280A0_ARRAY_MODE 0xFFFFF0FF

1384

#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000

1385

#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001

1386

#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002

1387

#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004

1388

#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)

1389

#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)

1390

#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF

1391

#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)

1392

#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)

1393

#define C_0280A0_READ_SIZE 0xFFFF7FFF

1394

#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)

1395

#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)

1396

#define C_0280A0_COMP_SWAP 0xFFFCFFFF

1397

#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)

1398

#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)

1399

#define C_0280A0_TILE_MODE 0xFFF3FFFF

1400

#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)

1401

#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)

1402

#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF

1403

#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)

1404

#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)

1405

#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF

1406

#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)

1407

#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)

1408

#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF

1409

#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)

1410

#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)

1411

#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF

1412

#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)

1413

#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)

1414

#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF

1415

#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)

1416

#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)

1417

#define C_0280A0_ROUND_MODE 0xFDFFFFFF

1418

#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)

1419

#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)

1420

#define C_0280A0_TILE_COMPACT 0xFBFFFFFF

1421

#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)

1422

#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)

1423

#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF

1424

#define R_0280A4_CB_COLOR1_INFO 0x0280A4

1425

#define R_0280A8_CB_COLOR2_INFO 0x0280A8

1426

#define R_0280AC_CB_COLOR3_INFO 0x0280AC

1427

#define R_0280B0_CB_COLOR4_INFO 0x0280B0

1428

#define R_0280B4_CB_COLOR5_INFO 0x0280B4

1429

#define R_0280B8_CB_COLOR6_INFO 0x0280B8

1430

#define R_0280BC_CB_COLOR7_INFO 0x0280BC

1431

#define R_028060_CB_COLOR0_SIZE 0x028060

1432

#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)

1433

#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)

1434

#define C_028060_PITCH_TILE_MAX 0xFFFFFC00

1435

#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)

1436

#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)

1437

#define C_028060_SLICE_TILE_MAX 0xC00003FF

1438

#define R_028064_CB_COLOR1_SIZE 0x028064

1439

#define R_028068_CB_COLOR2_SIZE 0x028068

1440

#define R_02806C_CB_COLOR3_SIZE 0x02806C

1441

#define R_028070_CB_COLOR4_SIZE 0x028070

1442

#define R_028074_CB_COLOR5_SIZE 0x028074

1443

#define R_028078_CB_COLOR6_SIZE 0x028078

1444

#define R_02807C_CB_COLOR7_SIZE 0x02807C

1445

#define R_028238_CB_TARGET_MASK 0x028238

1446

#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)

1447

#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)

1448

#define C_028238_TARGET0_ENABLE 0xFFFFFFF0

1449

#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)

1450

#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)

1451

#define C_028238_TARGET1_ENABLE 0xFFFFFF0F

1452

#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)

1453

#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)

1454

#define C_028238_TARGET2_ENABLE 0xFFFFF0FF

1455

#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)

1456

#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)

1457

#define C_028238_TARGET3_ENABLE 0xFFFF0FFF

1458

#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)

1459

#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)

1460

#define C_028238_TARGET4_ENABLE 0xFFF0FFFF

1461

#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)

1462

#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)

1463

#define C_028238_TARGET5_ENABLE 0xFF0FFFFF

1464

#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)

1465

#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)

1466

#define C_028238_TARGET6_ENABLE 0xF0FFFFFF

1467

#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)

1468

#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)

1469

#define C_028238_TARGET7_ENABLE 0x0FFFFFFF

1470

#define R_02823C_CB_SHADER_MASK 0x02823C

1471

#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)

1472

#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)

1473

#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0

1474

#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)

1475

#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)

1476

#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F

1477

#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)

1478

#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)

1479

#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF

1480

#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)

1481

#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)

1482

#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF

1483

#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)

1484

#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)

1485

#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF

1486

#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)

1487

#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)

1488

#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF

1489

#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)

1490

#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)

1491

#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF

1492

#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)

1493

#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)

1494

#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF

1495

#define R_028AB0_VGT_STRMOUT_EN 0x028AB0

1496

#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)

1497

#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)

1498

#define C_028AB0_STREAMOUT 0xFFFFFFFE

1499

#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20

1500

#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)

1501

#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)

1502

#define C_028B20_BUFFER_0_EN 0xFFFFFFFE

1503

#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)

1504

#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)

1505

#define C_028B20_BUFFER_1_EN 0xFFFFFFFD

1506

#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)

1507

#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)

1508

#define C_028B20_BUFFER_2_EN 0xFFFFFFFB

1509

#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)

1510

#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)

1511

#define C_028B20_BUFFER_3_EN 0xFFFFFFF7

1512

#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1513

#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1514

#define C_028B20_SIZE 0x00000000

1515

#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000

1516

#define S_038000_DIM(x) (((x) & 0x7) << 0)

1517

#define G_038000_DIM(x) (((x) >> 0) & 0x7)

1518

#define C_038000_DIM 0xFFFFFFF8

1519

#define V_038000_SQ_TEX_DIM_1D 0x00000000

1520

#define V_038000_SQ_TEX_DIM_2D 0x00000001

1521

#define V_038000_SQ_TEX_DIM_3D 0x00000002

1522

#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003

1523

#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004

1524

#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005

1525

#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006

1526

#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007

1527

#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)

1528

#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)

1529

#define C_038000_TILE_MODE 0xFFFFFF87

Alex Deucher

7f81337

2010-05-20 12:43:52 -0400

[diff] [blame]

1530

#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000

1531

#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001

1532

#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002

1533

#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1534

#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)

1535

#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)

1536

#define C_038000_TILE_TYPE 0xFFFFFF7F

1537

#define S_038000_PITCH(x) (((x) & 0x7FF) << 8)

1538

#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)

1539

#define C_038000_PITCH 0xFFF800FF

1540

#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)

1541

#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)

1542

#define C_038000_TEX_WIDTH 0x0007FFFF

1543

#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004

1544

#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)

1545

#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)

1546

#define C_038004_TEX_HEIGHT 0xFFFFE000

1547

#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)

1548

#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)

1549

#define C_038004_TEX_DEPTH 0xFC001FFF

1550

#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)

1551

#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)

1552

#define C_038004_DATA_FORMAT 0x03FFFFFF

1553

#define V_038004_COLOR_INVALID 0x00000000

1554

#define V_038004_COLOR_8 0x00000001

1555

#define V_038004_COLOR_4_4 0x00000002

1556

#define V_038004_COLOR_3_3_2 0x00000003

1557

#define V_038004_COLOR_16 0x00000005

1558

#define V_038004_COLOR_16_FLOAT 0x00000006

1559

#define V_038004_COLOR_8_8 0x00000007

1560

#define V_038004_COLOR_5_6_5 0x00000008

1561

#define V_038004_COLOR_6_5_5 0x00000009

1562

#define V_038004_COLOR_1_5_5_5 0x0000000A

1563

#define V_038004_COLOR_4_4_4_4 0x0000000B

1564

#define V_038004_COLOR_5_5_5_1 0x0000000C

1565

#define V_038004_COLOR_32 0x0000000D

1566

#define V_038004_COLOR_32_FLOAT 0x0000000E

1567

#define V_038004_COLOR_16_16 0x0000000F

1568

#define V_038004_COLOR_16_16_FLOAT 0x00000010

1569

#define V_038004_COLOR_8_24 0x00000011

1570

#define V_038004_COLOR_8_24_FLOAT 0x00000012

1571

#define V_038004_COLOR_24_8 0x00000013

1572

#define V_038004_COLOR_24_8_FLOAT 0x00000014

1573

#define V_038004_COLOR_10_11_11 0x00000015

1574

#define V_038004_COLOR_10_11_11_FLOAT 0x00000016

1575

#define V_038004_COLOR_11_11_10 0x00000017

1576

#define V_038004_COLOR_11_11_10_FLOAT 0x00000018

1577

#define V_038004_COLOR_2_10_10_10 0x00000019

1578

#define V_038004_COLOR_8_8_8_8 0x0000001A

1579

#define V_038004_COLOR_10_10_10_2 0x0000001B

1580

#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C

1581

#define V_038004_COLOR_32_32 0x0000001D

1582

#define V_038004_COLOR_32_32_FLOAT 0x0000001E

1583

#define V_038004_COLOR_16_16_16_16 0x0000001F

1584

#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020

1585

#define V_038004_COLOR_32_32_32_32 0x00000022

1586

#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023

1587

#define V_038004_FMT_1 0x00000025

1588

#define V_038004_FMT_GB_GR 0x00000027

1589

#define V_038004_FMT_BG_RG 0x00000028

1590

#define V_038004_FMT_32_AS_8 0x00000029

1591

#define V_038004_FMT_32_AS_8_8 0x0000002A

1592

#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B

1593

#define V_038004_FMT_8_8_8 0x0000002C

1594

#define V_038004_FMT_16_16_16 0x0000002D

1595

#define V_038004_FMT_16_16_16_FLOAT 0x0000002E

1596

#define V_038004_FMT_32_32_32 0x0000002F

1597

#define V_038004_FMT_32_32_32_FLOAT 0x00000030

Dave Airlie

60b212f

2011-02-18 05:51:58 +0000

[diff] [blame]

1598

#define V_038004_FMT_BC1 0x00000031

1599

#define V_038004_FMT_BC2 0x00000032

1600

#define V_038004_FMT_BC3 0x00000033

1601

#define V_038004_FMT_BC4 0x00000034

1602

#define V_038004_FMT_BC5 0x00000035

Marek Olšák

fe6f0bd

2011-05-07 01:09:57 +0200

[diff] [blame]

1603

#define V_038004_FMT_BC6 0x00000036

1604

#define V_038004_FMT_BC7 0x00000037

1605

#define V_038004_FMT_32_AS_32_32_32_32 0x00000038

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1606

#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010

1607

#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)

1608

#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)

1609

#define C_038010_FORMAT_COMP_X 0xFFFFFFFC

1610

#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)

1611

#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)

1612

#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3

1613

#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)

1614

#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)

1615

#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF

1616

#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)

1617

#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)

1618

#define C_038010_FORMAT_COMP_W 0xFFFFFF3F

1619

#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)

1620

#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)

1621

#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF

1622

#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)

1623

#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)

1624

#define C_038010_SRF_MODE_ALL 0xFFFFFBFF

1625

#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)

1626

#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)

1627

#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF

1628

#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)

1629

#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)

1630

#define C_038010_ENDIAN_SWAP 0xFFFFCFFF

1631

#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)

1632

#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)

1633

#define C_038010_REQUEST_SIZE 0xFFFF3FFF

1634

#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)

1635

#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)

1636

#define C_038010_DST_SEL_X 0xFFF8FFFF

1637

#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)

1638

#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)

1639

#define C_038010_DST_SEL_Y 0xFFC7FFFF

1640

#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)

1641

#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)

1642

#define C_038010_DST_SEL_Z 0xFE3FFFFF

1643

#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)

1644

#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)

1645

#define C_038010_DST_SEL_W 0xF1FFFFFF

Ilija Hadzic

3a38612

2011-10-12 23:29:37 -0400

[diff] [blame]

# define SQ_SEL_X 0

# define SQ_SEL_Y 1

# define SQ_SEL_Z 2

# define SQ_SEL_W 3

# define SQ_SEL_0 4

# define SQ_SEL_1 5

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1652

#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)

1653

#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)

1654

#define C_038010_BASE_LEVEL 0x0FFFFFFF

1655

#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014

1656

#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)

1657

#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)

1658

#define C_038014_LAST_LEVEL 0xFFFFFFF0

1659

#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)

1660

#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)

1661

#define C_038014_BASE_ARRAY 0xFFFE000F

1662

#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)

1663

#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)

1664

#define C_038014_LAST_ARRAY 0xC001FFFF

1665

#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8

1666

#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1667

#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1668

#define C_0288A8_ITEMSIZE 0xFFFF8000

1669

#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44

1670

#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1671

#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1672

#define C_008C44_MEM_SIZE 0x00000000

1673

#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0

1674

#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1675

#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1676

#define C_0288B0_ITEMSIZE 0xFFFF8000

1677

#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54

1678

#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1679

#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1680

#define C_008C54_MEM_SIZE 0x00000000

1681

#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0

1682

#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1683

#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1684

#define C_0288C0_ITEMSIZE 0xFFFF8000

1685

#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74

1686

#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1687

#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1688

#define C_008C74_MEM_SIZE 0x00000000

1689

#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4

1690

#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1691

#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1692

#define C_0288B4_ITEMSIZE 0xFFFF8000

1693

#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C

1694

#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1695

#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1696

#define C_008C5C_MEM_SIZE 0x00000000

1697

#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC

1698

#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1699

#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1700

#define C_0288AC_ITEMSIZE 0xFFFF8000

1701

#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C

1702

#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1703

#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1704

#define C_008C4C_MEM_SIZE 0x00000000

1705

#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC

1706

#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1707

#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1708

#define C_0288BC_ITEMSIZE 0xFFFF8000

1709

#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C

1710

#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1711

#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1712

#define C_008C6C_MEM_SIZE 0x00000000

1713

#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4

1714

#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1715

#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1716

#define C_0288C4_ITEMSIZE 0xFFFF8000

1717

#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C

1718

#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1719

#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1720

#define C_008C7C_MEM_SIZE 0x00000000

1721

#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8

1722

#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1723

#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1724

#define C_0288B8_ITEMSIZE 0xFFFF8000

1725

#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64

1726

#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1727

#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1728

#define C_008C64_MEM_SIZE 0x00000000

1729

#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8

1730

#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1731

#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1732

#define C_0288C8_ITEMSIZE 0xFFFF8000

1733

#define R_028010_DB_DEPTH_INFO 0x028010

1734

#define S_028010_FORMAT(x) (((x) & 0x7) << 0)

1735

#define G_028010_FORMAT(x) (((x) >> 0) & 0x7)

1736

#define C_028010_FORMAT 0xFFFFFFF8

1737

#define V_028010_DEPTH_INVALID 0x00000000

1738

#define V_028010_DEPTH_16 0x00000001

1739

#define V_028010_DEPTH_X8_24 0x00000002

1740

#define V_028010_DEPTH_8_24 0x00000003

1741

#define V_028010_DEPTH_X8_24_FLOAT 0x00000004

1742

#define V_028010_DEPTH_8_24_FLOAT 0x00000005

1743

#define V_028010_DEPTH_32_FLOAT 0x00000006

1744

#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007

1745

#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)

1746

#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)

1747

#define C_028010_READ_SIZE 0xFFFFFFF7

1748

#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)

1749

#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)

1750

#define C_028010_ARRAY_MODE 0xFFF87FFF

Alex Deucher

7f81337

2010-05-20 12:43:52 -0400

[diff] [blame]

1751

#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002

1752

#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1753

#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)

1754

#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)

1755

#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF

1756

#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)

1757

#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)

1758

#define C_028010_TILE_COMPACT 0xFBFFFFFF

1759

#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)

1760

#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)

1761

#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF

1762

#define R_028000_DB_DEPTH_SIZE 0x028000

1763

#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)

1764

#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)

1765

#define C_028000_PITCH_TILE_MAX 0xFFFFFC00

1766

#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)

1767

#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)

1768

#define C_028000_SLICE_TILE_MAX 0xC00003FF

1769

#define R_028004_DB_DEPTH_VIEW 0x028004

1770

#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)

1771

#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)

1772

#define C_028004_SLICE_START 0xFFFFF800

1773

#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)

1774

#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

1775

#define C_028004_SLICE_MAX 0xFF001FFF

1776

#define R_028800_DB_DEPTH_CONTROL 0x028800

1777

#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)

1778

#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)

1779

#define C_028800_STENCIL_ENABLE 0xFFFFFFFE

1780

#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)

1781

#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)

1782

#define C_028800_Z_ENABLE 0xFFFFFFFD

1783

#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)

1784

#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)

1785

#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB

1786

#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)

1787

#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)

1788

#define C_028800_ZFUNC 0xFFFFFF8F

1789

#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)

1790

#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)

1791

#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F

1792

#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)

1793

#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)

1794

#define C_028800_STENCILFUNC 0xFFFFF8FF

1795

#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)

1796

#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)

1797

#define C_028800_STENCILFAIL 0xFFFFC7FF

1798

#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)

1799

#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)

1800

#define C_028800_STENCILZPASS 0xFFFE3FFF

1801

#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)

1802

#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)

1803

#define C_028800_STENCILZFAIL 0xFFF1FFFF

1804

#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)

1805

#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)

1806

#define C_028800_STENCILFUNC_BF 0xFF8FFFFF

1807

#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)

1808

#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)

1809

#define C_028800_STENCILFAIL_BF 0xFC7FFFFF

1810

#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)

1811

#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)

1812

#define C_028800_STENCILZPASS_BF 0xE3FFFFFF

1813

#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)

1814

#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)

1815

#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1816

Jerome Glisse