Dhaval Patel | 13485f1 | 2017-01-11 12:55:22 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/delay.h> |
| 14 | #include "sde_hwio.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 15 | #include "sde_hw_ctl.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 16 | |
| 17 | #define CTL_LAYER(lm) \ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 18 | (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004)) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 19 | #define CTL_LAYER_EXT(lm) \ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 20 | (0x40 + (((lm) - LM_0) * 0x004)) |
Dhaval Patel | 13485f1 | 2017-01-11 12:55:22 -0800 | [diff] [blame] | 21 | #define CTL_LAYER_EXT2(lm) \ |
| 22 | (0x70 + (((lm) - LM_0) * 0x004)) |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 23 | #define CTL_LAYER_EXT3(lm) \ |
| 24 | (0xA0 + (((lm) - LM_0) * 0x004)) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 25 | #define CTL_TOP 0x014 |
| 26 | #define CTL_FLUSH 0x018 |
| 27 | #define CTL_START 0x01C |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 28 | #define CTL_SW_RESET 0x030 |
| 29 | #define CTL_LAYER_EXTN_OFFSET 0x40 |
| 30 | |
| 31 | #define SDE_REG_RESET_TIMEOUT_COUNT 20 |
| 32 | |
| 33 | static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl, |
| 34 | struct sde_mdss_cfg *m, |
| 35 | void __iomem *addr, |
| 36 | struct sde_hw_blk_reg_map *b) |
| 37 | { |
| 38 | int i; |
| 39 | |
| 40 | for (i = 0; i < m->ctl_count; i++) { |
| 41 | if (ctl == m->ctl[i].id) { |
| 42 | b->base_off = addr; |
| 43 | b->blk_off = m->ctl[i].base; |
| 44 | b->hwversion = m->hwversion; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 45 | b->log_mask = SDE_DBG_MASK_CTL; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 46 | return &m->ctl[i]; |
| 47 | } |
| 48 | } |
| 49 | return ERR_PTR(-ENOMEM); |
| 50 | } |
| 51 | |
| 52 | static int _mixer_stages(const struct sde_lm_cfg *mixer, int count, |
| 53 | enum sde_lm lm) |
| 54 | { |
| 55 | int i; |
| 56 | int stages = -EINVAL; |
| 57 | |
| 58 | for (i = 0; i < count; i++) { |
| 59 | if (lm == mixer[i].id) { |
| 60 | stages = mixer[i].sblk->maxblendstages; |
| 61 | break; |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | return stages; |
| 66 | } |
| 67 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 68 | static inline void sde_hw_ctl_trigger_start(struct sde_hw_ctl *ctx) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 69 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 70 | SDE_REG_WRITE(&ctx->hw, CTL_START, 0x1); |
| 71 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 72 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 73 | static inline void sde_hw_ctl_clear_pending_flush(struct sde_hw_ctl *ctx) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 74 | { |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 75 | ctx->pending_flush_mask = 0x0; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 76 | } |
| 77 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 78 | static inline void sde_hw_ctl_update_pending_flush(struct sde_hw_ctl *ctx, |
| 79 | u32 flushbits) |
| 80 | { |
| 81 | ctx->pending_flush_mask |= flushbits; |
| 82 | } |
| 83 | |
Clarence Ip | 110d15c | 2016-08-16 14:44:41 -0400 | [diff] [blame] | 84 | static u32 sde_hw_ctl_get_pending_flush(struct sde_hw_ctl *ctx) |
| 85 | { |
| 86 | if (!ctx) |
| 87 | return 0x0; |
| 88 | |
| 89 | return ctx->pending_flush_mask; |
| 90 | } |
| 91 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 92 | static inline void sde_hw_ctl_trigger_flush(struct sde_hw_ctl *ctx) |
| 93 | { |
| 94 | SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); |
| 95 | } |
| 96 | |
| 97 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 98 | static inline uint32_t sde_hw_ctl_get_bitmask_sspp(struct sde_hw_ctl *ctx, |
| 99 | enum sde_sspp sspp) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 100 | { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 101 | uint32_t flushbits = 0; |
| 102 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 103 | switch (sspp) { |
| 104 | case SSPP_VIG0: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 105 | flushbits = BIT(0); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 106 | break; |
| 107 | case SSPP_VIG1: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 108 | flushbits = BIT(1); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 109 | break; |
| 110 | case SSPP_VIG2: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 111 | flushbits = BIT(2); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 112 | break; |
| 113 | case SSPP_VIG3: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 114 | flushbits = BIT(18); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 115 | break; |
| 116 | case SSPP_RGB0: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 117 | flushbits = BIT(3); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 118 | break; |
| 119 | case SSPP_RGB1: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 120 | flushbits = BIT(4); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 121 | break; |
| 122 | case SSPP_RGB2: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 123 | flushbits = BIT(5); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 124 | break; |
| 125 | case SSPP_RGB3: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 126 | flushbits = BIT(19); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 127 | break; |
| 128 | case SSPP_DMA0: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 129 | flushbits = BIT(11); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 130 | break; |
| 131 | case SSPP_DMA1: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 132 | flushbits = BIT(12); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 133 | break; |
Dhaval Patel | 13485f1 | 2017-01-11 12:55:22 -0800 | [diff] [blame] | 134 | case SSPP_DMA2: |
| 135 | flushbits = BIT(24); |
| 136 | break; |
| 137 | case SSPP_DMA3: |
| 138 | flushbits = BIT(25); |
| 139 | break; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 140 | case SSPP_CURSOR0: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 141 | flushbits = BIT(22); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 142 | break; |
| 143 | case SSPP_CURSOR1: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 144 | flushbits = BIT(23); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 145 | break; |
| 146 | default: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 147 | break; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 148 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 149 | |
| 150 | return flushbits; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 153 | static inline uint32_t sde_hw_ctl_get_bitmask_mixer(struct sde_hw_ctl *ctx, |
| 154 | enum sde_lm lm) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 155 | { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 156 | uint32_t flushbits = 0; |
| 157 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 158 | switch (lm) { |
| 159 | case LM_0: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 160 | flushbits = BIT(6); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 161 | break; |
| 162 | case LM_1: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 163 | flushbits = BIT(7); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 164 | break; |
| 165 | case LM_2: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 166 | flushbits = BIT(8); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 167 | break; |
| 168 | case LM_3: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 169 | flushbits = BIT(9); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 170 | break; |
| 171 | case LM_4: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 172 | flushbits = BIT(10); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 173 | break; |
| 174 | case LM_5: |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 175 | flushbits = BIT(20); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 176 | break; |
| 177 | default: |
| 178 | return -EINVAL; |
| 179 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 180 | |
| 181 | flushbits |= BIT(17); /* CTL */ |
| 182 | |
| 183 | return flushbits; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | static inline int sde_hw_ctl_get_bitmask_dspp(struct sde_hw_ctl *ctx, |
| 187 | u32 *flushbits, enum sde_dspp dspp) |
| 188 | { |
| 189 | switch (dspp) { |
| 190 | case DSPP_0: |
| 191 | *flushbits |= BIT(13); |
| 192 | break; |
| 193 | case DSPP_1: |
| 194 | *flushbits |= BIT(14); |
| 195 | break; |
| 196 | default: |
| 197 | return -EINVAL; |
| 198 | } |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static inline int sde_hw_ctl_get_bitmask_intf(struct sde_hw_ctl *ctx, |
| 203 | u32 *flushbits, enum sde_intf intf) |
| 204 | { |
| 205 | switch (intf) { |
| 206 | case INTF_0: |
| 207 | *flushbits |= BIT(31); |
| 208 | break; |
| 209 | case INTF_1: |
| 210 | *flushbits |= BIT(30); |
| 211 | break; |
| 212 | case INTF_2: |
| 213 | *flushbits |= BIT(29); |
| 214 | break; |
| 215 | case INTF_3: |
| 216 | *flushbits |= BIT(28); |
| 217 | break; |
| 218 | default: |
| 219 | return -EINVAL; |
| 220 | } |
| 221 | return 0; |
| 222 | } |
| 223 | |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 224 | static inline int sde_hw_ctl_get_bitmask_wb(struct sde_hw_ctl *ctx, |
| 225 | u32 *flushbits, enum sde_wb wb) |
| 226 | { |
| 227 | switch (wb) { |
| 228 | case WB_0: |
| 229 | case WB_1: |
| 230 | case WB_2: |
| 231 | *flushbits |= BIT(16); |
| 232 | break; |
| 233 | default: |
| 234 | return -EINVAL; |
| 235 | } |
| 236 | return 0; |
| 237 | } |
| 238 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 239 | static inline int sde_hw_ctl_get_bitmask_cdm(struct sde_hw_ctl *ctx, |
| 240 | u32 *flushbits, enum sde_cdm cdm) |
| 241 | { |
| 242 | switch (cdm) { |
| 243 | case CDM_0: |
| 244 | *flushbits |= BIT(26); |
| 245 | break; |
| 246 | default: |
| 247 | return -EINVAL; |
| 248 | } |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx) |
| 253 | { |
| 254 | struct sde_hw_blk_reg_map *c = &ctx->hw; |
| 255 | int count = SDE_REG_RESET_TIMEOUT_COUNT; |
| 256 | int reset; |
| 257 | |
| 258 | SDE_REG_WRITE(c, CTL_SW_RESET, 0x1); |
| 259 | |
| 260 | for (; count > 0; count--) { |
| 261 | /* insert small delay to avoid spinning the cpu while waiting */ |
| 262 | usleep_range(20, 50); |
| 263 | reset = SDE_REG_READ(c, CTL_SW_RESET); |
| 264 | if (reset == 0) |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | return -EINVAL; |
| 269 | } |
| 270 | |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame] | 271 | static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx) |
| 272 | { |
| 273 | struct sde_hw_blk_reg_map *c = &ctx->hw; |
| 274 | int i; |
| 275 | |
| 276 | for (i = 0; i < ctx->mixer_count; i++) { |
| 277 | SDE_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0); |
| 278 | SDE_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0); |
| 279 | } |
| 280 | } |
| 281 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 282 | static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx, |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 283 | enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg, u32 index) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 284 | { |
| 285 | struct sde_hw_blk_reg_map *c = &ctx->hw; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 286 | u32 mixercfg = 0, mixercfg_ext = 0, mix, ext; |
| 287 | u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 288 | int i, j; |
| 289 | u8 stages; |
| 290 | int pipes_per_stage; |
| 291 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 292 | if (index >= CRTC_DUAL_MIXERS) |
| 293 | return; |
| 294 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 295 | stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm); |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 296 | if (stages < 0) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 297 | return; |
| 298 | |
| 299 | if (test_bit(SDE_MIXER_SOURCESPLIT, |
| 300 | &ctx->mixer_hw_caps->features)) |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 301 | pipes_per_stage = PIPES_PER_STAGE; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 302 | else |
| 303 | pipes_per_stage = 1; |
| 304 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 305 | mixercfg = BIT(24); /* always set BORDER_OUT */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 306 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 307 | for (i = 0; i <= stages; i++) { |
Clarence Ip | 7b49357 | 2015-12-21 17:57:48 -0500 | [diff] [blame] | 308 | /* overflow to ext register if 'i + 1 > 7' */ |
| 309 | mix = (i + 1) & 0x7; |
| 310 | ext = i >= 7; |
| 311 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 312 | for (j = 0 ; j < pipes_per_stage; j++) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 313 | enum sde_sspp_multirect_index rect_index = |
| 314 | stage_cfg->multirect_index[index][i][j]; |
| 315 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 316 | switch (stage_cfg->stage[index][i][j]) { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 317 | case SSPP_VIG0: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 318 | if (rect_index == SDE_SSPP_RECT_1) { |
| 319 | mixercfg_ext3 |= ((i + 1) & 0xF) << 0; |
| 320 | } else { |
| 321 | mixercfg |= mix << 0; |
| 322 | mixercfg_ext |= ext << 0; |
| 323 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 324 | break; |
| 325 | case SSPP_VIG1: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 326 | if (rect_index == SDE_SSPP_RECT_1) { |
| 327 | mixercfg_ext3 |= ((i + 1) & 0xF) << 4; |
| 328 | } else { |
| 329 | mixercfg |= mix << 3; |
| 330 | mixercfg_ext |= ext << 2; |
| 331 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 332 | break; |
| 333 | case SSPP_VIG2: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 334 | if (rect_index == SDE_SSPP_RECT_1) { |
| 335 | mixercfg_ext3 |= ((i + 1) & 0xF) << 8; |
| 336 | } else { |
| 337 | mixercfg |= mix << 6; |
| 338 | mixercfg_ext |= ext << 4; |
| 339 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 340 | break; |
| 341 | case SSPP_VIG3: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 342 | if (rect_index == SDE_SSPP_RECT_1) { |
| 343 | mixercfg_ext3 |= ((i + 1) & 0xF) << 12; |
| 344 | } else { |
| 345 | mixercfg |= mix << 26; |
| 346 | mixercfg_ext |= ext << 6; |
| 347 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 348 | break; |
| 349 | case SSPP_RGB0: |
Clarence Ip | 7b49357 | 2015-12-21 17:57:48 -0500 | [diff] [blame] | 350 | mixercfg |= mix << 9; |
| 351 | mixercfg_ext |= ext << 8; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 352 | break; |
| 353 | case SSPP_RGB1: |
Clarence Ip | 7b49357 | 2015-12-21 17:57:48 -0500 | [diff] [blame] | 354 | mixercfg |= mix << 12; |
| 355 | mixercfg_ext |= ext << 10; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 356 | break; |
| 357 | case SSPP_RGB2: |
Clarence Ip | 7b49357 | 2015-12-21 17:57:48 -0500 | [diff] [blame] | 358 | mixercfg |= mix << 15; |
| 359 | mixercfg_ext |= ext << 12; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 360 | break; |
| 361 | case SSPP_RGB3: |
Clarence Ip | 7b49357 | 2015-12-21 17:57:48 -0500 | [diff] [blame] | 362 | mixercfg |= mix << 29; |
| 363 | mixercfg_ext |= ext << 14; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 364 | break; |
| 365 | case SSPP_DMA0: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 366 | if (rect_index == SDE_SSPP_RECT_1) { |
| 367 | mixercfg_ext2 |= ((i + 1) & 0xF) << 8; |
| 368 | } else { |
| 369 | mixercfg |= mix << 18; |
| 370 | mixercfg_ext |= ext << 16; |
| 371 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 372 | break; |
| 373 | case SSPP_DMA1: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 374 | if (rect_index == SDE_SSPP_RECT_1) { |
| 375 | mixercfg_ext2 |= ((i + 1) & 0xF) << 12; |
| 376 | } else { |
| 377 | mixercfg |= mix << 21; |
| 378 | mixercfg_ext |= ext << 18; |
| 379 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 380 | break; |
Dhaval Patel | 13485f1 | 2017-01-11 12:55:22 -0800 | [diff] [blame] | 381 | case SSPP_DMA2: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 382 | if (rect_index == SDE_SSPP_RECT_1) { |
| 383 | mixercfg_ext2 |= ((i + 1) & 0xF) << 16; |
| 384 | } else { |
| 385 | mix |= (i + 1) & 0xF; |
| 386 | mixercfg_ext2 |= mix << 0; |
| 387 | } |
Dhaval Patel | 13485f1 | 2017-01-11 12:55:22 -0800 | [diff] [blame] | 388 | break; |
| 389 | case SSPP_DMA3: |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 390 | if (rect_index == SDE_SSPP_RECT_1) { |
| 391 | mixercfg_ext2 |= ((i + 1) & 0xF) << 20; |
| 392 | } else { |
| 393 | mix |= (i + 1) & 0xF; |
| 394 | mixercfg_ext2 |= mix << 4; |
| 395 | } |
Dhaval Patel | 13485f1 | 2017-01-11 12:55:22 -0800 | [diff] [blame] | 396 | break; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 397 | case SSPP_CURSOR0: |
Clarence Ip | 7b49357 | 2015-12-21 17:57:48 -0500 | [diff] [blame] | 398 | mixercfg_ext |= ((i + 1) & 0xF) << 20; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 399 | break; |
| 400 | case SSPP_CURSOR1: |
Clarence Ip | 7b49357 | 2015-12-21 17:57:48 -0500 | [diff] [blame] | 401 | mixercfg_ext |= ((i + 1) & 0xF) << 26; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 402 | break; |
| 403 | default: |
| 404 | break; |
| 405 | } |
| 406 | } |
| 407 | } |
| 408 | |
| 409 | SDE_REG_WRITE(c, CTL_LAYER(lm), mixercfg); |
| 410 | SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext); |
Dhaval Patel | 13485f1 | 2017-01-11 12:55:22 -0800 | [diff] [blame] | 411 | SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame^] | 412 | SDE_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 413 | } |
| 414 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 415 | static void sde_hw_ctl_intf_cfg(struct sde_hw_ctl *ctx, |
| 416 | struct sde_hw_intf_cfg *cfg) |
| 417 | { |
| 418 | struct sde_hw_blk_reg_map *c = &ctx->hw; |
| 419 | u32 intf_cfg = 0; |
| 420 | |
| 421 | intf_cfg |= (cfg->intf & 0xF) << 4; |
| 422 | |
| 423 | if (cfg->wb) |
| 424 | intf_cfg |= (cfg->wb & 0x3) + 2; |
| 425 | |
| 426 | if (cfg->mode_3d) { |
| 427 | intf_cfg |= BIT(19); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 428 | intf_cfg |= (cfg->mode_3d - 0x1) << 20; |
| 429 | } |
| 430 | |
| 431 | switch (cfg->intf_mode_sel) { |
| 432 | case SDE_CTL_MODE_SEL_VID: |
| 433 | intf_cfg &= ~BIT(17); |
| 434 | intf_cfg &= ~(0x3 << 15); |
| 435 | break; |
| 436 | case SDE_CTL_MODE_SEL_CMD: |
| 437 | intf_cfg |= BIT(17); |
| 438 | intf_cfg |= ((cfg->stream_sel & 0x3) << 15); |
| 439 | break; |
| 440 | default: |
| 441 | pr_err("unknown interface type %d\n", cfg->intf_mode_sel); |
| 442 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 443 | } |
| 444 | |
| 445 | SDE_REG_WRITE(c, CTL_TOP, intf_cfg); |
| 446 | } |
| 447 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 448 | static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, |
| 449 | unsigned long cap) |
| 450 | { |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 451 | ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush; |
| 452 | ops->update_pending_flush = sde_hw_ctl_update_pending_flush; |
Clarence Ip | 110d15c | 2016-08-16 14:44:41 -0400 | [diff] [blame] | 453 | ops->get_pending_flush = sde_hw_ctl_get_pending_flush; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 454 | ops->trigger_flush = sde_hw_ctl_trigger_flush; |
| 455 | ops->trigger_start = sde_hw_ctl_trigger_start; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 456 | ops->setup_intf_cfg = sde_hw_ctl_intf_cfg; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 457 | ops->reset = sde_hw_ctl_reset_control; |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame] | 458 | ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 459 | ops->setup_blendstage = sde_hw_ctl_setup_blendstage; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 460 | ops->get_bitmask_sspp = sde_hw_ctl_get_bitmask_sspp; |
| 461 | ops->get_bitmask_mixer = sde_hw_ctl_get_bitmask_mixer; |
| 462 | ops->get_bitmask_dspp = sde_hw_ctl_get_bitmask_dspp; |
| 463 | ops->get_bitmask_intf = sde_hw_ctl_get_bitmask_intf; |
| 464 | ops->get_bitmask_cdm = sde_hw_ctl_get_bitmask_cdm; |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 465 | ops->get_bitmask_wb = sde_hw_ctl_get_bitmask_wb; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 466 | }; |
| 467 | |
| 468 | struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx, |
| 469 | void __iomem *addr, |
| 470 | struct sde_mdss_cfg *m) |
| 471 | { |
| 472 | struct sde_hw_ctl *c; |
| 473 | struct sde_ctl_cfg *cfg; |
| 474 | |
| 475 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
| 476 | if (!c) |
| 477 | return ERR_PTR(-ENOMEM); |
| 478 | |
| 479 | cfg = _ctl_offset(idx, m, addr, &c->hw); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 480 | if (IS_ERR_OR_NULL(cfg)) { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 481 | kfree(c); |
Lloyd Atkinson | 2349126 | 2016-05-19 09:37:02 -0400 | [diff] [blame] | 482 | pr_err("failed to create sde_hw_ctl %d\n", idx); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 483 | return ERR_PTR(-EINVAL); |
| 484 | } |
| 485 | |
| 486 | c->caps = cfg; |
| 487 | _setup_ctl_ops(&c->ops, c->caps->features); |
| 488 | c->idx = idx; |
| 489 | c->mixer_count = m->mixer_count; |
| 490 | c->mixer_hw_caps = m->mixer; |
| 491 | |
| 492 | return c; |
| 493 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 494 | |
| 495 | void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx) |
| 496 | { |
| 497 | kfree(ctx); |
| 498 | } |