| Tatenda Chipeperekwa | 2eb6fa5 | 2017-07-12 13:42:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef _DP_REG_H_ |
| 16 | #define _DP_REG_H_ |
| 17 | |
| 18 | /* DP_TX Registers */ |
| 19 | #define DP_HW_VERSION (0x00000000) |
| 20 | #define DP_SW_RESET (0x00000010) |
| 21 | #define DP_PHY_CTRL (0x00000014) |
| 22 | #define DP_CLK_CTRL (0x00000018) |
| 23 | #define DP_CLK_ACTIVE (0x0000001C) |
| 24 | #define DP_INTR_STATUS (0x00000020) |
| 25 | #define DP_INTR_STATUS2 (0x00000024) |
| 26 | #define DP_INTR_STATUS3 (0x00000028) |
| 27 | |
| 28 | #define DP_DP_HPD_CTRL (0x00000200) |
| 29 | #define DP_DP_HPD_INT_STATUS (0x00000204) |
| 30 | #define DP_DP_HPD_INT_ACK (0x00000208) |
| 31 | #define DP_DP_HPD_INT_MASK (0x0000020C) |
| 32 | #define DP_DP_HPD_REFTIMER (0x00000218) |
| 33 | #define DP_DP_HPD_EVENT_TIME_0 (0x0000021C) |
| 34 | #define DP_DP_HPD_EVENT_TIME_1 (0x00000220) |
| 35 | #define DP_AUX_CTRL (0x00000230) |
| 36 | #define DP_AUX_DATA (0x00000234) |
| 37 | #define DP_AUX_TRANS_CTRL (0x00000238) |
| 38 | #define DP_TIMEOUT_COUNT (0x0000023C) |
| 39 | #define DP_AUX_LIMITS (0x00000240) |
| 40 | #define DP_AUX_STATUS (0x00000244) |
| 41 | |
| 42 | #define DP_DPCD_CP_IRQ (0x201) |
| 43 | #define DP_DPCD_RXSTATUS (0x69493) |
| 44 | |
| 45 | #define DP_INTERRUPT_TRANS_NUM (0x000002A0) |
| 46 | |
| 47 | #define DP_MAINLINK_CTRL (0x00000400) |
| 48 | #define DP_STATE_CTRL (0x00000404) |
| 49 | #define DP_CONFIGURATION_CTRL (0x00000408) |
| 50 | #define DP_SOFTWARE_MVID (0x00000410) |
| 51 | #define DP_SOFTWARE_NVID (0x00000418) |
| 52 | #define DP_TOTAL_HOR_VER (0x0000041C) |
| 53 | #define DP_START_HOR_VER_FROM_SYNC (0x00000420) |
| 54 | #define DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000424) |
| 55 | #define DP_ACTIVE_HOR_VER (0x00000428) |
| 56 | #define DP_MISC1_MISC0 (0x0000042C) |
| 57 | #define DP_VALID_BOUNDARY (0x00000430) |
| 58 | #define DP_VALID_BOUNDARY_2 (0x00000434) |
| 59 | #define DP_LOGICAL2PHYSCIAL_LANE_MAPPING (0x00000438) |
| 60 | |
| 61 | #define DP_MAINLINK_READY (0x00000440) |
| 62 | #define DP_MAINLINK_LEVELS (0x00000444) |
| 63 | #define DP_TU (0x0000044C) |
| 64 | |
| 65 | #define DP_HBR2_COMPLIANCE_SCRAMBLER_RESET (0x00000454) |
| 66 | #define DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000004C0) |
| 67 | #define DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000004C4) |
| 68 | #define DP_TEST_80BIT_CUSTOM_PATTERN_REG2 (0x000004C8) |
| 69 | |
| 70 | #define MMSS_DP_MISC1_MISC0 (0x0000042C) |
| 71 | #define MMSS_DP_AUDIO_TIMING_GEN (0x00000480) |
| 72 | #define MMSS_DP_AUDIO_TIMING_RBR_32 (0x00000484) |
| 73 | #define MMSS_DP_AUDIO_TIMING_HBR_32 (0x00000488) |
| 74 | #define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000048C) |
| 75 | #define MMSS_DP_AUDIO_TIMING_HBR_44 (0x00000490) |
| 76 | #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000494) |
| 77 | #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000498) |
| 78 | |
| 79 | #define MMSS_DP_PSR_CRC_RG (0x00000554) |
| 80 | #define MMSS_DP_PSR_CRC_B (0x00000558) |
| 81 | |
| Ajay Singh Parmar | 059d0e0 | 2017-09-13 11:37:40 -0700 | [diff] [blame] | 82 | #define DP_COMPRESSION_MODE_CTRL (0x00000580) |
| 83 | |
| Tatenda Chipeperekwa | 2eb6fa5 | 2017-07-12 13:42:11 -0700 | [diff] [blame] | 84 | #define MMSS_DP_AUDIO_CFG (0x00000600) |
| 85 | #define MMSS_DP_AUDIO_STATUS (0x00000604) |
| 86 | #define MMSS_DP_AUDIO_PKT_CTRL (0x00000608) |
| 87 | #define MMSS_DP_AUDIO_PKT_CTRL2 (0x0000060C) |
| 88 | #define MMSS_DP_AUDIO_ACR_CTRL (0x00000610) |
| 89 | #define MMSS_DP_AUDIO_CTRL_RESET (0x00000614) |
| 90 | |
| 91 | #define MMSS_DP_SDP_CFG (0x00000628) |
| 92 | #define MMSS_DP_SDP_CFG2 (0x0000062C) |
| 93 | #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000630) |
| 94 | #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000634) |
| 95 | |
| 96 | #define MMSS_DP_AUDIO_STREAM_0 (0x00000640) |
| 97 | #define MMSS_DP_AUDIO_STREAM_1 (0x00000644) |
| 98 | |
| 99 | #define MMSS_DP_EXTENSION_0 (0x00000650) |
| 100 | #define MMSS_DP_EXTENSION_1 (0x00000654) |
| 101 | #define MMSS_DP_EXTENSION_2 (0x00000658) |
| 102 | #define MMSS_DP_EXTENSION_3 (0x0000065C) |
| 103 | #define MMSS_DP_EXTENSION_4 (0x00000660) |
| 104 | #define MMSS_DP_EXTENSION_5 (0x00000664) |
| 105 | #define MMSS_DP_EXTENSION_6 (0x00000668) |
| 106 | #define MMSS_DP_EXTENSION_7 (0x0000066C) |
| 107 | #define MMSS_DP_EXTENSION_8 (0x00000670) |
| 108 | #define MMSS_DP_EXTENSION_9 (0x00000674) |
| 109 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_0 (0x00000678) |
| 110 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000067C) |
| 111 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_2 (0x00000680) |
| 112 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_3 (0x00000684) |
| 113 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000688) |
| 114 | #define MMSS_DP_AUDIO_COPYMANAGEMENT_5 (0x0000068C) |
| 115 | #define MMSS_DP_AUDIO_ISRC_0 (0x00000690) |
| 116 | #define MMSS_DP_AUDIO_ISRC_1 (0x00000694) |
| 117 | #define MMSS_DP_AUDIO_ISRC_2 (0x00000698) |
| 118 | #define MMSS_DP_AUDIO_ISRC_3 (0x0000069C) |
| 119 | #define MMSS_DP_AUDIO_ISRC_4 (0x000006A0) |
| 120 | #define MMSS_DP_AUDIO_ISRC_5 (0x000006A4) |
| 121 | #define MMSS_DP_AUDIO_INFOFRAME_0 (0x000006A8) |
| 122 | #define MMSS_DP_AUDIO_INFOFRAME_1 (0x000006AC) |
| 123 | #define MMSS_DP_AUDIO_INFOFRAME_2 (0x000006B0) |
| 124 | |
| 125 | #define MMSS_DP_GENERIC0_0 (0x00000700) |
| 126 | #define MMSS_DP_GENERIC0_1 (0x00000704) |
| 127 | #define MMSS_DP_GENERIC0_2 (0x00000708) |
| 128 | #define MMSS_DP_GENERIC0_3 (0x0000070C) |
| 129 | #define MMSS_DP_GENERIC0_4 (0x00000710) |
| 130 | #define MMSS_DP_GENERIC0_5 (0x00000714) |
| 131 | #define MMSS_DP_GENERIC0_6 (0x00000718) |
| 132 | #define MMSS_DP_GENERIC0_7 (0x0000071C) |
| 133 | #define MMSS_DP_GENERIC0_8 (0x00000720) |
| 134 | #define MMSS_DP_GENERIC0_9 (0x00000724) |
| 135 | #define MMSS_DP_GENERIC1_0 (0x00000728) |
| 136 | #define MMSS_DP_GENERIC1_1 (0x0000072C) |
| 137 | #define MMSS_DP_GENERIC1_2 (0x00000730) |
| 138 | #define MMSS_DP_GENERIC1_3 (0x00000734) |
| 139 | #define MMSS_DP_GENERIC1_4 (0x00000738) |
| 140 | #define MMSS_DP_GENERIC1_5 (0x0000073C) |
| 141 | #define MMSS_DP_GENERIC1_6 (0x00000740) |
| 142 | #define MMSS_DP_GENERIC1_7 (0x00000744) |
| 143 | #define MMSS_DP_GENERIC1_8 (0x00000748) |
| 144 | #define MMSS_DP_GENERIC1_9 (0x0000074C) |
| 145 | |
| Ajay Singh Parmar | 059d0e0 | 2017-09-13 11:37:40 -0700 | [diff] [blame] | 146 | #define MMSS_DP_VSCEXT_0 (0x000006D0) |
| 147 | #define MMSS_DP_VSCEXT_1 (0x000006D4) |
| 148 | #define MMSS_DP_VSCEXT_2 (0x000006D8) |
| 149 | #define MMSS_DP_VSCEXT_3 (0x000006DC) |
| 150 | #define MMSS_DP_VSCEXT_4 (0x000006E0) |
| 151 | #define MMSS_DP_VSCEXT_5 (0x000006E4) |
| 152 | #define MMSS_DP_VSCEXT_6 (0x000006E8) |
| 153 | #define MMSS_DP_VSCEXT_7 (0x000006EC) |
| 154 | #define MMSS_DP_VSCEXT_8 (0x000006F0) |
| 155 | #define MMSS_DP_VSCEXT_9 (0x000006F4) |
| 156 | |
| Tatenda Chipeperekwa | 2eb6fa5 | 2017-07-12 13:42:11 -0700 | [diff] [blame] | 157 | #define MMSS_DP_TIMING_ENGINE_EN (0x00000A10) |
| 158 | #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000A88) |
| 159 | |
| 160 | /*DP PHY Register offsets */ |
| 161 | #define DP_PHY_REVISION_ID0 (0x00000000) |
| 162 | #define DP_PHY_REVISION_ID1 (0x00000004) |
| 163 | #define DP_PHY_REVISION_ID2 (0x00000008) |
| 164 | #define DP_PHY_REVISION_ID3 (0x0000000C) |
| 165 | |
| 166 | #define DP_PHY_CFG (0x00000010) |
| 167 | #define DP_PHY_PD_CTL (0x00000018) |
| 168 | #define DP_PHY_MODE (0x0000001C) |
| 169 | |
| 170 | #define DP_PHY_AUX_CFG0 (0x00000020) |
| 171 | #define DP_PHY_AUX_CFG1 (0x00000024) |
| 172 | #define DP_PHY_AUX_CFG2 (0x00000028) |
| 173 | #define DP_PHY_AUX_CFG3 (0x0000002C) |
| 174 | #define DP_PHY_AUX_CFG4 (0x00000030) |
| 175 | #define DP_PHY_AUX_CFG5 (0x00000034) |
| 176 | #define DP_PHY_AUX_CFG6 (0x00000038) |
| 177 | #define DP_PHY_AUX_CFG7 (0x0000003C) |
| 178 | #define DP_PHY_AUX_CFG8 (0x00000040) |
| 179 | #define DP_PHY_AUX_CFG9 (0x00000044) |
| 180 | #define DP_PHY_AUX_INTERRUPT_MASK (0x00000048) |
| 181 | #define DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) |
| Padmanabhan Komanduru | f69e357 | 2017-09-27 20:39:32 +0530 | [diff] [blame] | 182 | #define DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) |
| Tatenda Chipeperekwa | 2eb6fa5 | 2017-07-12 13:42:11 -0700 | [diff] [blame] | 183 | |
| 184 | #define DP_PHY_SPARE0 (0x00AC) |
| 185 | |
| 186 | #define TXn_TX_EMP_POST1_LVL (0x000C) |
| 187 | #define TXn_TX_DRV_LVL (0x001C) |
| 188 | |
| 189 | #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x004) |
| 190 | |
| 191 | /* DP MMSS_CC registers */ |
| 192 | #define MMSS_DP_LINK_CMD_RCGR (0x0138) |
| 193 | #define MMSS_DP_LINK_CFG_RCGR (0x013C) |
| 194 | #define MMSS_DP_PIXEL_M (0x0174) |
| 195 | #define MMSS_DP_PIXEL_N (0x0178) |
| 196 | |
| 197 | /* DP HDCP 1.3 registers */ |
| 198 | #define DP_HDCP_CTRL (0x0A0) |
| 199 | #define DP_HDCP_STATUS (0x0A4) |
| 200 | #define DP_HDCP_SW_UPPER_AKSV (0x298) |
| 201 | #define DP_HDCP_SW_LOWER_AKSV (0x29C) |
| 202 | #define DP_HDCP_ENTROPY_CTRL0 (0x750) |
| 203 | #define DP_HDCP_ENTROPY_CTRL1 (0x75C) |
| 204 | #define DP_HDCP_SHA_STATUS (0x0C8) |
| 205 | #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) |
| 206 | #define DP_HDCP_RCVPORT_DATA3 (0x2A4) |
| 207 | #define DP_HDCP_RCVPORT_DATA4 (0x2A8) |
| 208 | #define DP_HDCP_RCVPORT_DATA5 (0x0C0) |
| 209 | #define DP_HDCP_RCVPORT_DATA6 (0x0C4) |
| 210 | |
| 211 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024) |
| 212 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA (0x028) |
| 213 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) |
| 214 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008) |
| 215 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) |
| 216 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010) |
| 217 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014) |
| 218 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) |
| 219 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) |
| 220 | #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) |
| 221 | |
| Padmanabhan Komanduru | b6117bd | 2017-05-11 20:18:40 -0700 | [diff] [blame] | 222 | /* USB3 DP COM registers */ |
| 223 | #define USB3_DP_COM_RESET_OVRD_CTRL (0x1C) |
| 224 | #define USB3_DP_COM_PHY_MODE_CTRL (0x00) |
| 225 | #define USB3_DP_COM_SW_RESET (0x04) |
| 226 | #define USB3_DP_COM_TYPEC_CTRL (0x10) |
| 227 | #define USB3_DP_COM_SWI_CTRL (0x0c) |
| 228 | #define USB3_DP_COM_POWER_DOWN_CTRL (0x08) |
| 229 | |
| 230 | |
| 231 | |
| Tatenda Chipeperekwa | 2eb6fa5 | 2017-07-12 13:42:11 -0700 | [diff] [blame] | 232 | #endif /* _DP_REG_H_ */ |