Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 2ef28cfb098914f1b8e74807e0cbca2e89262d97 / . / drivers / pinctrl / sh-pfc / pfc-r8a73a4.c
blob: d25fd4ea0a1da009e90fdb9ffb6ddd0ae1c0e03d [file] [log] [blame]
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1/*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]20#include <linux/io.h>
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]21#include <linux/kernel.h>
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]22#include <linux/pinctrl/pinconf-generic.h>
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]23#include <mach/irqs.h>
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]24
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]25#include "core.h"
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]26#include "sh_pfc.h"
27
28#define CPU_ALL_PORT(fn, pfx, sfx) \
29 /* Port0 - Port30 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]30 PORT_10(0, fn, pfx, sfx), \
31 PORT_10(10, fn, pfx##1, sfx), \
32 PORT_10(20, fn, pfx##2, sfx), \
33 PORT_1(30, fn, pfx##30, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]34 /* Port32 - Port40 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]35 PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
36 PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
37 PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
38 PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
39 PORT_1(40, fn, pfx##40, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]40 /* Port64 - Port85 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]41 PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
42 PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
43 PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
44 PORT_10(70, fn, pfx##7, sfx), \
45 PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
46 PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
47 PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]48 /* Port96 - Port126 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]49 PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \
50 PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \
51 PORT_10(100, fn, pfx##10, sfx), \
52 PORT_10(110, fn, pfx##11, sfx), \
53 PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
54 PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
55 PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
56 PORT_1(126, fn, pfx##126, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]57 /* Port128 - Port134 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]58 PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
59 PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
60 PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
61 PORT_1(134, fn, pfx##134, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]62 /* Port160 - Port178 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]63 PORT_10(160, fn, pfx##16, sfx), \
64 PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
65 PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
66 PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
67 PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
68 PORT_1(178, fn, pfx##178, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]69 /* Port192 - Port222 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]70 PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
71 PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
72 PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
73 PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
74 PORT_10(200, fn, pfx##20, sfx), \
75 PORT_10(210, fn, pfx##21, sfx), \
76 PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
77 PORT_1(222, fn, pfx##222, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]78 /* Port224 - Port250 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]79 PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
80 PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
81 PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
82 PORT_10(230, fn, pfx##23, sfx), \
83 PORT_10(240, fn, pfx##24, sfx), \
84 PORT_1(250, fn, pfx##250, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]85 /* Port256 - Port283 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]86 PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
87 PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
88 PORT_10(260, fn, pfx##26, sfx), \
89 PORT_10(270, fn, pfx##27, sfx), \
90 PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
91 PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]92 /* Port288 - Port308 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]93 PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
94 PORT_10(290, fn, pfx##29, sfx), \
95 PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
96 PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
97 PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
98 PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
99 PORT_1(308, fn, pfx##308, sfx), \
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]100 /* Port320 - Port329 */ \
Laurent Pinchart16b915e2013-02-14 00:24:32 +0100[diff] [blame]101 PORT_10(320, fn, pfx##32, sfx)
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]102
103
104enum {
105 PINMUX_RESERVED = 0,
106
107 /* PORT0_DATA -> PORT329_DATA */
108 PINMUX_DATA_BEGIN,
109 PORT_ALL(DATA),
110 PINMUX_DATA_END,
111
112 /* PORT0_IN -> PORT329_IN */
113 PINMUX_INPUT_BEGIN,
114 PORT_ALL(IN),
115 PINMUX_INPUT_END,
116
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]117 /* PORT0_OUT -> PORT329_OUT */
118 PINMUX_OUTPUT_BEGIN,
119 PORT_ALL(OUT),
120 PINMUX_OUTPUT_END,
121
122 PINMUX_FUNCTION_BEGIN,
123 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
124 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
125 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
126 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
127 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
128 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
129 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
130 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
131 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
132 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
133
134 MSEL1CR_31_0, MSEL1CR_31_1,
135 MSEL1CR_27_0, MSEL1CR_27_1,
136 MSEL1CR_25_0, MSEL1CR_25_1,
137 MSEL1CR_24_0, MSEL1CR_24_1,
138 MSEL1CR_22_0, MSEL1CR_22_1,
139 MSEL1CR_21_0, MSEL1CR_21_1,
140 MSEL1CR_20_0, MSEL1CR_20_1,
141 MSEL1CR_19_0, MSEL1CR_19_1,
142 MSEL1CR_18_0, MSEL1CR_18_1,
143 MSEL1CR_17_0, MSEL1CR_17_1,
144 MSEL1CR_16_0, MSEL1CR_16_1,
145 MSEL1CR_15_0, MSEL1CR_15_1,
146 MSEL1CR_14_0, MSEL1CR_14_1,
147 MSEL1CR_13_0, MSEL1CR_13_1,
148 MSEL1CR_12_0, MSEL1CR_12_1,
149 MSEL1CR_11_0, MSEL1CR_11_1,
150 MSEL1CR_10_0, MSEL1CR_10_1,
151 MSEL1CR_09_0, MSEL1CR_09_1,
152 MSEL1CR_08_0, MSEL1CR_08_1,
153 MSEL1CR_07_0, MSEL1CR_07_1,
154 MSEL1CR_06_0, MSEL1CR_06_1,
155 MSEL1CR_05_0, MSEL1CR_05_1,
156 MSEL1CR_04_0, MSEL1CR_04_1,
157 MSEL1CR_03_0, MSEL1CR_03_1,
158 MSEL1CR_02_0, MSEL1CR_02_1,
159 MSEL1CR_01_0, MSEL1CR_01_1,
160 MSEL1CR_00_0, MSEL1CR_00_1,
161
162 MSEL3CR_31_0, MSEL3CR_31_1,
163 MSEL3CR_28_0, MSEL3CR_28_1,
164 MSEL3CR_27_0, MSEL3CR_27_1,
165 MSEL3CR_26_0, MSEL3CR_26_1,
166 MSEL3CR_23_0, MSEL3CR_23_1,
167 MSEL3CR_22_0, MSEL3CR_22_1,
168 MSEL3CR_21_0, MSEL3CR_21_1,
169 MSEL3CR_20_0, MSEL3CR_20_1,
170 MSEL3CR_19_0, MSEL3CR_19_1,
171 MSEL3CR_18_0, MSEL3CR_18_1,
172 MSEL3CR_17_0, MSEL3CR_17_1,
173 MSEL3CR_16_0, MSEL3CR_16_1,
174 MSEL3CR_15_0, MSEL3CR_15_1,
175 MSEL3CR_12_0, MSEL3CR_12_1,
176 MSEL3CR_11_0, MSEL3CR_11_1,
177 MSEL3CR_10_0, MSEL3CR_10_1,
178 MSEL3CR_09_0, MSEL3CR_09_1,
179 MSEL3CR_06_0, MSEL3CR_06_1,
180 MSEL3CR_03_0, MSEL3CR_03_1,
181 MSEL3CR_01_0, MSEL3CR_01_1,
182 MSEL3CR_00_0, MSEL3CR_00_1,
183
184 MSEL4CR_30_0, MSEL4CR_30_1,
185 MSEL4CR_29_0, MSEL4CR_29_1,
186 MSEL4CR_28_0, MSEL4CR_28_1,
187 MSEL4CR_27_0, MSEL4CR_27_1,
188 MSEL4CR_26_0, MSEL4CR_26_1,
189 MSEL4CR_25_0, MSEL4CR_25_1,
190 MSEL4CR_24_0, MSEL4CR_24_1,
191 MSEL4CR_23_0, MSEL4CR_23_1,
192 MSEL4CR_22_0, MSEL4CR_22_1,
193 MSEL4CR_21_0, MSEL4CR_21_1,
194 MSEL4CR_20_0, MSEL4CR_20_1,
195 MSEL4CR_19_0, MSEL4CR_19_1,
196 MSEL4CR_18_0, MSEL4CR_18_1,
197 MSEL4CR_17_0, MSEL4CR_17_1,
198 MSEL4CR_16_0, MSEL4CR_16_1,
199 MSEL4CR_15_0, MSEL4CR_15_1,
200 MSEL4CR_14_0, MSEL4CR_14_1,
201 MSEL4CR_13_0, MSEL4CR_13_1,
202 MSEL4CR_12_0, MSEL4CR_12_1,
203 MSEL4CR_11_0, MSEL4CR_11_1,
204 MSEL4CR_10_0, MSEL4CR_10_1,
205 MSEL4CR_09_0, MSEL4CR_09_1,
206 MSEL4CR_07_0, MSEL4CR_07_1,
207 MSEL4CR_04_0, MSEL4CR_04_1,
208 MSEL4CR_01_0, MSEL4CR_01_1,
209
210 MSEL5CR_31_0, MSEL5CR_31_1,
211 MSEL5CR_30_0, MSEL5CR_30_1,
212 MSEL5CR_29_0, MSEL5CR_29_1,
213 MSEL5CR_28_0, MSEL5CR_28_1,
214 MSEL5CR_27_0, MSEL5CR_27_1,
215 MSEL5CR_26_0, MSEL5CR_26_1,
216 MSEL5CR_25_0, MSEL5CR_25_1,
217 MSEL5CR_24_0, MSEL5CR_24_1,
218 MSEL5CR_23_0, MSEL5CR_23_1,
219 MSEL5CR_22_0, MSEL5CR_22_1,
220 MSEL5CR_21_0, MSEL5CR_21_1,
221 MSEL5CR_20_0, MSEL5CR_20_1,
222 MSEL5CR_19_0, MSEL5CR_19_1,
223 MSEL5CR_18_0, MSEL5CR_18_1,
224 MSEL5CR_17_0, MSEL5CR_17_1,
225 MSEL5CR_16_0, MSEL5CR_16_1,
226 MSEL5CR_15_0, MSEL5CR_15_1,
227 MSEL5CR_14_0, MSEL5CR_14_1,
228 MSEL5CR_13_0, MSEL5CR_13_1,
229 MSEL5CR_12_0, MSEL5CR_12_1,
230 MSEL5CR_11_0, MSEL5CR_11_1,
231 MSEL5CR_10_0, MSEL5CR_10_1,
232 MSEL5CR_09_0, MSEL5CR_09_1,
233 MSEL5CR_08_0, MSEL5CR_08_1,
234 MSEL5CR_07_0, MSEL5CR_07_1,
235 MSEL5CR_06_0, MSEL5CR_06_1,
236
237 MSEL8CR_16_0, MSEL8CR_16_1,
238 MSEL8CR_01_0, MSEL8CR_01_1,
239 MSEL8CR_00_0, MSEL8CR_00_1,
240
241 PINMUX_FUNCTION_END,
242
243 PINMUX_MARK_BEGIN,
244
245
246#define F1(a) a##_MARK
247#define F2(a) a##_MARK
248#define F3(a) a##_MARK
249#define F4(a) a##_MARK
250#define F5(a) a##_MARK
251#define F6(a) a##_MARK
252#define F7(a) a##_MARK
253#define IRQ(a) IRQ##a##_MARK
254
255 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
256 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
257 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
258 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
259 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
260 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
261 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
262 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
263 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
264 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
265 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
266 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
267 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
268 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
269 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
270 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
271 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
272 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
273 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
274 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
275 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
276 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
277 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
278 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
279 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
280 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
281 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
282 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
283 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
284 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
285 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
286 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
287
288 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
289 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
290 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
291 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
292 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
293 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
294 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
295 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
296 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
297 F7(CHSCIF0_HSCK), /* Port40 */
298
299 F1(PDM0_DATA), /* Port64 */
300 F1(PDM1_DATA),
301 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
302 IRQ(40),
303 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
304 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
305 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
306 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
307 F7(CHSCIF1_HRTS), /* Port70 */
308 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
309 F7(CHSCIF1_HCTS),
310 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
311 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
312 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
313 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
314 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
315
316 F1(KEYIN0), /* Port96 */
317 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
318 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
319 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
320 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
321 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
322 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
323 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
324 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
325 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
326 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
327 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
328 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
329 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
330 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
331 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
332 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
333 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
334 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
335 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
336 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
337 F5(SIM0_VOLTSEL1), /* Port130 */
338 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
339 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
340 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
341 IRQ(20), /* Port160 */
342 IRQ(21), IRQ(22), IRQ(23),
343 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
344 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
345 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
346 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
347 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
348 F1(A9), F2(MMCD1_6), IRQ(32),
349 F1(A8), F2(MMCD1_5), IRQ(33),
350 F1(A7), F2(MMCD1_4), IRQ(34),
351 F1(A6), F2(MMCD1_3), IRQ(35),
352 F1(A5), F2(MMCD1_2), IRQ(36),
353 F1(A4), F2(MMCD1_1), IRQ(37),
354 F1(A3), F2(MMCD1_0), IRQ(38),
355 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
356 F1(A1),
357 F1(A0), F2(BS),
358 F1(CKO), F2(MMCCLK1),
359 F1(CS0_N), F5(SIM0_GPO1),
360 F1(CS2_N), F5(SIM0_GPO2),
361 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
362 F1(D15), F5(GIO_OUT15),
363 F1(D14), F5(GIO_OUT14),
364 F1(D13), F5(GIO_OUT13),
365 F1(D12), F5(GIO_OUT12), /* Port210 */
366 F1(D11), F5(WGM_TXP2),
367 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
368 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
369 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
370 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
371 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
372 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
373 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
374 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
375 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
376 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
377 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
378 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
379 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
380 F1(WE0_N), F2(RDWR_227),
381 F1(WE1_N), F5(SIM0_GPO0),
382 F1(PWMO), F2(VIO_CKO1_229),
383 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
384 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
385 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
386 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
387 F1(FSIAISLD), F2(PDM3_DATA_235),
388 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
389 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
390 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
391 F1(FSIBISLD), /* Port240 */
392 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
393 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
394 F1(FSIBCK), F3(ISP_SHUTTER0_245),
395 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
396 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
397 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
398 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
399 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
400 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
401 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
402 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
403 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
404 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
405 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
406 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
407 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
408 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
409 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
410 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
411 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
412 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
413 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
414 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
415 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
416 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
417 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
418 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
419 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
420 F4(MSIOF6_SS1), /* Port300 */
421 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
422 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
423 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
424 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
425 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
426 IRQ(55), IRQ(56), IRQ(57),
427 PINMUX_MARK_END,
428};
429
Laurent Pinchart533743d2013-07-15 13:03:20 +0200[diff] [blame]430static const u16 pinmux_data[] = {
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]431 /* specify valid pin states for each pin in GPIO mode */
Magnus Damm202ac6a2013-03-26 22:51:53 +0900[diff] [blame]432 PINMUX_DATA_ALL(),
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]433
434 /* Port0 */
435 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
436 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
437 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
438 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
439
440 /* Port1 */
441 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
442 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
443 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
444 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
445
446 /* Port2 */
447 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
448 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
449 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
450 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
451
452 /* Port3 */
453 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
454 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
455 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
456 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
457
458 /* Port4 */
459 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
460 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
461 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
462 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
463
464 /* Port5 */
465 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
466 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
467 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
468 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
469
470 /* Port6 */
471 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
472 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
473 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
474 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
475
476 /* Port7 */
477 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
478 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
479 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
480 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
481
482 /* Port8 */
483 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
484 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
485 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
486 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
487
488 /* Port9 */
489 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
490 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
491 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
492 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
493
494 /* Port10 */
495 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
496 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
497 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
498 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
499
500 /* Port11 */
501 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
502 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
503 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
504 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
505
506 /* Port12 */
507 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
508 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
509 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
510 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
511
512 /* Port13 */
513 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
514 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
515 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
516 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
517 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
518
519 /* Port14 */
520 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
521 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
522 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
523 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
524 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
525
526 /* Port15 */
527 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
528 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
529 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
530 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
531
532 /* Port16 */
533 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
534 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
535 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
536
537 /* Port17 */
538 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
539 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
540 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
541
542 /* Port18 */
543 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
544 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
545 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
546
547 /* Port19 */
548 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
549 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
550 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
551
552 /* Port20 */
553 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
554 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
555 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
556
557 /* Port21 */
558 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
559 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
560 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
561
562 /* Port22 */
563 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
564 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
565 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
566
567 /* Port23 */
568 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
569 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
570 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
571
572 /* Port24 */
573 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
574 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
575 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
576 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
577
578 /* Port25 */
579 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
580 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
581 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
582
583 /* Port26 */
584 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
585 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
586 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
587 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
588
589 /* Port27 */
590 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
591 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
592 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
593 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
594
595 /* Port28 */
596 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
597 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
598 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
599
600 /* Port29 */
601 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
602 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
603 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
604
605 /* Port30 */
606 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
607 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
608 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
609
610 /* Port32 */
611 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
612 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
613 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
614
615 /* Port33 */
616 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
617 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
618 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
619
620 /* Port34 */
621 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
622 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
623 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
624
625 /* Port35 */
626 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
627 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
628
629 /* Port36 */
630 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
631 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
632
633 /* Port37 */
634 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
635 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
636
637 /* Port38 */
638 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
639 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
640 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
641 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
642
643 /* Port39 */
644 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
645 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
646 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
647 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
648
649 /* Port40 */
650 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
651 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
652 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
653 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
654
655 /* Port64 */
656 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
657
658 /* Port65 */
659 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
660
661 /* Port66 */
662 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
663 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
664 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
665 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
666 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
667
668 /* Port67 */
669 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
670 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
671 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
672 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
673
674 /* Port68 */
675 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
676 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
677 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
678 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
679
680 /* Port69 */
681 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
682 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
683 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
684 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
685
686 /* Port70 */
687 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
688 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
689 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
690 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
691 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
692
693 /* Port71 */
694 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
695 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
696 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
697 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
698 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
699
700 /* Port72 */
701 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
702 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
703 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
704 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
705
706 /* Port73 */
707 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
708 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
709 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
710 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
711
712 /* Port74 - Port85 */
713 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
714 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
715 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
716 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
717 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
718 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
719 PINMUX_DATA(TXP_MARK, PORT80_FN1),
720 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
721 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
722 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
723 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
724 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
725
726 /* Port96 - Port101 */
727 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
728 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
729 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
730 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
731 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
732 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
733
734 /* Port102 */
735 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
736 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
737
738 /* Port103 */
739 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
740 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
741
742 /* Port104 - Port108 */
743 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
744 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
745 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
746 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
747 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
748
749 /* Port109 */
750 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
751 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
752
753 /* Port110 */
754 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
755 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
756
757 /* Port111 */
758 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
759 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
760 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
761
762 /* Port112 */
763 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
764 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
765 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
766 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
767
768 /* Port113 */
769 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
770 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
771 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
772 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
773
774 /* Port114 */
775 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
776 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
777 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
778 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
779
780 /* Port115 */
781 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
782 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
783 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
784 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
785
786 /* Port116 */
787 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
788 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
789
790 /* Port117 */
791 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
792 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
793
794 /* Port118 */
795 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
796 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
797
798 /* Port119 */
799 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
800 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
801
802 /* Port120 */
803 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
804 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
805 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
806
807 /* Port121 */
808 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
809 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
810
811 /* Port122 */
812 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
813 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
814
815 /* Port123 */
816 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
817 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
818
819 /* Port124 */
820 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
821
822 /* Port125 */
823 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
824 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
825 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
826 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
827
828 /* Port126 */
829 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
830 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
831 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
832
833 /* Port128 */
834 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
835 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
836 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
837 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
838
839 /* Port129 */
840 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
841 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
842 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
843
844 /* Port130 */
845 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
846 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
847 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
848 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
849
850 /* Port131 */
851 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
852 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
853
854 /* Port132 */
855 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
856 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
857 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
858
859 /* Port133 */
860 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
861 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
862 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
863 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
864
865 /* Port134 */
866 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
867 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
868 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
869
870 /* Port160 - Port178 */
871 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
872 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
873 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
874 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
875 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
876 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
877 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
878 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
879 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
880 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
881 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
882 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
883 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
884 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
885 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
886 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
887 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
888 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
889 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
890
891 /* Port192 - Port200 FN1 */
892 PINMUX_DATA(A10_MARK, PORT192_FN1),
893 PINMUX_DATA(A9_MARK, PORT193_FN1),
894 PINMUX_DATA(A8_MARK, PORT194_FN1),
895 PINMUX_DATA(A7_MARK, PORT195_FN1),
896 PINMUX_DATA(A6_MARK, PORT196_FN1),
897 PINMUX_DATA(A5_MARK, PORT197_FN1),
898 PINMUX_DATA(A4_MARK, PORT198_FN1),
899 PINMUX_DATA(A3_MARK, PORT199_FN1),
900 PINMUX_DATA(A2_MARK, PORT200_FN1),
901
902 /* Port192 - Port200 FN2 */
903 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
904 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
905 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
906 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
907 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
908 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
909 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
910 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
911 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
912
913 /* Port192 - Port200 IRQ */
914 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
915 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
916 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
917 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
918 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
919 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
920 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
921 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
922 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
923
924 /* Port201 */
925 PINMUX_DATA(A1_MARK, PORT201_FN1),
926
927 /* Port202 */
928 PINMUX_DATA(A0_MARK, PORT202_FN1),
929 PINMUX_DATA(BS_MARK, PORT202_FN2),
930
931 /* Port203 */
932 PINMUX_DATA(CKO_MARK, PORT203_FN1),
933 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
934
935 /* Port204 */
936 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
937 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
938
939 /* Port205 */
940 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
941 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
942
943 /* Port206 */
944 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
945 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
946 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
947
948 /* Port207 - Port212 FN1 */
949 PINMUX_DATA(D15_MARK, PORT207_FN1),
950 PINMUX_DATA(D14_MARK, PORT208_FN1),
951 PINMUX_DATA(D13_MARK, PORT209_FN1),
952 PINMUX_DATA(D12_MARK, PORT210_FN1),
953 PINMUX_DATA(D11_MARK, PORT211_FN1),
954 PINMUX_DATA(D10_MARK, PORT212_FN1),
955
956 /* Port207 - Port212 FN5 */
957 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
958 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
959 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
960 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
961 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
962 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
963
964 /* Port213 - Port222 FN1 */
965 PINMUX_DATA(D9_MARK, PORT213_FN1),
966 PINMUX_DATA(D8_MARK, PORT214_FN1),
967 PINMUX_DATA(D7_MARK, PORT215_FN1),
968 PINMUX_DATA(D6_MARK, PORT216_FN1),
969 PINMUX_DATA(D5_MARK, PORT217_FN1),
970 PINMUX_DATA(D4_MARK, PORT218_FN1),
971 PINMUX_DATA(D3_MARK, PORT219_FN1),
972 PINMUX_DATA(D2_MARK, PORT220_FN1),
973 PINMUX_DATA(D1_MARK, PORT221_FN1),
974 PINMUX_DATA(D0_MARK, PORT222_FN1),
975
976 /* Port213 - Port222 FN2 */
977 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
978 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
979 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
980 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
981 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
982 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
983 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
984 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
985 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
986 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
987
988 /* Port213 - Port222 FN5 */
989 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
990 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
991 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
992 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
993 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
994 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
995 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
996 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
997 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
998 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
999
1000 /* Port224 */
1001 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1002 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1003 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1004
1005 /* Port225 */
1006 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1007
1008 /* Port226 */
1009 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1010 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1011 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1012
1013 /* Port227 */
1014 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1015 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1016
1017 /* Port228 */
1018 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1019 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1020
1021 /* Port229 */
1022 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1023 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1024
1025 /* Port230 */
1026 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1027 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1028
1029 /* Port231 */
1030 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1031 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1032
1033 /* Port232 */
1034 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1035 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1036
1037 /* Port233 */
1038 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1039 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1040
1041 /* Port234 */
1042 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1043 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1044 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1045
1046 /* Port235 */
1047 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1048 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1049
1050 /* Port236 */
1051 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1052 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1053 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1054
1055 /* Port237 */
1056 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1057 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1058
1059 /* Port238 */
1060 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1061 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1062
1063 /* Port239 */
1064 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1065 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1066
1067 /* Port240 */
1068 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1069
1070 /* Port241 */
1071 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1072 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1073
1074 /* Port242 */
1075 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1076 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1077
1078 /* Port243 */
1079 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1080 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1081
1082 /* Port244 */
1083 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1084 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1085
1086 /* Port245 */
1087 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1088 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1089
1090 /* Port246 - Port250 FN1 */
1091 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1092 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1093 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1094 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1095 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1096
1097 /* Port256 - Port258 */
1098 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1099 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1100 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1101
1102 /* Port259 */
1103 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1104 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1105
1106 /* Port260 */
1107 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1108
1109 /* Port261 */
1110 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1111 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1112
1113 /* Port262 */
1114 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1115
1116 /* Port263 - Port266 FN1 */
1117 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1118 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1119 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1120 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1121
1122 /* Port263 - Port266 FN4 */
1123 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1124 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1125 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1126 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1127
1128 /* Port267 */
1129 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1130
1131 /* Port268 */
1132 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1133 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1134
1135 /* Port269 */
1136 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1137 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1138
1139 /* Port270 - Port273 FN1 */
1140 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1141 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1142 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1143 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1144
1145 /* Port270 - Port273 FN3 */
1146 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1147 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1148 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1149 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1150
1151 /* Port274 */
1152 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1153 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1154
1155 /* Port275 - Port280 */
1156 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1157 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1158 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1159 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1160 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1161 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1162
1163 /* Port281 */
1164 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1165 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1166
1167 /* Port282 */
1168 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1169 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1170
1171 /* Port283 */
1172 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1173
1174 /* Port289 */
1175 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1176 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1177
1178 /* Port290 */
1179 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1180 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1181 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1182
1183 /* Port291 - Port294 FN1 */
1184 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1185 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1186 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1187 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1188
1189 /* Port291 - Port294 FN3 */
1190 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1191 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1192 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1193 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1194
1195 /* Port295 */
1196 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1197 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1198 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1199 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1200
1201 /* Port296 */
1202 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1203 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1204 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1205
1206 /* Port297 - Port300 FN1 */
1207 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1208 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1209 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1210 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1211
1212 /* Port297 - Port300 FN2 */
1213 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1214 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1215 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1216 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1217
1218 /* Port297 - Port300 FN3 */
1219 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1220 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1221 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1222 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1223
1224 /* Port297 - Port300 FN4 */
1225 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1226 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1227 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1228 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1229
1230 /* Port301 */
1231 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1232 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1233
1234 /* Port302 - Port306 FN1 */
1235 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1236 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1237 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1238 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1239 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1240
1241 /* Port302 - Port306 FN3 */
1242 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1243 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1244 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1245 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1246 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1247
1248 /* Port307 */
1249 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1250
1251 /* Port308 */
1252 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1253 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1254
1255 /* Port320 - Port329 */
1256 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1257 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1258 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1259 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1260 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1261 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1262 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1263 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1264 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1265 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1266};
1267
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]1268#define __O (SH_PFC_PIN_CFG_OUTPUT)
1269#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1270#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1271
Laurent Pinchartdf020272013-07-15 17:42:48 +0200[diff] [blame]1272#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1273#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]1274
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1275static struct sh_pfc_pin pinmux_pins[] = {
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]1276 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1277 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1278 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1279 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1280 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1281 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1282 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1283 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1284 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1285 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1286 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1287 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1288 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1289 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1290 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1291 R8A73A4_PIN_IO_PU_PD(30),
1292 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1293 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1294 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1295 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1296 R8A73A4_PIN_IO_PU_PD(40),
1297 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1298 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1299 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1300 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1301 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1302 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1303 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1304 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1305 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1306 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1307 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1308 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1309 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1310 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1311 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1312 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1313 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1314 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1315 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1316 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1317 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1318 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1319 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1320 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1321 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1322 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1323 R8A73A4_PIN_IO_PU_PD(126),
1324 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1325 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1326 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1327 R8A73A4_PIN_IO_PU_PD(134),
1328 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1329 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1330 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1331 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1332 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1333 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1334 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1335 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1336 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1337 R8A73A4_PIN_IO_PU_PD(178),
1338 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1339 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1340 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1341 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1342 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1343 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1344 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1345 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1346 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1347 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1348 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1349 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1350 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1351 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1352 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1353 R8A73A4_PIN_IO_PU_PD(222),
1354 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1355 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1356 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1357 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1358 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1359 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1360 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1361 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1362 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1363 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1364 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1365 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1366 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1367 R8A73A4_PIN_IO_PU_PD(250),
1368 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1369 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1370 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1371 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1372 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1373 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1374 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1375 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1376 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1377 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1378 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1379 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1380 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1381 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1382 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1383 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1384 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1385 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1386 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1387 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1388 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1389 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1390 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1391 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1392 R8A73A4_PIN_IO_PU_PD(308),
1393 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1394 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1395 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1396 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1397 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1398};
1399
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame]1400/* - IRQC ------------------------------------------------------------------- */
1401#define IRQC_PINS_MUX(pin, irq_mark) \
1402static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1403 pin, \
1404}; \
1405static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1406 IRQ##irq_mark##_MARK, \
1407}
1408IRQC_PINS_MUX(0, 0);
1409IRQC_PINS_MUX(1, 1);
1410IRQC_PINS_MUX(2, 2);
1411IRQC_PINS_MUX(3, 3);
1412IRQC_PINS_MUX(4, 4);
1413IRQC_PINS_MUX(5, 5);
1414IRQC_PINS_MUX(6, 6);
1415IRQC_PINS_MUX(7, 7);
1416IRQC_PINS_MUX(8, 8);
1417IRQC_PINS_MUX(9, 9);
1418IRQC_PINS_MUX(10, 10);
1419IRQC_PINS_MUX(11, 11);
1420IRQC_PINS_MUX(12, 12);
1421IRQC_PINS_MUX(13, 13);
1422IRQC_PINS_MUX(14, 14);
1423IRQC_PINS_MUX(15, 15);
1424IRQC_PINS_MUX(66, 40);
1425IRQC_PINS_MUX(84, 19);
1426IRQC_PINS_MUX(85, 18);
1427IRQC_PINS_MUX(102, 41);
1428IRQC_PINS_MUX(103, 42);
1429IRQC_PINS_MUX(109, 43);
1430IRQC_PINS_MUX(110, 44);
1431IRQC_PINS_MUX(111, 45);
1432IRQC_PINS_MUX(112, 46);
1433IRQC_PINS_MUX(113, 47);
1434IRQC_PINS_MUX(114, 48);
1435IRQC_PINS_MUX(115, 49);
1436IRQC_PINS_MUX(160, 20);
1437IRQC_PINS_MUX(161, 21);
1438IRQC_PINS_MUX(162, 22);
1439IRQC_PINS_MUX(163, 23);
1440IRQC_PINS_MUX(175, 24);
1441IRQC_PINS_MUX(176, 25);
1442IRQC_PINS_MUX(177, 26);
1443IRQC_PINS_MUX(178, 27);
1444IRQC_PINS_MUX(192, 31);
1445IRQC_PINS_MUX(193, 32);
1446IRQC_PINS_MUX(194, 33);
1447IRQC_PINS_MUX(195, 34);
1448IRQC_PINS_MUX(196, 35);
1449IRQC_PINS_MUX(197, 36);
1450IRQC_PINS_MUX(198, 37);
1451IRQC_PINS_MUX(199, 38);
1452IRQC_PINS_MUX(200, 39);
1453IRQC_PINS_MUX(290, 51);
1454IRQC_PINS_MUX(296, 52);
1455IRQC_PINS_MUX(301, 50);
1456IRQC_PINS_MUX(320, 16);
1457IRQC_PINS_MUX(321, 17);
1458IRQC_PINS_MUX(322, 28);
1459IRQC_PINS_MUX(323, 29);
1460IRQC_PINS_MUX(324, 30);
1461IRQC_PINS_MUX(325, 53);
1462IRQC_PINS_MUX(326, 54);
1463IRQC_PINS_MUX(327, 55);
1464IRQC_PINS_MUX(328, 56);
1465IRQC_PINS_MUX(329, 57);
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]1466/* - MMCIF0 ----------------------------------------------------------------- */
1467static const unsigned int mmc0_data1_pins[] = {
1468 /* D[0] */
1469 164,
1470};
1471static const unsigned int mmc0_data1_mux[] = {
1472 MMCD0_0_MARK,
1473};
1474static const unsigned int mmc0_data4_pins[] = {
1475 /* D[0:3] */
1476 164, 165, 166, 167,
1477};
1478static const unsigned int mmc0_data4_mux[] = {
1479 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1480};
1481static const unsigned int mmc0_data8_pins[] = {
1482 /* D[0:7] */
1483 164, 165, 166, 167, 168, 169, 170, 171,
1484};
1485static const unsigned int mmc0_data8_mux[] = {
1486 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1487 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1488};
1489static const unsigned int mmc0_ctrl_pins[] = {
1490 /* CMD, CLK */
1491 172, 173,
1492};
1493static const unsigned int mmc0_ctrl_mux[] = {
1494 MMCCMD0_MARK, MMCCLK0_MARK,
1495};
1496/* - MMCIF1 ----------------------------------------------------------------- */
1497static const unsigned int mmc1_data1_pins[] = {
1498 /* D[0] */
1499 199,
1500};
1501static const unsigned int mmc1_data1_mux[] = {
1502 MMCD1_0_MARK,
1503};
1504static const unsigned int mmc1_data4_pins[] = {
1505 /* D[0:3] */
1506 199, 198, 197, 196,
1507};
1508static const unsigned int mmc1_data4_mux[] = {
1509 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1510};
1511static const unsigned int mmc1_data8_pins[] = {
1512 /* D[0:7] */
1513 199, 198, 197, 196, 195, 194, 193, 192,
1514};
1515static const unsigned int mmc1_data8_mux[] = {
1516 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1517 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1518};
1519static const unsigned int mmc1_ctrl_pins[] = {
1520 /* CMD, CLK */
1521 200, 203,
1522};
1523static const unsigned int mmc1_ctrl_mux[] = {
1524 MMCCMD1_MARK, MMCCLK1_MARK,
1525};
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1526/* - SCIFA0 ----------------------------------------------------------------- */
1527static const unsigned int scifa0_data_pins[] = {
1528 /* SCIFA0_RXD, SCIFA0_TXD */
1529 117, 116,
1530};
1531static const unsigned int scifa0_data_mux[] = {
1532 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1533};
1534static const unsigned int scifa0_clk_pins[] = {
1535 /* SCIFA0_SCK */
1536 34,
1537};
1538static const unsigned int scifa0_clk_mux[] = {
1539 SCIFA0_SCK_MARK,
1540};
1541static const unsigned int scifa0_ctrl_pins[] = {
1542 /* SCIFA0_RTS, SCIFA0_CTS */
1543 32, 33,
1544};
1545static const unsigned int scifa0_ctrl_mux[] = {
1546 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1547};
1548/* - SCIFA1 ----------------------------------------------------------------- */
1549static const unsigned int scifa1_data_pins[] = {
1550 /* SCIFA1_RXD, SCIFA1_TXD */
1551 119, 118,
1552};
1553static const unsigned int scifa1_data_mux[] = {
1554 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1555};
1556static const unsigned int scifa1_clk_pins[] = {
1557 /* SCIFA1_SCK */
1558 37,
1559};
1560static const unsigned int scifa1_clk_mux[] = {
1561 SCIFA1_SCK_MARK,
1562};
1563static const unsigned int scifa1_ctrl_pins[] = {
1564 /* SCIFA1_RTS, SCIFA1_CTS */
1565 35, 36,
1566};
1567static const unsigned int scifa1_ctrl_mux[] = {
1568 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1569};
1570/* - SCIFB0 ----------------------------------------------------------------- */
1571static const unsigned int scifb0_data_pins[] = {
1572 /* SCIFB0_RXD, SCIFB0_TXD */
1573 123, 122,
1574};
1575static const unsigned int scifb0_data_mux[] = {
1576 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1577};
1578static const unsigned int scifb0_clk_pins[] = {
1579 /* SCIFB0_SCK */
1580 40,
1581};
1582static const unsigned int scifb0_clk_mux[] = {
1583 SCIFB0_SCK_MARK,
1584};
1585static const unsigned int scifb0_ctrl_pins[] = {
1586 /* SCIFB0_RTS, SCIFB0_CTS */
1587 38, 39,
1588};
1589static const unsigned int scifb0_ctrl_mux[] = {
1590 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1591};
1592/* - SCIFB1 ----------------------------------------------------------------- */
1593static const unsigned int scifb1_data_pins[] = {
1594 /* SCIFB1_RXD, SCIFB1_TXD */
1595 27, 26,
1596};
1597static const unsigned int scifb1_data_mux[] = {
1598 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1599};
1600static const unsigned int scifb1_clk_pins[] = {
1601 /* SCIFB1_SCK */
1602 28,
1603};
1604static const unsigned int scifb1_clk_mux[] = {
1605 SCIFB1_SCK_28_MARK,
1606};
1607static const unsigned int scifb1_ctrl_pins[] = {
1608 /* SCIFB1_RTS, SCIFB1_CTS */
1609 24, 25,
1610};
1611static const unsigned int scifb1_ctrl_mux[] = {
1612 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1613};
1614static const unsigned int scifb1_data_b_pins[] = {
1615 /* SCIFB1_RXD, SCIFB1_TXD */
1616 72, 67,
1617};
1618static const unsigned int scifb1_data_b_mux[] = {
1619 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1620};
1621static const unsigned int scifb1_clk_b_pins[] = {
1622 /* SCIFB1_SCK */
1623 261,
1624};
1625static const unsigned int scifb1_clk_b_mux[] = {
1626 SCIFB1_SCK_261_MARK,
1627};
1628static const unsigned int scifb1_ctrl_b_pins[] = {
1629 /* SCIFB1_RTS, SCIFB1_CTS */
1630 70, 71,
1631};
1632static const unsigned int scifb1_ctrl_b_mux[] = {
1633 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1634};
1635/* - SCIFB2 ----------------------------------------------------------------- */
1636static const unsigned int scifb2_data_pins[] = {
1637 /* SCIFB2_RXD, SCIFB2_TXD */
1638 69, 68,
1639};
1640static const unsigned int scifb2_data_mux[] = {
1641 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1642};
1643static const unsigned int scifb2_clk_pins[] = {
1644 /* SCIFB2_SCK */
1645 262,
1646};
1647static const unsigned int scifb2_clk_mux[] = {
1648 SCIFB2_SCK_262_MARK,
1649};
1650static const unsigned int scifb2_ctrl_pins[] = {
1651 /* SCIFB2_RTS, SCIFB2_CTS */
1652 73, 66,
1653};
1654static const unsigned int scifb2_ctrl_mux[] = {
1655 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1656};
1657static const unsigned int scifb2_data_b_pins[] = {
1658 /* SCIFB2_RXD, SCIFB2_TXD */
1659 297, 295,
1660};
1661static const unsigned int scifb2_data_b_mux[] = {
1662 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1663};
1664static const unsigned int scifb2_clk_b_pins[] = {
1665 /* SCIFB2_SCK */
1666 299,
1667};
1668static const unsigned int scifb2_clk_b_mux[] = {
1669 SCIFB2_SCK_299_MARK,
1670};
1671static const unsigned int scifb2_ctrl_b_pins[] = {
1672 /* SCIFB2_RTS, SCIFB2_CTS */
1673 300, 298,
1674};
1675static const unsigned int scifb2_ctrl_b_mux[] = {
1676 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1677};
1678/* - SCIFB3 ----------------------------------------------------------------- */
1679static const unsigned int scifb3_data_pins[] = {
1680 /* SCIFB3_RXD, SCIFB3_TXD */
1681 22, 21,
1682};
1683static const unsigned int scifb3_data_mux[] = {
1684 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1685};
1686static const unsigned int scifb3_clk_pins[] = {
1687 /* SCIFB3_SCK */
1688 23,
1689};
1690static const unsigned int scifb3_clk_mux[] = {
1691 SCIFB3_SCK_23_MARK,
1692};
1693static const unsigned int scifb3_ctrl_pins[] = {
1694 /* SCIFB3_RTS, SCIFB3_CTS */
1695 19, 20,
1696};
1697static const unsigned int scifb3_ctrl_mux[] = {
1698 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1699};
1700static const unsigned int scifb3_data_b_pins[] = {
1701 /* SCIFB3_RXD, SCIFB3_TXD */
1702 120, 121,
1703};
1704static const unsigned int scifb3_data_b_mux[] = {
1705 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1706};
1707static const unsigned int scifb3_clk_b_pins[] = {
1708 /* SCIFB3_SCK */
1709 40,
1710};
1711static const unsigned int scifb3_clk_b_mux[] = {
1712 SCIFB3_SCK_40_MARK,
1713};
1714static const unsigned int scifb3_ctrl_b_pins[] = {
1715 /* SCIFB3_RTS, SCIFB3_CTS */
1716 38, 39,
1717};
1718static const unsigned int scifb3_ctrl_b_mux[] = {
1719 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1720};
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]1721/* - SDHI0 ------------------------------------------------------------------ */
1722static const unsigned int sdhi0_data1_pins[] = {
1723 /* D0 */
1724 302,
1725};
1726static const unsigned int sdhi0_data1_mux[] = {
1727 SDHID0_0_MARK,
1728};
1729static const unsigned int sdhi0_data4_pins[] = {
1730 /* D[0:3] */
1731 302, 303, 304, 305,
1732};
1733static const unsigned int sdhi0_data4_mux[] = {
1734 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1735};
1736static const unsigned int sdhi0_ctrl_pins[] = {
1737 /* CLK, CMD */
1738 308, 306,
1739};
1740static const unsigned int sdhi0_ctrl_mux[] = {
1741 SDHICLK0_MARK, SDHICMD0_MARK,
1742};
1743static const unsigned int sdhi0_cd_pins[] = {
1744 /* CD */
1745 301,
1746};
1747static const unsigned int sdhi0_cd_mux[] = {
1748 SDHICD0_MARK,
1749};
1750static const unsigned int sdhi0_wp_pins[] = {
1751 /* WP */
1752 307,
1753};
1754static const unsigned int sdhi0_wp_mux[] = {
1755 SDHIWP0_MARK,
1756};
1757/* - SDHI1 ------------------------------------------------------------------ */
1758static const unsigned int sdhi1_data1_pins[] = {
1759 /* D0 */
1760 289,
1761};
1762static const unsigned int sdhi1_data1_mux[] = {
1763 SDHID1_0_MARK,
1764};
1765static const unsigned int sdhi1_data4_pins[] = {
1766 /* D[0:3] */
1767 289, 290, 291, 292,
1768};
1769static const unsigned int sdhi1_data4_mux[] = {
1770 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1771};
1772static const unsigned int sdhi1_ctrl_pins[] = {
1773 /* CLK, CMD */
1774 293, 294,
1775};
1776static const unsigned int sdhi1_ctrl_mux[] = {
1777 SDHICLK1_MARK, SDHICMD1_MARK,
1778};
1779/* - SDHI2 ------------------------------------------------------------------ */
1780static const unsigned int sdhi2_data1_pins[] = {
1781 /* D0 */
1782 295,
1783};
1784static const unsigned int sdhi2_data1_mux[] = {
1785 SDHID2_0_MARK,
1786};
1787static const unsigned int sdhi2_data4_pins[] = {
1788 /* D[0:3] */
1789 295, 296, 297, 298,
1790};
1791static const unsigned int sdhi2_data4_mux[] = {
1792 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1793};
1794static const unsigned int sdhi2_ctrl_pins[] = {
1795 /* CLK, CMD */
1796 299, 300,
1797};
1798static const unsigned int sdhi2_ctrl_mux[] = {
1799 SDHICLK2_MARK, SDHICMD2_MARK,
1800};
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1801
1802static const struct sh_pfc_pin_group pinmux_groups[] = {
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame]1803 SH_PFC_PIN_GROUP(irqc_irq0),
1804 SH_PFC_PIN_GROUP(irqc_irq1),
1805 SH_PFC_PIN_GROUP(irqc_irq2),
1806 SH_PFC_PIN_GROUP(irqc_irq3),
1807 SH_PFC_PIN_GROUP(irqc_irq4),
1808 SH_PFC_PIN_GROUP(irqc_irq5),
1809 SH_PFC_PIN_GROUP(irqc_irq6),
1810 SH_PFC_PIN_GROUP(irqc_irq7),
1811 SH_PFC_PIN_GROUP(irqc_irq8),
1812 SH_PFC_PIN_GROUP(irqc_irq9),
1813 SH_PFC_PIN_GROUP(irqc_irq10),
1814 SH_PFC_PIN_GROUP(irqc_irq11),
1815 SH_PFC_PIN_GROUP(irqc_irq12),
1816 SH_PFC_PIN_GROUP(irqc_irq13),
1817 SH_PFC_PIN_GROUP(irqc_irq14),
1818 SH_PFC_PIN_GROUP(irqc_irq15),
1819 SH_PFC_PIN_GROUP(irqc_irq16),
1820 SH_PFC_PIN_GROUP(irqc_irq17),
1821 SH_PFC_PIN_GROUP(irqc_irq18),
1822 SH_PFC_PIN_GROUP(irqc_irq19),
1823 SH_PFC_PIN_GROUP(irqc_irq20),
1824 SH_PFC_PIN_GROUP(irqc_irq21),
1825 SH_PFC_PIN_GROUP(irqc_irq22),
1826 SH_PFC_PIN_GROUP(irqc_irq23),
1827 SH_PFC_PIN_GROUP(irqc_irq24),
1828 SH_PFC_PIN_GROUP(irqc_irq25),
1829 SH_PFC_PIN_GROUP(irqc_irq26),
1830 SH_PFC_PIN_GROUP(irqc_irq27),
1831 SH_PFC_PIN_GROUP(irqc_irq28),
1832 SH_PFC_PIN_GROUP(irqc_irq29),
1833 SH_PFC_PIN_GROUP(irqc_irq30),
1834 SH_PFC_PIN_GROUP(irqc_irq31),
1835 SH_PFC_PIN_GROUP(irqc_irq32),
1836 SH_PFC_PIN_GROUP(irqc_irq33),
1837 SH_PFC_PIN_GROUP(irqc_irq34),
1838 SH_PFC_PIN_GROUP(irqc_irq35),
1839 SH_PFC_PIN_GROUP(irqc_irq36),
1840 SH_PFC_PIN_GROUP(irqc_irq37),
1841 SH_PFC_PIN_GROUP(irqc_irq38),
1842 SH_PFC_PIN_GROUP(irqc_irq39),
1843 SH_PFC_PIN_GROUP(irqc_irq40),
1844 SH_PFC_PIN_GROUP(irqc_irq41),
1845 SH_PFC_PIN_GROUP(irqc_irq42),
1846 SH_PFC_PIN_GROUP(irqc_irq43),
1847 SH_PFC_PIN_GROUP(irqc_irq44),
1848 SH_PFC_PIN_GROUP(irqc_irq45),
1849 SH_PFC_PIN_GROUP(irqc_irq46),
1850 SH_PFC_PIN_GROUP(irqc_irq47),
1851 SH_PFC_PIN_GROUP(irqc_irq48),
1852 SH_PFC_PIN_GROUP(irqc_irq49),
1853 SH_PFC_PIN_GROUP(irqc_irq50),
1854 SH_PFC_PIN_GROUP(irqc_irq51),
1855 SH_PFC_PIN_GROUP(irqc_irq52),
1856 SH_PFC_PIN_GROUP(irqc_irq53),
1857 SH_PFC_PIN_GROUP(irqc_irq54),
1858 SH_PFC_PIN_GROUP(irqc_irq55),
1859 SH_PFC_PIN_GROUP(irqc_irq56),
1860 SH_PFC_PIN_GROUP(irqc_irq57),
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]1861 SH_PFC_PIN_GROUP(mmc0_data1),
1862 SH_PFC_PIN_GROUP(mmc0_data4),
1863 SH_PFC_PIN_GROUP(mmc0_data8),
1864 SH_PFC_PIN_GROUP(mmc0_ctrl),
1865 SH_PFC_PIN_GROUP(mmc1_data1),
1866 SH_PFC_PIN_GROUP(mmc1_data4),
1867 SH_PFC_PIN_GROUP(mmc1_data8),
1868 SH_PFC_PIN_GROUP(mmc1_ctrl),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1869 SH_PFC_PIN_GROUP(scifa0_data),
1870 SH_PFC_PIN_GROUP(scifa0_clk),
1871 SH_PFC_PIN_GROUP(scifa0_ctrl),
1872 SH_PFC_PIN_GROUP(scifa1_data),
1873 SH_PFC_PIN_GROUP(scifa1_clk),
1874 SH_PFC_PIN_GROUP(scifa1_ctrl),
1875 SH_PFC_PIN_GROUP(scifb0_data),
1876 SH_PFC_PIN_GROUP(scifb0_clk),
1877 SH_PFC_PIN_GROUP(scifb0_ctrl),
1878 SH_PFC_PIN_GROUP(scifb1_data),
1879 SH_PFC_PIN_GROUP(scifb1_clk),
1880 SH_PFC_PIN_GROUP(scifb1_ctrl),
1881 SH_PFC_PIN_GROUP(scifb1_data_b),
1882 SH_PFC_PIN_GROUP(scifb1_clk_b),
1883 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1884 SH_PFC_PIN_GROUP(scifb2_data),
1885 SH_PFC_PIN_GROUP(scifb2_clk),
1886 SH_PFC_PIN_GROUP(scifb2_ctrl),
1887 SH_PFC_PIN_GROUP(scifb2_data_b),
1888 SH_PFC_PIN_GROUP(scifb2_clk_b),
1889 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1890 SH_PFC_PIN_GROUP(scifb3_data),
1891 SH_PFC_PIN_GROUP(scifb3_clk),
1892 SH_PFC_PIN_GROUP(scifb3_ctrl),
1893 SH_PFC_PIN_GROUP(scifb3_data_b),
1894 SH_PFC_PIN_GROUP(scifb3_clk_b),
1895 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]1896 SH_PFC_PIN_GROUP(sdhi0_data1),
1897 SH_PFC_PIN_GROUP(sdhi0_data4),
1898 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1899 SH_PFC_PIN_GROUP(sdhi0_cd),
1900 SH_PFC_PIN_GROUP(sdhi0_wp),
1901 SH_PFC_PIN_GROUP(sdhi1_data1),
1902 SH_PFC_PIN_GROUP(sdhi1_data4),
1903 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1904 SH_PFC_PIN_GROUP(sdhi2_data1),
1905 SH_PFC_PIN_GROUP(sdhi2_data4),
1906 SH_PFC_PIN_GROUP(sdhi2_ctrl),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1907};
1908
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame]1909static const char * const irqc_groups[] = {
1910 "irqc_irq0",
1911 "irqc_irq1",
1912 "irqc_irq2",
1913 "irqc_irq3",
1914 "irqc_irq4",
1915 "irqc_irq5",
1916 "irqc_irq6",
1917 "irqc_irq7",
1918 "irqc_irq8",
1919 "irqc_irq9",
1920 "irqc_irq10",
1921 "irqc_irq11",
1922 "irqc_irq12",
1923 "irqc_irq13",
1924 "irqc_irq14",
1925 "irqc_irq15",
1926 "irqc_irq16",
1927 "irqc_irq17",
1928 "irqc_irq18",
1929 "irqc_irq19",
1930 "irqc_irq20",
1931 "irqc_irq21",
1932 "irqc_irq22",
1933 "irqc_irq23",
1934 "irqc_irq24",
1935 "irqc_irq25",
1936 "irqc_irq26",
1937 "irqc_irq27",
1938 "irqc_irq28",
1939 "irqc_irq29",
1940 "irqc_irq30",
1941 "irqc_irq31",
1942 "irqc_irq32",
1943 "irqc_irq33",
1944 "irqc_irq34",
1945 "irqc_irq35",
1946 "irqc_irq36",
1947 "irqc_irq37",
1948 "irqc_irq38",
1949 "irqc_irq39",
1950 "irqc_irq40",
1951 "irqc_irq41",
1952 "irqc_irq42",
1953 "irqc_irq43",
1954 "irqc_irq44",
1955 "irqc_irq45",
1956 "irqc_irq46",
1957 "irqc_irq47",
1958 "irqc_irq48",
1959 "irqc_irq49",
1960 "irqc_irq50",
1961 "irqc_irq51",
1962 "irqc_irq52",
1963 "irqc_irq53",
1964 "irqc_irq54",
1965 "irqc_irq55",
1966 "irqc_irq56",
1967 "irqc_irq57",
1968};
1969
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]1970static const char * const mmc0_groups[] = {
1971 "mmc0_data1",
1972 "mmc0_data4",
1973 "mmc0_data8",
1974 "mmc0_ctrl",
1975};
1976
1977static const char * const mmc1_groups[] = {
1978 "mmc1_data1",
1979 "mmc1_data4",
1980 "mmc1_data8",
1981 "mmc1_ctrl",
1982};
1983
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]1984static const char * const scifa0_groups[] = {
1985 "scifa0_data",
1986 "scifa0_clk",
1987 "scifa0_ctrl",
1988};
1989
1990static const char * const scifa1_groups[] = {
1991 "scifa1_data",
1992 "scifa1_clk",
1993 "scifa1_ctrl",
1994};
1995
1996static const char * const scifb0_groups[] = {
1997 "scifb0_data",
1998 "scifb0_clk",
1999 "scifb0_ctrl",
2000};
2001
2002static const char * const scifb1_groups[] = {
2003 "scifb1_data",
2004 "scifb1_clk",
2005 "scifb1_ctrl",
2006 "scifb1_data_b",
2007 "scifb1_clk_b",
2008 "scifb1_ctrl_b",
2009};
2010
2011static const char * const scifb2_groups[] = {
2012 "scifb2_data",
2013 "scifb2_clk",
2014 "scifb2_ctrl",
2015 "scifb2_data_b",
2016 "scifb2_clk_b",
2017 "scifb2_ctrl_b",
2018};
2019
2020static const char * const scifb3_groups[] = {
2021 "scifb3_data",
2022 "scifb3_clk",
2023 "scifb3_ctrl",
2024 "scifb3_data_b",
2025 "scifb3_clk_b",
2026 "scifb3_ctrl_b",
2027};
2028
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]2029static const char * const sdhi0_groups[] = {
2030 "sdhi0_data1",
2031 "sdhi0_data4",
2032 "sdhi0_ctrl",
2033 "sdhi0_cd",
2034 "sdhi0_wp",
2035};
2036
2037static const char * const sdhi1_groups[] = {
2038 "sdhi1_data1",
2039 "sdhi1_data4",
2040 "sdhi1_ctrl",
2041};
2042
2043static const char * const sdhi2_groups[] = {
2044 "sdhi2_data1",
2045 "sdhi2_data4",
2046 "sdhi2_ctrl",
2047};
2048
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]2049static const struct sh_pfc_function pinmux_functions[] = {
Magnus Damm515a8282013-03-28 00:16:37 +0900[diff] [blame]2050 SH_PFC_FUNCTION(irqc),
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]2051 SH_PFC_FUNCTION(mmc0),
2052 SH_PFC_FUNCTION(mmc1),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]2053 SH_PFC_FUNCTION(scifa0),
2054 SH_PFC_FUNCTION(scifa1),
2055 SH_PFC_FUNCTION(scifb0),
2056 SH_PFC_FUNCTION(scifb1),
2057 SH_PFC_FUNCTION(scifb2),
2058 SH_PFC_FUNCTION(scifb3),
Guennadi Liakhovetski6e8d1d42013-06-11 13:37:48 +0200[diff] [blame]2059 SH_PFC_FUNCTION(sdhi0),
2060 SH_PFC_FUNCTION(sdhi1),
2061 SH_PFC_FUNCTION(sdhi2),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]2062};
2063
Magnus Damm202ac6a2013-03-26 22:51:53 +0900[diff] [blame]2064#undef PORTCR
2065#define PORTCR(nr, reg) \
2066 { \
2067 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2068 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2069 PORT##nr##_FN0, PORT##nr##_FN1, \
2070 PORT##nr##_FN2, PORT##nr##_FN3, \
2071 PORT##nr##_FN4, PORT##nr##_FN5, \
2072 PORT##nr##_FN6, PORT##nr##_FN7 } \
2073 }
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2074
Magnus Damm202ac6a2013-03-26 22:51:53 +0900[diff] [blame]2075static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2076 PORTCR(0, 0xe6050000),
2077 PORTCR(1, 0xe6050001),
2078 PORTCR(2, 0xe6050002),
2079 PORTCR(3, 0xe6050003),
2080 PORTCR(4, 0xe6050004),
2081 PORTCR(5, 0xe6050005),
2082 PORTCR(6, 0xe6050006),
2083 PORTCR(7, 0xe6050007),
2084 PORTCR(8, 0xe6050008),
2085 PORTCR(9, 0xe6050009),
2086 PORTCR(10, 0xe605000A),
2087 PORTCR(11, 0xe605000B),
2088 PORTCR(12, 0xe605000C),
2089 PORTCR(13, 0xe605000D),
2090 PORTCR(14, 0xe605000E),
2091 PORTCR(15, 0xe605000F),
2092 PORTCR(16, 0xe6050010),
2093 PORTCR(17, 0xe6050011),
2094 PORTCR(18, 0xe6050012),
2095 PORTCR(19, 0xe6050013),
2096 PORTCR(20, 0xe6050014),
2097 PORTCR(21, 0xe6050015),
2098 PORTCR(22, 0xe6050016),
2099 PORTCR(23, 0xe6050017),
2100 PORTCR(24, 0xe6050018),
2101 PORTCR(25, 0xe6050019),
2102 PORTCR(26, 0xe605001A),
2103 PORTCR(27, 0xe605001B),
2104 PORTCR(28, 0xe605001C),
2105 PORTCR(29, 0xe605001D),
2106 PORTCR(30, 0xe605001E),
2107 PORTCR(32, 0xe6051020),
2108 PORTCR(33, 0xe6051021),
2109 PORTCR(34, 0xe6051022),
2110 PORTCR(35, 0xe6051023),
2111 PORTCR(36, 0xe6051024),
2112 PORTCR(37, 0xe6051025),
2113 PORTCR(38, 0xe6051026),
2114 PORTCR(39, 0xe6051027),
2115 PORTCR(40, 0xe6051028),
2116 PORTCR(64, 0xe6050040),
2117 PORTCR(65, 0xe6050041),
2118 PORTCR(66, 0xe6050042),
2119 PORTCR(67, 0xe6050043),
2120 PORTCR(68, 0xe6050044),
2121 PORTCR(69, 0xe6050045),
2122 PORTCR(70, 0xe6050046),
2123 PORTCR(71, 0xe6050047),
2124 PORTCR(72, 0xe6050048),
2125 PORTCR(73, 0xe6050049),
2126 PORTCR(74, 0xe605004A),
2127 PORTCR(75, 0xe605004B),
2128 PORTCR(76, 0xe605004C),
2129 PORTCR(77, 0xe605004D),
2130 PORTCR(78, 0xe605004E),
2131 PORTCR(79, 0xe605004F),
2132 PORTCR(80, 0xe6050050),
2133 PORTCR(81, 0xe6050051),
2134 PORTCR(82, 0xe6050052),
2135 PORTCR(83, 0xe6050053),
2136 PORTCR(84, 0xe6050054),
2137 PORTCR(85, 0xe6050055),
2138 PORTCR(96, 0xe6051060),
2139 PORTCR(97, 0xe6051061),
2140 PORTCR(98, 0xe6051062),
2141 PORTCR(99, 0xe6051063),
2142 PORTCR(100, 0xe6051064),
2143 PORTCR(101, 0xe6051065),
2144 PORTCR(102, 0xe6051066),
2145 PORTCR(103, 0xe6051067),
2146 PORTCR(104, 0xe6051068),
2147 PORTCR(105, 0xe6051069),
2148 PORTCR(106, 0xe605106A),
2149 PORTCR(107, 0xe605106B),
2150 PORTCR(108, 0xe605106C),
2151 PORTCR(109, 0xe605106D),
2152 PORTCR(110, 0xe605106E),
2153 PORTCR(111, 0xe605106F),
2154 PORTCR(112, 0xe6051070),
2155 PORTCR(113, 0xe6051071),
2156 PORTCR(114, 0xe6051072),
2157 PORTCR(115, 0xe6051073),
2158 PORTCR(116, 0xe6051074),
2159 PORTCR(117, 0xe6051075),
2160 PORTCR(118, 0xe6051076),
2161 PORTCR(119, 0xe6051077),
2162 PORTCR(120, 0xe6051078),
2163 PORTCR(121, 0xe6051079),
2164 PORTCR(122, 0xe605107A),
2165 PORTCR(123, 0xe605107B),
2166 PORTCR(124, 0xe605107C),
2167 PORTCR(125, 0xe605107D),
2168 PORTCR(126, 0xe605107E),
2169 PORTCR(128, 0xe6051080),
2170 PORTCR(129, 0xe6051081),
2171 PORTCR(130, 0xe6051082),
2172 PORTCR(131, 0xe6051083),
2173 PORTCR(132, 0xe6051084),
2174 PORTCR(133, 0xe6051085),
2175 PORTCR(134, 0xe6051086),
2176 PORTCR(160, 0xe60520A0),
2177 PORTCR(161, 0xe60520A1),
2178 PORTCR(162, 0xe60520A2),
2179 PORTCR(163, 0xe60520A3),
2180 PORTCR(164, 0xe60520A4),
2181 PORTCR(165, 0xe60520A5),
2182 PORTCR(166, 0xe60520A6),
2183 PORTCR(167, 0xe60520A7),
2184 PORTCR(168, 0xe60520A8),
2185 PORTCR(169, 0xe60520A9),
2186 PORTCR(170, 0xe60520AA),
2187 PORTCR(171, 0xe60520AB),
2188 PORTCR(172, 0xe60520AC),
2189 PORTCR(173, 0xe60520AD),
2190 PORTCR(174, 0xe60520AE),
2191 PORTCR(175, 0xe60520AF),
2192 PORTCR(176, 0xe60520B0),
2193 PORTCR(177, 0xe60520B1),
2194 PORTCR(178, 0xe60520B2),
2195 PORTCR(192, 0xe60520C0),
2196 PORTCR(193, 0xe60520C1),
2197 PORTCR(194, 0xe60520C2),
2198 PORTCR(195, 0xe60520C3),
2199 PORTCR(196, 0xe60520C4),
2200 PORTCR(197, 0xe60520C5),
2201 PORTCR(198, 0xe60520C6),
2202 PORTCR(199, 0xe60520C7),
2203 PORTCR(200, 0xe60520C8),
2204 PORTCR(201, 0xe60520C9),
2205 PORTCR(202, 0xe60520CA),
2206 PORTCR(203, 0xe60520CB),
2207 PORTCR(204, 0xe60520CC),
2208 PORTCR(205, 0xe60520CD),
2209 PORTCR(206, 0xe60520CE),
2210 PORTCR(207, 0xe60520CF),
2211 PORTCR(208, 0xe60520D0),
2212 PORTCR(209, 0xe60520D1),
2213 PORTCR(210, 0xe60520D2),
2214 PORTCR(211, 0xe60520D3),
2215 PORTCR(212, 0xe60520D4),
2216 PORTCR(213, 0xe60520D5),
2217 PORTCR(214, 0xe60520D6),
2218 PORTCR(215, 0xe60520D7),
2219 PORTCR(216, 0xe60520D8),
2220 PORTCR(217, 0xe60520D9),
2221 PORTCR(218, 0xe60520DA),
2222 PORTCR(219, 0xe60520DB),
2223 PORTCR(220, 0xe60520DC),
2224 PORTCR(221, 0xe60520DD),
2225 PORTCR(222, 0xe60520DE),
2226 PORTCR(224, 0xe60520E0),
2227 PORTCR(225, 0xe60520E1),
2228 PORTCR(226, 0xe60520E2),
2229 PORTCR(227, 0xe60520E3),
2230 PORTCR(228, 0xe60520E4),
2231 PORTCR(229, 0xe60520E5),
2232 PORTCR(230, 0xe60520e6),
2233 PORTCR(231, 0xe60520E7),
2234 PORTCR(232, 0xe60520E8),
2235 PORTCR(233, 0xe60520E9),
2236 PORTCR(234, 0xe60520EA),
2237 PORTCR(235, 0xe60520EB),
2238 PORTCR(236, 0xe60520EC),
2239 PORTCR(237, 0xe60520ED),
2240 PORTCR(238, 0xe60520EE),
2241 PORTCR(239, 0xe60520EF),
2242 PORTCR(240, 0xe60520F0),
2243 PORTCR(241, 0xe60520F1),
2244 PORTCR(242, 0xe60520F2),
2245 PORTCR(243, 0xe60520F3),
2246 PORTCR(244, 0xe60520F4),
2247 PORTCR(245, 0xe60520F5),
2248 PORTCR(246, 0xe60520F6),
2249 PORTCR(247, 0xe60520F7),
2250 PORTCR(248, 0xe60520F8),
2251 PORTCR(249, 0xe60520F9),
2252 PORTCR(250, 0xe60520FA),
2253 PORTCR(256, 0xe6052100),
2254 PORTCR(257, 0xe6052101),
2255 PORTCR(258, 0xe6052102),
2256 PORTCR(259, 0xe6052103),
2257 PORTCR(260, 0xe6052104),
2258 PORTCR(261, 0xe6052105),
2259 PORTCR(262, 0xe6052106),
2260 PORTCR(263, 0xe6052107),
2261 PORTCR(264, 0xe6052108),
2262 PORTCR(265, 0xe6052109),
2263 PORTCR(266, 0xe605210A),
2264 PORTCR(267, 0xe605210B),
2265 PORTCR(268, 0xe605210C),
2266 PORTCR(269, 0xe605210D),
2267 PORTCR(270, 0xe605210E),
2268 PORTCR(271, 0xe605210F),
2269 PORTCR(272, 0xe6052110),
2270 PORTCR(273, 0xe6052111),
2271 PORTCR(274, 0xe6052112),
2272 PORTCR(275, 0xe6052113),
2273 PORTCR(276, 0xe6052114),
2274 PORTCR(277, 0xe6052115),
2275 PORTCR(278, 0xe6052116),
2276 PORTCR(279, 0xe6052117),
2277 PORTCR(280, 0xe6052118),
2278 PORTCR(281, 0xe6052119),
2279 PORTCR(282, 0xe605211A),
2280 PORTCR(283, 0xe605211B),
2281 PORTCR(288, 0xe6053120),
2282 PORTCR(289, 0xe6053121),
2283 PORTCR(290, 0xe6053122),
2284 PORTCR(291, 0xe6053123),
2285 PORTCR(292, 0xe6053124),
2286 PORTCR(293, 0xe6053125),
2287 PORTCR(294, 0xe6053126),
2288 PORTCR(295, 0xe6053127),
2289 PORTCR(296, 0xe6053128),
2290 PORTCR(297, 0xe6053129),
2291 PORTCR(298, 0xe605312A),
2292 PORTCR(299, 0xe605312B),
2293 PORTCR(300, 0xe605312C),
2294 PORTCR(301, 0xe605312D),
2295 PORTCR(302, 0xe605312E),
2296 PORTCR(303, 0xe605312F),
2297 PORTCR(304, 0xe6053130),
2298 PORTCR(305, 0xe6053131),
2299 PORTCR(306, 0xe6053132),
2300 PORTCR(307, 0xe6053133),
2301 PORTCR(308, 0xe6053134),
2302 PORTCR(320, 0xe6053140),
2303 PORTCR(321, 0xe6053141),
2304 PORTCR(322, 0xe6053142),
2305 PORTCR(323, 0xe6053143),
2306 PORTCR(324, 0xe6053144),
2307 PORTCR(325, 0xe6053145),
2308 PORTCR(326, 0xe6053146),
2309 PORTCR(327, 0xe6053147),
2310 PORTCR(328, 0xe6053148),
2311 PORTCR(329, 0xe6053149),
2312
2313 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2314 MSEL1CR_31_0, MSEL1CR_31_1,
2315 0, 0,
2316 0, 0,
2317 0, 0,
2318 MSEL1CR_27_0, MSEL1CR_27_1,
2319 0, 0,
2320 MSEL1CR_25_0, MSEL1CR_25_1,
2321 MSEL1CR_24_0, MSEL1CR_24_1,
2322 0, 0,
2323 MSEL1CR_22_0, MSEL1CR_22_1,
2324 MSEL1CR_21_0, MSEL1CR_21_1,
2325 MSEL1CR_20_0, MSEL1CR_20_1,
2326 MSEL1CR_19_0, MSEL1CR_19_1,
2327 MSEL1CR_18_0, MSEL1CR_18_1,
2328 MSEL1CR_17_0, MSEL1CR_17_1,
2329 MSEL1CR_16_0, MSEL1CR_16_1,
2330 MSEL1CR_15_0, MSEL1CR_15_1,
2331 MSEL1CR_14_0, MSEL1CR_14_1,
2332 MSEL1CR_13_0, MSEL1CR_13_1,
2333 MSEL1CR_12_0, MSEL1CR_12_1,
2334 MSEL1CR_11_0, MSEL1CR_11_1,
2335 MSEL1CR_10_0, MSEL1CR_10_1,
2336 MSEL1CR_09_0, MSEL1CR_09_1,
2337 MSEL1CR_08_0, MSEL1CR_08_1,
2338 MSEL1CR_07_0, MSEL1CR_07_1,
2339 MSEL1CR_06_0, MSEL1CR_06_1,
2340 MSEL1CR_05_0, MSEL1CR_05_1,
2341 MSEL1CR_04_0, MSEL1CR_04_1,
2342 MSEL1CR_03_0, MSEL1CR_03_1,
2343 MSEL1CR_02_0, MSEL1CR_02_1,
2344 MSEL1CR_01_0, MSEL1CR_01_1,
2345 MSEL1CR_00_0, MSEL1CR_00_1,
2346 }
2347 },
2348 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2349 MSEL3CR_31_0, MSEL3CR_31_1,
2350 0, 0,
2351 0, 0,
2352 MSEL3CR_28_0, MSEL3CR_28_1,
2353 MSEL3CR_27_0, MSEL3CR_27_1,
2354 MSEL3CR_26_0, MSEL3CR_26_1,
2355 0, 0,
2356 0, 0,
2357 MSEL3CR_23_0, MSEL3CR_23_1,
2358 MSEL3CR_22_0, MSEL3CR_22_1,
2359 MSEL3CR_21_0, MSEL3CR_21_1,
2360 MSEL3CR_20_0, MSEL3CR_20_1,
2361 MSEL3CR_19_0, MSEL3CR_19_1,
2362 MSEL3CR_18_0, MSEL3CR_18_1,
2363 MSEL3CR_17_0, MSEL3CR_17_1,
2364 MSEL3CR_16_0, MSEL3CR_16_1,
2365 MSEL3CR_15_0, MSEL3CR_15_1,
2366 0, 0,
2367 0, 0,
2368 MSEL3CR_12_0, MSEL3CR_12_1,
2369 MSEL3CR_11_0, MSEL3CR_11_1,
2370 MSEL3CR_10_0, MSEL3CR_10_1,
2371 MSEL3CR_09_0, MSEL3CR_09_1,
2372 0, 0,
2373 0, 0,
2374 MSEL3CR_06_0, MSEL3CR_06_1,
2375 0, 0,
2376 0, 0,
2377 MSEL3CR_03_0, MSEL3CR_03_1,
2378 0, 0,
2379 MSEL3CR_01_0, MSEL3CR_01_1,
2380 MSEL3CR_00_0, MSEL3CR_00_1,
2381 }
2382 },
2383 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2384 0, 0,
2385 MSEL4CR_30_0, MSEL4CR_30_1,
2386 MSEL4CR_29_0, MSEL4CR_29_1,
2387 MSEL4CR_28_0, MSEL4CR_28_1,
2388 MSEL4CR_27_0, MSEL4CR_27_1,
2389 MSEL4CR_26_0, MSEL4CR_26_1,
2390 MSEL4CR_25_0, MSEL4CR_25_1,
2391 MSEL4CR_24_0, MSEL4CR_24_1,
2392 MSEL4CR_23_0, MSEL4CR_23_1,
2393 MSEL4CR_22_0, MSEL4CR_22_1,
2394 MSEL4CR_21_0, MSEL4CR_21_1,
2395 MSEL4CR_20_0, MSEL4CR_20_1,
2396 MSEL4CR_19_0, MSEL4CR_19_1,
2397 MSEL4CR_18_0, MSEL4CR_18_1,
2398 MSEL4CR_17_0, MSEL4CR_17_1,
2399 MSEL4CR_16_0, MSEL4CR_16_1,
2400 MSEL4CR_15_0, MSEL4CR_15_1,
2401 MSEL4CR_14_0, MSEL4CR_14_1,
2402 MSEL4CR_13_0, MSEL4CR_13_1,
2403 MSEL4CR_12_0, MSEL4CR_12_1,
2404 MSEL4CR_11_0, MSEL4CR_11_1,
2405 MSEL4CR_10_0, MSEL4CR_10_1,
2406 MSEL4CR_09_0, MSEL4CR_09_1,
2407 0, 0,
2408 MSEL4CR_07_0, MSEL4CR_07_1,
2409 0, 0,
2410 0, 0,
2411 MSEL4CR_04_0, MSEL4CR_04_1,
2412 0, 0,
2413 0, 0,
2414 MSEL4CR_01_0, MSEL4CR_01_1,
2415 0, 0,
2416 }
2417 },
2418 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2419 MSEL5CR_31_0, MSEL5CR_31_1,
2420 MSEL5CR_30_0, MSEL5CR_30_1,
2421 MSEL5CR_29_0, MSEL5CR_29_1,
2422 MSEL5CR_28_0, MSEL5CR_28_1,
2423 MSEL5CR_27_0, MSEL5CR_27_1,
2424 MSEL5CR_26_0, MSEL5CR_26_1,
2425 MSEL5CR_25_0, MSEL5CR_25_1,
2426 MSEL5CR_24_0, MSEL5CR_24_1,
2427 MSEL5CR_23_0, MSEL5CR_23_1,
2428 MSEL5CR_22_0, MSEL5CR_22_1,
2429 MSEL5CR_21_0, MSEL5CR_21_1,
2430 MSEL5CR_20_0, MSEL5CR_20_1,
2431 MSEL5CR_19_0, MSEL5CR_19_1,
2432 MSEL5CR_18_0, MSEL5CR_18_1,
2433 MSEL5CR_17_0, MSEL5CR_17_1,
2434 MSEL5CR_16_0, MSEL5CR_16_1,
2435 MSEL5CR_15_0, MSEL5CR_15_1,
2436 MSEL5CR_14_0, MSEL5CR_14_1,
2437 MSEL5CR_13_0, MSEL5CR_13_1,
2438 MSEL5CR_12_0, MSEL5CR_12_1,
2439 MSEL5CR_11_0, MSEL5CR_11_1,
2440 MSEL5CR_10_0, MSEL5CR_10_1,
2441 MSEL5CR_09_0, MSEL5CR_09_1,
2442 MSEL5CR_08_0, MSEL5CR_08_1,
2443 MSEL5CR_07_0, MSEL5CR_07_1,
2444 MSEL5CR_06_0, MSEL5CR_06_1,
2445 0, 0,
2446 0, 0,
2447 0, 0,
2448 0, 0,
2449 0, 0,
2450 0, 0,
2451 }
2452 },
2453 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2454 0, 0,
2455 0, 0,
2456 0, 0,
2457 0, 0,
2458 0, 0,
2459 0, 0,
2460 0, 0,
2461 0, 0,
2462 0, 0,
2463 0, 0,
2464 0, 0,
2465 0, 0,
2466 0, 0,
2467 0, 0,
2468 0, 0,
2469 MSEL8CR_16_0, MSEL8CR_16_1,
2470 0, 0,
2471 0, 0,
2472 0, 0,
2473 0, 0,
2474 0, 0,
2475 0, 0,
2476 0, 0,
2477 0, 0,
2478 0, 0,
2479 0, 0,
2480 0, 0,
2481 0, 0,
2482 0, 0,
2483 0, 0,
2484 MSEL8CR_01_0, MSEL8CR_01_1,
2485 MSEL8CR_00_0, MSEL8CR_00_1,
2486 }
2487 },
2488 { },
2489};
2490
2491static const struct pinmux_data_reg pinmux_data_regs[] = {
2492
2493 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2494 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2495 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2496 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2497 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2498 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2499 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2500 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2501 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2502 }
2503 },
2504 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2505 0, 0, 0, 0,
2506 0, 0, 0, 0,
2507 0, 0, 0, 0,
2508 0, 0, 0, 0,
2509 0, 0, 0, 0,
2510 0, 0, 0, PORT40_DATA,
2511 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2512 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2513 }
2514 },
2515 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2516 0, 0, 0, 0,
2517 0, 0, 0, 0,
2518 0, 0, PORT85_DATA, PORT84_DATA,
2519 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2520 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2521 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2522 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2523 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2524 }
2525 },
2526 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2527 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2528 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2529 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2530 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2531 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2532 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2533 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2534 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2535 }
2536 },
2537 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2538 0, 0, 0, 0,
2539 0, 0, 0, 0,
2540 0, 0, 0, 0,
2541 0, 0, 0, 0,
2542 0, 0, 0, 0,
2543 0, 0, 0, 0,
2544 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2545 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2546 }
2547 },
2548 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2549 0, 0, 0, 0,
2550 0, 0, 0, 0,
2551 0, 0, 0, 0,
2552 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2553 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2554 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2555 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2556 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2557 }
2558 },
2559 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2560 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2561 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2562 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2563 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2564 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2565 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2566 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2567 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2568 }
2569 },
2570 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2571 0, 0, 0, 0,
2572 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2573 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2574 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2575 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2576 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2577 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2578 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2579 }
2580 },
2581 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2582 0, 0, 0, 0,
2583 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2584 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2585 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2586 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2587 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2588 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2589 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2590 }
2591 },
2592 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2593 0, 0, 0, 0,
2594 0, 0, 0, 0,
2595 0, 0, 0, PORT308_DATA,
2596 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2597 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2598 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2599 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2600 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2601 }
2602 },
2603 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2604 0, 0, 0, 0,
2605 0, 0, 0, 0,
2606 0, 0, 0, 0,
2607 0, 0, 0, 0,
2608 0, 0, 0, 0,
2609 0, 0, PORT329_DATA, PORT328_DATA,
2610 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2611 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2612 }
2613 },
2614 { },
2615};
2616
Magnus Dammc96931c2013-03-26 22:50:09 +0900[diff] [blame]2617static const struct pinmux_irq pinmux_irqs[] = {
2618 PINMUX_IRQ(irq_pin(0), 0),
2619 PINMUX_IRQ(irq_pin(1), 1),
2620 PINMUX_IRQ(irq_pin(2), 2),
2621 PINMUX_IRQ(irq_pin(3), 3),
2622 PINMUX_IRQ(irq_pin(4), 4),
2623 PINMUX_IRQ(irq_pin(5), 5),
2624 PINMUX_IRQ(irq_pin(6), 6),
2625 PINMUX_IRQ(irq_pin(7), 7),
2626 PINMUX_IRQ(irq_pin(8), 8),
2627 PINMUX_IRQ(irq_pin(9), 9),
2628 PINMUX_IRQ(irq_pin(10), 10),
2629 PINMUX_IRQ(irq_pin(11), 11),
2630 PINMUX_IRQ(irq_pin(12), 12),
2631 PINMUX_IRQ(irq_pin(13), 13),
2632 PINMUX_IRQ(irq_pin(14), 14),
2633 PINMUX_IRQ(irq_pin(15), 15),
2634 PINMUX_IRQ(irq_pin(16), 320),
2635 PINMUX_IRQ(irq_pin(17), 321),
2636 PINMUX_IRQ(irq_pin(18), 85),
2637 PINMUX_IRQ(irq_pin(19), 84),
2638 PINMUX_IRQ(irq_pin(20), 160),
2639 PINMUX_IRQ(irq_pin(21), 161),
2640 PINMUX_IRQ(irq_pin(22), 162),
2641 PINMUX_IRQ(irq_pin(23), 163),
2642 PINMUX_IRQ(irq_pin(24), 175),
2643 PINMUX_IRQ(irq_pin(25), 176),
2644 PINMUX_IRQ(irq_pin(26), 177),
2645 PINMUX_IRQ(irq_pin(27), 178),
2646 PINMUX_IRQ(irq_pin(28), 322),
2647 PINMUX_IRQ(irq_pin(29), 323),
2648 PINMUX_IRQ(irq_pin(30), 324),
2649 PINMUX_IRQ(irq_pin(31), 192),
2650 PINMUX_IRQ(irq_pin(32), 193),
2651 PINMUX_IRQ(irq_pin(33), 194),
2652 PINMUX_IRQ(irq_pin(34), 195),
2653 PINMUX_IRQ(irq_pin(35), 196),
2654 PINMUX_IRQ(irq_pin(36), 197),
2655 PINMUX_IRQ(irq_pin(37), 198),
2656 PINMUX_IRQ(irq_pin(38), 199),
2657 PINMUX_IRQ(irq_pin(39), 200),
2658 PINMUX_IRQ(irq_pin(40), 66),
2659 PINMUX_IRQ(irq_pin(41), 102),
2660 PINMUX_IRQ(irq_pin(42), 103),
2661 PINMUX_IRQ(irq_pin(43), 109),
2662 PINMUX_IRQ(irq_pin(44), 110),
2663 PINMUX_IRQ(irq_pin(45), 111),
2664 PINMUX_IRQ(irq_pin(46), 112),
2665 PINMUX_IRQ(irq_pin(47), 113),
2666 PINMUX_IRQ(irq_pin(48), 114),
2667 PINMUX_IRQ(irq_pin(49), 115),
2668 PINMUX_IRQ(irq_pin(50), 301),
2669 PINMUX_IRQ(irq_pin(51), 290),
2670 PINMUX_IRQ(irq_pin(52), 296),
2671 PINMUX_IRQ(irq_pin(53), 325),
2672 PINMUX_IRQ(irq_pin(54), 326),
2673 PINMUX_IRQ(irq_pin(55), 327),
2674 PINMUX_IRQ(irq_pin(56), 328),
2675 PINMUX_IRQ(irq_pin(57), 329),
2676};
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]2677
2678#define PORTCR_PULMD_OFF (0 << 6)
2679#define PORTCR_PULMD_DOWN (2 << 6)
2680#define PORTCR_PULMD_UP (3 << 6)
2681#define PORTCR_PULMD_MASK (3 << 6)
2682
2683static const unsigned int r8a73a4_portcr_offsets[] = {
2684 0x00000000, 0x00001000, 0x00000000, 0x00001000,
2685 0x00001000, 0x00002000, 0x00002000, 0x00002000,
2686 0x00002000, 0x00003000, 0x00003000,
2687};
2688
2689static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2690 unsigned int pin)
2691{
2692 void __iomem *addr;
2693
2694 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2695
2696 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2697 case PORTCR_PULMD_UP:
2698 return PIN_CONFIG_BIAS_PULL_UP;
2699 case PORTCR_PULMD_DOWN:
2700 return PIN_CONFIG_BIAS_PULL_DOWN;
2701 case PORTCR_PULMD_OFF:
2702 default:
2703 return PIN_CONFIG_BIAS_DISABLE;
2704 }
2705}
2706
2707static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2708 unsigned int bias)
2709{
2710 void __iomem *addr;
2711 u32 value;
2712
2713 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2714 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2715
2716 switch (bias) {
2717 case PIN_CONFIG_BIAS_PULL_UP:
2718 value |= PORTCR_PULMD_UP;
2719 break;
2720 case PIN_CONFIG_BIAS_PULL_DOWN:
2721 value |= PORTCR_PULMD_DOWN;
2722 break;
2723 }
2724
2725 iowrite8(value, addr);
2726}
2727
2728static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
2729 .get_bias = r8a73a4_pinmux_get_bias,
2730 .set_bias = r8a73a4_pinmux_set_bias,
2731};
2732
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2733const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2734 .name = "r8a73a4_pfc",
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]2735 .ops = &r8a73a4_pinmux_ops,
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2736
2737 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2738 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2739 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2740
2741 .pins = pinmux_pins,
2742 .nr_pins = ARRAY_SIZE(pinmux_pins),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]2743
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame]2744 .groups = pinmux_groups,
2745 .nr_groups = ARRAY_SIZE(pinmux_groups),
2746 .functions = pinmux_functions,
2747 .nr_functions = ARRAY_SIZE(pinmux_functions),
2748
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2749 .cfg_regs = pinmux_config_regs,
2750 .data_regs = pinmux_data_regs,
2751
2752 .gpio_data = pinmux_data,
2753 .gpio_data_size = ARRAY_SIZE(pinmux_data),
Magnus Dammc96931c2013-03-26 22:50:09 +0900[diff] [blame]2754
2755 .gpio_irq = pinmux_irqs,
2756 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]2757};