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Tero Kristob4761192013-09-13 12:02:15 +03001/*
2 * TI Divider Clock
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/ti.h>
24
25#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__
27
28#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
29
30#define div_mask(d) ((1 << ((d)->width)) - 1)
31
32static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
33{
34 unsigned int maxdiv = 0;
35 const struct clk_div_table *clkt;
36
37 for (clkt = table; clkt->div; clkt++)
38 if (clkt->div > maxdiv)
39 maxdiv = clkt->div;
40 return maxdiv;
41}
42
43static unsigned int _get_maxdiv(struct clk_divider *divider)
44{
45 if (divider->flags & CLK_DIVIDER_ONE_BASED)
46 return div_mask(divider);
47 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
48 return 1 << div_mask(divider);
49 if (divider->table)
50 return _get_table_maxdiv(divider->table);
51 return div_mask(divider) + 1;
52}
53
54static unsigned int _get_table_div(const struct clk_div_table *table,
55 unsigned int val)
56{
57 const struct clk_div_table *clkt;
58
59 for (clkt = table; clkt->div; clkt++)
60 if (clkt->val == val)
61 return clkt->div;
62 return 0;
63}
64
65static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
66{
67 if (divider->flags & CLK_DIVIDER_ONE_BASED)
68 return val;
69 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
70 return 1 << val;
71 if (divider->table)
72 return _get_table_div(divider->table, val);
73 return val + 1;
74}
75
76static unsigned int _get_table_val(const struct clk_div_table *table,
77 unsigned int div)
78{
79 const struct clk_div_table *clkt;
80
81 for (clkt = table; clkt->div; clkt++)
82 if (clkt->div == div)
83 return clkt->val;
84 return 0;
85}
86
87static unsigned int _get_val(struct clk_divider *divider, u8 div)
88{
89 if (divider->flags & CLK_DIVIDER_ONE_BASED)
90 return div;
91 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
92 return __ffs(div);
93 if (divider->table)
94 return _get_table_val(divider->table, div);
95 return div - 1;
96}
97
98static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
99 unsigned long parent_rate)
100{
101 struct clk_divider *divider = to_clk_divider(hw);
102 unsigned int div, val;
103
104 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
105 val &= div_mask(divider);
106
107 div = _get_div(divider, val);
108 if (!div) {
109 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
110 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
111 __clk_get_name(hw->clk));
112 return parent_rate;
113 }
114
Tomi Valkeinen7e50e7e2014-02-13 12:04:00 +0200115 return DIV_ROUND_UP(parent_rate, div);
Tero Kristob4761192013-09-13 12:02:15 +0300116}
117
118/*
119 * The reverse of DIV_ROUND_UP: The maximum number which
120 * divided by m is r
121 */
122#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
123
124static bool _is_valid_table_div(const struct clk_div_table *table,
125 unsigned int div)
126{
127 const struct clk_div_table *clkt;
128
129 for (clkt = table; clkt->div; clkt++)
130 if (clkt->div == div)
131 return true;
132 return false;
133}
134
135static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
136{
137 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
138 return is_power_of_2(div);
139 if (divider->table)
140 return _is_valid_table_div(divider->table, div);
141 return true;
142}
143
144static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
145 unsigned long *best_parent_rate)
146{
147 struct clk_divider *divider = to_clk_divider(hw);
148 int i, bestdiv = 0;
149 unsigned long parent_rate, best = 0, now, maxdiv;
150 unsigned long parent_rate_saved = *best_parent_rate;
151
152 if (!rate)
153 rate = 1;
154
155 maxdiv = _get_maxdiv(divider);
156
157 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
158 parent_rate = *best_parent_rate;
159 bestdiv = DIV_ROUND_UP(parent_rate, rate);
160 bestdiv = bestdiv == 0 ? 1 : bestdiv;
161 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
162 return bestdiv;
163 }
164
165 /*
166 * The maximum divider we can use without overflowing
167 * unsigned long in rate * i below
168 */
169 maxdiv = min(ULONG_MAX / rate, maxdiv);
170
171 for (i = 1; i <= maxdiv; i++) {
172 if (!_is_valid_div(divider, i))
173 continue;
174 if (rate * i == parent_rate_saved) {
175 /*
176 * It's the most ideal case if the requested rate can be
177 * divided from parent clock without needing to change
178 * parent rate, so return the divider immediately.
179 */
180 *best_parent_rate = parent_rate_saved;
181 return i;
182 }
183 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
184 MULT_ROUND_UP(rate, i));
Tomi Valkeinen7e50e7e2014-02-13 12:04:00 +0200185 now = DIV_ROUND_UP(parent_rate, i);
Tero Kristob4761192013-09-13 12:02:15 +0300186 if (now <= rate && now > best) {
187 bestdiv = i;
188 best = now;
189 *best_parent_rate = parent_rate;
190 }
191 }
192
193 if (!bestdiv) {
194 bestdiv = _get_maxdiv(divider);
195 *best_parent_rate =
196 __clk_round_rate(__clk_get_parent(hw->clk), 1);
197 }
198
199 return bestdiv;
200}
201
202static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
203 unsigned long *prate)
204{
205 int div;
206 div = ti_clk_divider_bestdiv(hw, rate, prate);
207
Tomi Valkeinen7e50e7e2014-02-13 12:04:00 +0200208 return DIV_ROUND_UP(*prate, div);
Tero Kristob4761192013-09-13 12:02:15 +0300209}
210
211static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
212 unsigned long parent_rate)
213{
Nishanth Menon2f103252014-08-18 11:56:54 -0500214 struct clk_divider *divider;
Tero Kristob4761192013-09-13 12:02:15 +0300215 unsigned int div, value;
216 unsigned long flags = 0;
217 u32 val;
218
Nishanth Menon2f103252014-08-18 11:56:54 -0500219 if (!hw || !rate)
220 return -EINVAL;
221
222 divider = to_clk_divider(hw);
223
Tomi Valkeinen7e50e7e2014-02-13 12:04:00 +0200224 div = DIV_ROUND_UP(parent_rate, rate);
Tero Kristob4761192013-09-13 12:02:15 +0300225 value = _get_val(divider, div);
226
227 if (value > div_mask(divider))
228 value = div_mask(divider);
229
230 if (divider->lock)
231 spin_lock_irqsave(divider->lock, flags);
232
233 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
234 val = div_mask(divider) << (divider->shift + 16);
235 } else {
236 val = ti_clk_ll_ops->clk_readl(divider->reg);
237 val &= ~(div_mask(divider) << divider->shift);
238 }
239 val |= value << divider->shift;
240 ti_clk_ll_ops->clk_writel(val, divider->reg);
241
242 if (divider->lock)
243 spin_unlock_irqrestore(divider->lock, flags);
244
245 return 0;
246}
247
248const struct clk_ops ti_clk_divider_ops = {
249 .recalc_rate = ti_clk_divider_recalc_rate,
250 .round_rate = ti_clk_divider_round_rate,
251 .set_rate = ti_clk_divider_set_rate,
252};
253
254static struct clk *_register_divider(struct device *dev, const char *name,
255 const char *parent_name,
256 unsigned long flags, void __iomem *reg,
257 u8 shift, u8 width, u8 clk_divider_flags,
258 const struct clk_div_table *table,
259 spinlock_t *lock)
260{
261 struct clk_divider *div;
262 struct clk *clk;
263 struct clk_init_data init;
264
265 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
266 if (width + shift > 16) {
267 pr_warn("divider value exceeds LOWORD field\n");
268 return ERR_PTR(-EINVAL);
269 }
270 }
271
272 /* allocate the divider */
273 div = kzalloc(sizeof(*div), GFP_KERNEL);
274 if (!div) {
275 pr_err("%s: could not allocate divider clk\n", __func__);
276 return ERR_PTR(-ENOMEM);
277 }
278
279 init.name = name;
280 init.ops = &ti_clk_divider_ops;
281 init.flags = flags | CLK_IS_BASIC;
282 init.parent_names = (parent_name ? &parent_name : NULL);
283 init.num_parents = (parent_name ? 1 : 0);
284
285 /* struct clk_divider assignments */
286 div->reg = reg;
287 div->shift = shift;
288 div->width = width;
289 div->flags = clk_divider_flags;
290 div->lock = lock;
291 div->hw.init = &init;
292 div->table = table;
293
294 /* register the clock */
295 clk = clk_register(dev, &div->hw);
296
297 if (IS_ERR(clk))
298 kfree(div);
299
300 return clk;
301}
302
303static struct clk_div_table
304__init *ti_clk_get_div_table(struct device_node *node)
305{
306 struct clk_div_table *table;
307 const __be32 *divspec;
308 u32 val;
309 u32 num_div;
310 u32 valid_div;
311 int i;
312
313 divspec = of_get_property(node, "ti,dividers", &num_div);
314
315 if (!divspec)
316 return NULL;
317
318 num_div /= 4;
319
320 valid_div = 0;
321
322 /* Determine required size for divider table */
323 for (i = 0; i < num_div; i++) {
324 of_property_read_u32_index(node, "ti,dividers", i, &val);
325 if (val)
326 valid_div++;
327 }
328
329 if (!valid_div) {
330 pr_err("no valid dividers for %s table\n", node->name);
331 return ERR_PTR(-EINVAL);
332 }
333
334 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
335
336 if (!table)
337 return ERR_PTR(-ENOMEM);
338
339 valid_div = 0;
340
341 for (i = 0; i < num_div; i++) {
342 of_property_read_u32_index(node, "ti,dividers", i, &val);
343 if (val) {
344 table[valid_div].div = val;
345 table[valid_div].val = i;
346 valid_div++;
347 }
348 }
349
350 return table;
351}
352
353static int _get_divider_width(struct device_node *node,
354 const struct clk_div_table *table,
355 u8 flags)
356{
357 u32 min_div;
358 u32 max_div;
359 u32 val = 0;
360 u32 div;
361
362 if (!table) {
363 /* Clk divider table not provided, determine min/max divs */
364 if (of_property_read_u32(node, "ti,min-div", &min_div))
365 min_div = 1;
366
367 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
368 pr_err("no max-div for %s!\n", node->name);
369 return -EINVAL;
370 }
371
372 /* Determine bit width for the field */
373 if (flags & CLK_DIVIDER_ONE_BASED)
374 val = 1;
375
376 div = min_div;
377
378 while (div < max_div) {
379 if (flags & CLK_DIVIDER_POWER_OF_TWO)
380 div <<= 1;
381 else
382 div++;
383 val++;
384 }
385 } else {
386 div = 0;
387
388 while (table[div].div) {
389 val = table[div].val;
390 div++;
391 }
392 }
393
394 return fls(val);
395}
396
397static int __init ti_clk_divider_populate(struct device_node *node,
398 void __iomem **reg, const struct clk_div_table **table,
399 u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
400{
401 u32 val;
402
403 *reg = ti_clk_get_reg_addr(node, 0);
404 if (!*reg)
405 return -EINVAL;
406
407 if (!of_property_read_u32(node, "ti,bit-shift", &val))
408 *shift = val;
409 else
410 *shift = 0;
411
412 *flags = 0;
413 *div_flags = 0;
414
415 if (of_property_read_bool(node, "ti,index-starts-at-one"))
416 *div_flags |= CLK_DIVIDER_ONE_BASED;
417
418 if (of_property_read_bool(node, "ti,index-power-of-two"))
419 *div_flags |= CLK_DIVIDER_POWER_OF_TWO;
420
421 if (of_property_read_bool(node, "ti,set-rate-parent"))
422 *flags |= CLK_SET_RATE_PARENT;
423
424 *table = ti_clk_get_div_table(node);
425
426 if (IS_ERR(*table))
427 return PTR_ERR(*table);
428
429 *width = _get_divider_width(node, *table, *div_flags);
430
431 return 0;
432}
433
434/**
435 * of_ti_divider_clk_setup - Setup function for simple div rate clock
436 * @node: device node for this clock
437 *
438 * Sets up a basic divider clock.
439 */
440static void __init of_ti_divider_clk_setup(struct device_node *node)
441{
442 struct clk *clk;
443 const char *parent_name;
444 void __iomem *reg;
445 u8 clk_divider_flags = 0;
446 u8 width = 0;
447 u8 shift = 0;
448 const struct clk_div_table *table = NULL;
449 u32 flags = 0;
450
451 parent_name = of_clk_get_parent_name(node, 0);
452
453 if (ti_clk_divider_populate(node, &reg, &table, &flags,
454 &clk_divider_flags, &width, &shift))
455 goto cleanup;
456
457 clk = _register_divider(NULL, node->name, parent_name, flags, reg,
458 shift, width, clk_divider_flags, table, NULL);
459
460 if (!IS_ERR(clk)) {
461 of_clk_add_provider(node, of_clk_src_simple_get, clk);
462 of_ti_clk_autoidle_setup(node);
463 return;
464 }
465
466cleanup:
467 kfree(table);
468}
469CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
470
471static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
472{
473 struct clk_divider *div;
474 u32 val;
475
476 div = kzalloc(sizeof(*div), GFP_KERNEL);
477 if (!div)
478 return;
479
480 if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
481 &div->flags, &div->width, &div->shift) < 0)
482 goto cleanup;
483
484 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
485 return;
486
487cleanup:
488 kfree(div->table);
489 kfree(div);
490}
491CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
492 of_ti_composite_divider_clk_setup);