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Russell Kinga09e64f2008-08-05 16:14:15 +01001/*
2 * arch/arm/mach-at91/include/mach/at91_aic.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Advanced Interrupt Controller (AIC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_AIC_H
17#define AT91_AIC_H
18
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080019#ifndef __ASSEMBLY__
20extern void __iomem *at91_aic_base;
21
22#define at91_aic_read(field) \
23 __raw_readl(at91_aic_base + field)
24
25#define at91_aic_write(field, value) \
Ludovic Desrochesf25b00b2012-05-31 17:26:05 +020026 __raw_writel(value, at91_aic_base + field)
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080027#else
28.extern at91_aic_base
29#endif
30
Ludovic Desroches8fe82a52012-06-21 14:47:27 +020031/* Number of irq lines managed by AIC */
32#define NR_AIC_IRQS 32
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020033#define NR_AIC5_IRQS 128
34
35#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */
36#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */
Ludovic Desroches8fe82a52012-06-21 14:47:27 +020037
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020038#define AT91_AIC_IRQ_MIN_PRIORITY 0
39#define AT91_AIC_IRQ_MAX_PRIORITY 7
40
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080041#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020042#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */
Russell Kinga09e64f2008-08-05 16:14:15 +010043#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
44#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
45#define AT91_AIC_SRCTYPE_LOW (0 << 5)
46#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
47#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
48#define AT91_AIC_SRCTYPE_RISING (3 << 5)
49
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080050#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020051#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080052#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020053#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080054#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020055#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080056#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020057#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */
Russell Kinga09e64f2008-08-05 16:14:15 +010058#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
59
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080060#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020061#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */
62#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */
63#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */
64#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080065#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020066#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080067#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020068#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */
Russell Kinga09e64f2008-08-05 16:14:15 +010069#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
70#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
71
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080072#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020073#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080074#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020075#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080076#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020077#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080078#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020079#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080080#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020081#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080082#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020083#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080084#define AT91_AIC_DCR 0x138 /* Debug Control Register */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020085#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */
Russell Kinga09e64f2008-08-05 16:14:15 +010086#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
87#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
88
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080089#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020090#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080091#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020092#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */
Jean-Christophe PLAGNIOL-VILLARDbe6d4322011-11-03 01:12:50 +080093#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020094#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */
Russell Kinga09e64f2008-08-05 16:14:15 +010095
Ludovic Desroches3e135462012-06-11 15:38:03 +020096void at91_aic_handle_irq(struct pt_regs *regs);
Ludovic Desrochesc4b68522012-05-30 10:01:09 +020097void at91_aic5_handle_irq(struct pt_regs *regs);
Ludovic Desroches3e135462012-06-11 15:38:03 +020098
Russell Kinga09e64f2008-08-05 16:14:15 +010099#endif