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Jon Loeligerb8f114d2005-09-21 14:54:51 -05001#ifndef _ASM_POWERPC_DMA_H
2#define _ASM_POWERPC_DMA_H
Arnd Bergmann88ced032005-12-16 22:43:46 +01003#ifdef __KERNEL__
Jon Loeligerb8f114d2005-09-21 14:54:51 -05004
Linus Torvalds1da177e2005-04-16 15:20:36 -07005/*
Jon Loeligerb8f114d2005-09-21 14:54:51 -05006 * Defines for using and allocating dma channels.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Written by Hennus Bergman, 1992.
8 * High DMA channel support & info by Hannu Savolainen
9 * and John Boyd, Nov. 1992.
10 * Changes for ppc sound by Christoph Nadig
11 */
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013/*
14 * Note: Adapted for PowerPC by Gary Thomas
15 * Modified by Cort Dougan <cort@cs.nmt.edu>
16 *
17 * None of this really applies for Power Macintoshes. There is
18 * basically just enough here to get kernel/dma.c to compile.
19 *
20 * There may be some comments or restrictions made here which are
21 * not valid for the PReP platform. Take what you read
22 * with a grain of salt.
23 */
24
Jon Loeligerb8f114d2005-09-21 14:54:51 -050025#include <linux/config.h>
26#include <asm/io.h>
27#include <linux/spinlock.h>
28#include <asm/system.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef MAX_DMA_CHANNELS
31#define MAX_DMA_CHANNELS 8
32#endif
33
34/* The maximum address that we can perform a DMA transfer to on this platform */
35/* Doesn't really apply... */
Jon Loeligerb8f114d2005-09-21 14:54:51 -050036#define MAX_DMA_ADDRESS (~0UL)
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Jon Loeligerb8f114d2005-09-21 14:54:51 -050038#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
40#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
41#define dma_outb outb_p
42#else
43#define dma_outb outb
44#endif
45
46#define dma_inb inb
47
48/*
49 * NOTES about DMA transfers:
50 *
51 * controller 1: channels 0-3, byte operations, ports 00-1F
52 * controller 2: channels 4-7, word operations, ports C0-DF
53 *
54 * - ALL registers are 8 bits only, regardless of transfer size
55 * - channel 4 is not used - cascades 1 into 2.
56 * - channels 0-3 are byte - addresses/counts are for physical bytes
57 * - channels 5-7 are word - addresses/counts are for physical words
58 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
59 * - transfer count loaded to registers is 1 less than actual count
60 * - controller 2 offsets are all even (2x offsets for controller 1)
61 * - page registers for 5-7 don't use data bit 0, represent 128K pages
62 * - page registers for 0-3 use bit 0, represent 64K pages
63 *
64 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
65 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
66 * Note that addresses loaded into registers must be _physical_ addresses,
67 * not logical addresses (which may differ if paging is active).
68 *
69 * Address mapping for channels 0-3:
70 *
71 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
72 * | ... | | ... | | ... |
73 * | ... | | ... | | ... |
74 * | ... | | ... | | ... |
75 * P7 ... P0 A7 ... A0 A7 ... A0
76 * | Page | Addr MSB | Addr LSB | (DMA registers)
77 *
78 * Address mapping for channels 5-7:
79 *
80 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
81 * | ... | \ \ ... \ \ \ ... \ \
82 * | ... | \ \ ... \ \ \ ... \ (not used)
83 * | ... | \ \ ... \ \ \ ... \
84 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
85 * | Page | Addr MSB | Addr LSB | (DMA registers)
86 *
87 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
88 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
89 * the hardware level, so odd-byte transfers aren't possible).
90 *
91 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
92 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
93 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
94 *
95 */
96
97/* see prep_setup_arch() for detailed informations */
98#if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_PPC_PREP)
99extern long ppc_cs4232_dma, ppc_cs4232_dma2;
100#define SND_DMA1 ppc_cs4232_dma
101#define SND_DMA2 ppc_cs4232_dma2
102#else
103#define SND_DMA1 -1
104#define SND_DMA2 -1
105#endif
106
107/* 8237 DMA controllers */
108#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
109#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
110
111/* DMA controller registers */
112#define DMA1_CMD_REG 0x08 /* command register (w) */
113#define DMA1_STAT_REG 0x08 /* status register (r) */
114#define DMA1_REQ_REG 0x09 /* request register (w) */
115#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
116#define DMA1_MODE_REG 0x0B /* mode register (w) */
117#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
118#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
119#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
120#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
121#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
122
123#define DMA2_CMD_REG 0xD0 /* command register (w) */
124#define DMA2_STAT_REG 0xD0 /* status register (r) */
125#define DMA2_REQ_REG 0xD2 /* request register (w) */
126#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
127#define DMA2_MODE_REG 0xD6 /* mode register (w) */
128#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
129#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
130#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
131#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
132#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
133
134#define DMA_ADDR_0 0x00 /* DMA address registers */
135#define DMA_ADDR_1 0x02
136#define DMA_ADDR_2 0x04
137#define DMA_ADDR_3 0x06
138#define DMA_ADDR_4 0xC0
139#define DMA_ADDR_5 0xC4
140#define DMA_ADDR_6 0xC8
141#define DMA_ADDR_7 0xCC
142
143#define DMA_CNT_0 0x01 /* DMA count registers */
144#define DMA_CNT_1 0x03
145#define DMA_CNT_2 0x05
146#define DMA_CNT_3 0x07
147#define DMA_CNT_4 0xC2
148#define DMA_CNT_5 0xC6
149#define DMA_CNT_6 0xCA
150#define DMA_CNT_7 0xCE
151
152#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
153#define DMA_LO_PAGE_1 0x83
154#define DMA_LO_PAGE_2 0x81
155#define DMA_LO_PAGE_3 0x82
156#define DMA_LO_PAGE_5 0x8B
157#define DMA_LO_PAGE_6 0x89
158#define DMA_LO_PAGE_7 0x8A
159
160#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
161#define DMA_HI_PAGE_1 0x483
162#define DMA_HI_PAGE_2 0x481
163#define DMA_HI_PAGE_3 0x482
164#define DMA_HI_PAGE_5 0x48B
165#define DMA_HI_PAGE_6 0x489
166#define DMA_HI_PAGE_7 0x48A
167
168#define DMA1_EXT_REG 0x40B
169#define DMA2_EXT_REG 0x4D6
170
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500171#ifndef __powerpc64__
172 /* in arch/ppc/kernel/setup.c -- Cort */
173 extern unsigned int DMA_MODE_WRITE;
174 extern unsigned int DMA_MODE_READ;
175 extern unsigned long ISA_DMA_THRESHOLD;
176#else
177 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
178 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
179#endif
180
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500182
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183#define DMA_AUTOINIT 0x10
184
185extern spinlock_t dma_spin_lock;
186
187static __inline__ unsigned long claim_dma_lock(void)
188{
189 unsigned long flags;
190 spin_lock_irqsave(&dma_spin_lock, flags);
191 return flags;
192}
193
194static __inline__ void release_dma_lock(unsigned long flags)
195{
196 spin_unlock_irqrestore(&dma_spin_lock, flags);
197}
198
199/* enable/disable a specific DMA channel */
200static __inline__ void enable_dma(unsigned int dmanr)
201{
202 unsigned char ucDmaCmd = 0x00;
203
204 if (dmanr != 4) {
205 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
206 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
207 }
208 if (dmanr <= 3) {
209 dma_outb(dmanr, DMA1_MASK_REG);
210 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500211 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 dma_outb(dmanr & 3, DMA2_MASK_REG);
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500213 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214}
215
216static __inline__ void disable_dma(unsigned int dmanr)
217{
218 if (dmanr <= 3)
219 dma_outb(dmanr | 4, DMA1_MASK_REG);
220 else
221 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
222}
223
224/* Clear the 'DMA Pointer Flip Flop'.
225 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
226 * Use this once to initialize the FF to a known state.
227 * After that, keep track of it. :-)
228 * --- In order to do that, the DMA routines below should ---
229 * --- only be used while interrupts are disabled! ---
230 */
231static __inline__ void clear_dma_ff(unsigned int dmanr)
232{
233 if (dmanr <= 3)
234 dma_outb(0, DMA1_CLEAR_FF_REG);
235 else
236 dma_outb(0, DMA2_CLEAR_FF_REG);
237}
238
239/* set mode (above) for a specific DMA channel */
240static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
241{
242 if (dmanr <= 3)
243 dma_outb(mode | dmanr, DMA1_MODE_REG);
244 else
245 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
246}
247
248/* Set only the page register bits of the transfer address.
249 * This is used for successive transfers when we know the contents of
250 * the lower 16 bits of the DMA current address register, but a 64k boundary
251 * may have been crossed.
252 */
253static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
254{
255 switch (dmanr) {
256 case 0:
257 dma_outb(pagenr, DMA_LO_PAGE_0);
258 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
259 break;
260 case 1:
261 dma_outb(pagenr, DMA_LO_PAGE_1);
262 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
263 break;
264 case 2:
265 dma_outb(pagenr, DMA_LO_PAGE_2);
266 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
267 break;
268 case 3:
269 dma_outb(pagenr, DMA_LO_PAGE_3);
270 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
271 break;
272 case 5:
273 if (SND_DMA1 == 5 || SND_DMA2 == 5)
274 dma_outb(pagenr, DMA_LO_PAGE_5);
275 else
276 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
277 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
278 break;
279 case 6:
280 if (SND_DMA1 == 6 || SND_DMA2 == 6)
281 dma_outb(pagenr, DMA_LO_PAGE_6);
282 else
283 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
284 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
285 break;
286 case 7:
287 if (SND_DMA1 == 7 || SND_DMA2 == 7)
288 dma_outb(pagenr, DMA_LO_PAGE_7);
289 else
290 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
291 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
292 break;
293 }
294}
295
296/* Set transfer address & page bits for specific DMA channel.
297 * Assumes dma flipflop is clear.
298 */
299static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
300{
301 if (dmanr <= 3) {
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500302 dma_outb(phys & 0xff,
303 ((dmanr & 3) << 1) + IO_DMA1_BASE);
304 dma_outb((phys >> 8) & 0xff,
305 ((dmanr & 3) << 1) + IO_DMA1_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500307 dma_outb(phys & 0xff,
308 ((dmanr & 3) << 2) + IO_DMA2_BASE);
309 dma_outb((phys >> 8) & 0xff,
310 ((dmanr & 3) << 2) + IO_DMA2_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 dma_outb((dmanr & 3), DMA2_EXT_REG);
312 } else {
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500313 dma_outb((phys >> 1) & 0xff,
314 ((dmanr & 3) << 2) + IO_DMA2_BASE);
315 dma_outb((phys >> 9) & 0xff,
316 ((dmanr & 3) << 2) + IO_DMA2_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 }
318 set_dma_page(dmanr, phys >> 16);
319}
320
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500321
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
323 * a specific DMA channel.
324 * You must ensure the parameters are valid.
325 * NOTE: from a manual: "the number of transfers is one more
326 * than the initial word count"! This is taken into account.
327 * Assumes dma flip-flop is clear.
328 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
329 */
330static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
331{
332 count--;
333 if (dmanr <= 3) {
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500334 dma_outb(count & 0xff,
335 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
336 dma_outb((count >> 8) & 0xff,
337 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500339 dma_outb(count & 0xff,
340 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
341 dma_outb((count >> 8) & 0xff,
342 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 } else {
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500344 dma_outb((count >> 1) & 0xff,
345 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
346 dma_outb((count >> 9) & 0xff,
347 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348 }
349}
350
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500351
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352/* Get DMA residue count. After a DMA transfer, this
353 * should return zero. Reading this while a DMA transfer is
354 * still in progress will return unpredictable results.
355 * If called before the channel has been used, it may return 1.
356 * Otherwise, it returns the number of _bytes_ left to transfer.
357 *
358 * Assumes DMA flip-flop is clear.
359 */
360static __inline__ int get_dma_residue(unsigned int dmanr)
361{
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500362 unsigned int io_port = (dmanr <= 3)
363 ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
365
366 /* using short to get 16-bit wrap around */
367 unsigned short count;
368
369 count = 1 + dma_inb(io_port);
370 count += dma_inb(io_port) << 8;
371
372 return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
373 ? count : (count << 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374}
375
376/* These are in kernel/dma.c: */
377
378/* reserve a DMA channel */
379extern int request_dma(unsigned int dmanr, const char *device_id);
380/* release it again */
381extern void free_dma(unsigned int dmanr);
382
383#ifdef CONFIG_PCI
384extern int isa_dma_bridge_buggy;
385#else
386#define isa_dma_bridge_buggy (0)
387#endif
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500388
389#endif /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
390
Arnd Bergmann88ced032005-12-16 22:43:46 +0100391#endif /* __KERNEL__ */
Jon Loeligerb8f114d2005-09-21 14:54:51 -0500392#endif /* _ASM_POWERPC_DMA_H */