blob: 6274579effc9a8bf179e7b73578cf3af3e709fd3 [file] [log] [blame]
Amir Levy9659e592016-10-27 18:08:27 +03001/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "ipa_i.h"
14#include "ipahal/ipahal.h"
15
16static const u32 ipa_hdr_bin_sz[IPA_HDR_BIN_MAX] = { 8, 16, 24, 36, 60};
17static const u32 ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN_MAX] = { 32, 64};
18
19#define HDR_TYPE_IS_VALID(type) \
20 ((type) >= 0 && (type) < IPA_HDR_L2_MAX)
21
22#define HDR_PROC_TYPE_IS_VALID(type) \
23 ((type) >= 0 && (type) < IPA_HDR_PROC_MAX)
24
25/**
26 * ipa3_generate_hdr_hw_tbl() - generates the headers table
27 * @mem: [out] buffer to put the header table
28 *
29 * Returns: 0 on success, negative on failure
30 */
31static int ipa3_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem)
32{
33 struct ipa3_hdr_entry *entry;
34
35 mem->size = ipa3_ctx->hdr_tbl.end;
36
37 if (mem->size == 0) {
38 IPAERR("hdr tbl empty\n");
39 return -EPERM;
40 }
41 IPADBG_LOW("tbl_sz=%d\n", ipa3_ctx->hdr_tbl.end);
42
43 mem->base = dma_alloc_coherent(ipa3_ctx->pdev, mem->size,
44 &mem->phys_base, GFP_KERNEL);
45 if (!mem->base) {
46 IPAERR("fail to alloc DMA buff of size %d\n", mem->size);
47 return -ENOMEM;
48 }
49
50 memset(mem->base, 0, mem->size);
51 list_for_each_entry(entry, &ipa3_ctx->hdr_tbl.head_hdr_entry_list,
52 link) {
53 if (entry->is_hdr_proc_ctx)
54 continue;
55 IPADBG_LOW("hdr of len %d ofst=%d\n", entry->hdr_len,
56 entry->offset_entry->offset);
57 ipahal_cp_hdr_to_hw_buff(mem->base, entry->offset_entry->offset,
58 entry->hdr, entry->hdr_len);
59 }
60
61 return 0;
62}
63
64static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem,
65 u32 hdr_base_addr)
66{
67 struct ipa3_hdr_proc_ctx_entry *entry;
68 int ret;
69
70 list_for_each_entry(entry,
71 &ipa3_ctx->hdr_proc_ctx_tbl.head_proc_ctx_entry_list,
72 link) {
73 IPADBG_LOW("processing type %d ofst=%d\n",
74 entry->type, entry->offset_entry->offset);
75 ret = ipahal_cp_proc_ctx_to_hw_buff(entry->type, mem->base,
76 entry->offset_entry->offset,
77 entry->hdr->hdr_len,
78 entry->hdr->is_hdr_proc_ctx,
79 entry->hdr->phys_base,
80 hdr_base_addr,
81 entry->hdr->offset_entry);
82 if (ret)
83 return ret;
84 }
85
86 return 0;
87}
88
89/**
90 * ipa3_generate_hdr_proc_ctx_hw_tbl() -
91 * generates the headers processing context table.
92 * @mem: [out] buffer to put the processing context table
93 * @aligned_mem: [out] actual processing context table (with alignment).
94 * Processing context table needs to be 8 Bytes aligned.
95 *
96 * Returns: 0 on success, negative on failure
97 */
98static int ipa3_generate_hdr_proc_ctx_hw_tbl(u32 hdr_sys_addr,
99 struct ipa_mem_buffer *mem, struct ipa_mem_buffer *aligned_mem)
100{
101 u32 hdr_base_addr;
102
103 mem->size = (ipa3_ctx->hdr_proc_ctx_tbl.end) ? : 4;
104
105 /* make sure table is aligned */
106 mem->size += IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE;
107
108 IPADBG_LOW("tbl_sz=%d\n", ipa3_ctx->hdr_proc_ctx_tbl.end);
109
110 mem->base = dma_alloc_coherent(ipa3_ctx->pdev, mem->size,
111 &mem->phys_base, GFP_KERNEL);
112 if (!mem->base) {
113 IPAERR("fail to alloc DMA buff of size %d\n", mem->size);
114 return -ENOMEM;
115 }
116
117 aligned_mem->phys_base =
118 IPA_HDR_PROC_CTX_TABLE_ALIGNMENT(mem->phys_base);
119 aligned_mem->base = mem->base +
120 (aligned_mem->phys_base - mem->phys_base);
121 aligned_mem->size = mem->size - IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE;
122 memset(aligned_mem->base, 0, aligned_mem->size);
123 hdr_base_addr = (ipa3_ctx->hdr_tbl_lcl) ? IPA_MEM_PART(apps_hdr_ofst) :
124 hdr_sys_addr;
125 return ipa3_hdr_proc_ctx_to_hw_format(aligned_mem, hdr_base_addr);
126}
127
128/**
129 * __ipa_commit_hdr_v3_0() - Commits the header table from memory to HW
130 *
131 * Returns: 0 on success, negative on failure
132 */
133int __ipa_commit_hdr_v3_0(void)
134{
135 struct ipa3_desc desc[2];
136 struct ipa_mem_buffer hdr_mem;
137 struct ipa_mem_buffer ctx_mem;
138 struct ipa_mem_buffer aligned_ctx_mem;
139 struct ipahal_imm_cmd_dma_shared_mem dma_cmd_hdr = {0};
140 struct ipahal_imm_cmd_dma_shared_mem dma_cmd_ctx = {0};
141 struct ipahal_imm_cmd_register_write reg_write_cmd = {0};
142 struct ipahal_imm_cmd_hdr_init_system hdr_init_cmd = {0};
143 struct ipahal_imm_cmd_pyld *hdr_cmd_pyld = NULL;
144 struct ipahal_imm_cmd_pyld *ctx_cmd_pyld = NULL;
145 int rc = -EFAULT;
146 u32 proc_ctx_size;
147 u32 proc_ctx_ofst;
148 u32 proc_ctx_size_ddr;
149
150 memset(desc, 0, 2 * sizeof(struct ipa3_desc));
151
152 if (ipa3_generate_hdr_hw_tbl(&hdr_mem)) {
153 IPAERR("fail to generate HDR HW TBL\n");
154 goto end;
155 }
156
157 if (ipa3_generate_hdr_proc_ctx_hw_tbl(hdr_mem.phys_base, &ctx_mem,
158 &aligned_ctx_mem)) {
159 IPAERR("fail to generate HDR PROC CTX HW TBL\n");
160 goto end;
161 }
162
163 if (ipa3_ctx->hdr_tbl_lcl) {
164 if (hdr_mem.size > IPA_MEM_PART(apps_hdr_size)) {
165 IPAERR("tbl too big needed %d avail %d\n", hdr_mem.size,
166 IPA_MEM_PART(apps_hdr_size));
167 goto end;
168 } else {
169 dma_cmd_hdr.is_read = false; /* write operation */
170 dma_cmd_hdr.skip_pipeline_clear = false;
171 dma_cmd_hdr.pipeline_clear_options = IPAHAL_HPS_CLEAR;
172 dma_cmd_hdr.system_addr = hdr_mem.phys_base;
173 dma_cmd_hdr.size = hdr_mem.size;
174 dma_cmd_hdr.local_addr =
175 ipa3_ctx->smem_restricted_bytes +
176 IPA_MEM_PART(apps_hdr_ofst);
177 hdr_cmd_pyld = ipahal_construct_imm_cmd(
178 IPA_IMM_CMD_DMA_SHARED_MEM,
179 &dma_cmd_hdr, false);
180 if (!hdr_cmd_pyld) {
181 IPAERR("fail construct dma_shared_mem cmd\n");
182 goto end;
183 }
184 desc[0].opcode = ipahal_imm_cmd_get_opcode(
185 IPA_IMM_CMD_DMA_SHARED_MEM);
186 desc[0].pyld = hdr_cmd_pyld->data;
187 desc[0].len = hdr_cmd_pyld->len;
188 }
189 } else {
190 if (hdr_mem.size > IPA_MEM_PART(apps_hdr_size_ddr)) {
191 IPAERR("tbl too big needed %d avail %d\n", hdr_mem.size,
192 IPA_MEM_PART(apps_hdr_size_ddr));
193 goto end;
194 } else {
195 hdr_init_cmd.hdr_table_addr = hdr_mem.phys_base;
196 hdr_cmd_pyld = ipahal_construct_imm_cmd(
197 IPA_IMM_CMD_HDR_INIT_SYSTEM,
198 &hdr_init_cmd, false);
199 if (!hdr_cmd_pyld) {
200 IPAERR("fail construct hdr_init_system cmd\n");
201 goto end;
202 }
203 desc[0].opcode = ipahal_imm_cmd_get_opcode(
204 IPA_IMM_CMD_HDR_INIT_SYSTEM);
205 desc[0].pyld = hdr_cmd_pyld->data;
206 desc[0].len = hdr_cmd_pyld->len;
207 }
208 }
209 desc[0].type = IPA_IMM_CMD_DESC;
210 IPA_DUMP_BUFF(hdr_mem.base, hdr_mem.phys_base, hdr_mem.size);
211
212 proc_ctx_size = IPA_MEM_PART(apps_hdr_proc_ctx_size);
213 proc_ctx_ofst = IPA_MEM_PART(apps_hdr_proc_ctx_ofst);
214 if (ipa3_ctx->hdr_proc_ctx_tbl_lcl) {
215 if (aligned_ctx_mem.size > proc_ctx_size) {
216 IPAERR("tbl too big needed %d avail %d\n",
217 aligned_ctx_mem.size,
218 proc_ctx_size);
219 goto end;
220 } else {
221 dma_cmd_ctx.is_read = false; /* Write operation */
222 dma_cmd_ctx.skip_pipeline_clear = false;
223 dma_cmd_ctx.pipeline_clear_options = IPAHAL_HPS_CLEAR;
224 dma_cmd_ctx.system_addr = aligned_ctx_mem.phys_base;
225 dma_cmd_ctx.size = aligned_ctx_mem.size;
226 dma_cmd_ctx.local_addr =
227 ipa3_ctx->smem_restricted_bytes +
228 proc_ctx_ofst;
229 ctx_cmd_pyld = ipahal_construct_imm_cmd(
230 IPA_IMM_CMD_DMA_SHARED_MEM,
231 &dma_cmd_ctx, false);
232 if (!ctx_cmd_pyld) {
233 IPAERR("fail construct dma_shared_mem cmd\n");
234 goto end;
235 }
236 desc[1].opcode = ipahal_imm_cmd_get_opcode(
237 IPA_IMM_CMD_DMA_SHARED_MEM);
238 desc[1].pyld = ctx_cmd_pyld->data;
239 desc[1].len = ctx_cmd_pyld->len;
240 }
241 } else {
242 proc_ctx_size_ddr = IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr);
243 if (aligned_ctx_mem.size > proc_ctx_size_ddr) {
244 IPAERR("tbl too big, needed %d avail %d\n",
245 aligned_ctx_mem.size,
246 proc_ctx_size_ddr);
247 goto end;
248 } else {
249 reg_write_cmd.skip_pipeline_clear = false;
250 reg_write_cmd.pipeline_clear_options =
251 IPAHAL_HPS_CLEAR;
252 reg_write_cmd.offset =
253 ipahal_get_reg_ofst(
254 IPA_SYS_PKT_PROC_CNTXT_BASE);
255 reg_write_cmd.value = aligned_ctx_mem.phys_base;
256 reg_write_cmd.value_mask =
257 ~(IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE - 1);
258 ctx_cmd_pyld = ipahal_construct_imm_cmd(
259 IPA_IMM_CMD_REGISTER_WRITE,
260 &reg_write_cmd, false);
261 if (!ctx_cmd_pyld) {
262 IPAERR("fail construct register_write cmd\n");
263 goto end;
264 }
265 desc[1].opcode = ipahal_imm_cmd_get_opcode(
266 IPA_IMM_CMD_REGISTER_WRITE);
267 desc[1].pyld = ctx_cmd_pyld->data;
268 desc[1].len = ctx_cmd_pyld->len;
269 }
270 }
271 desc[1].type = IPA_IMM_CMD_DESC;
272 IPA_DUMP_BUFF(ctx_mem.base, ctx_mem.phys_base, ctx_mem.size);
273
274 if (ipa3_send_cmd(2, desc))
275 IPAERR("fail to send immediate command\n");
276 else
277 rc = 0;
278
279 if (ipa3_ctx->hdr_tbl_lcl) {
280 dma_free_coherent(ipa3_ctx->pdev, hdr_mem.size, hdr_mem.base,
281 hdr_mem.phys_base);
282 } else {
283 if (!rc) {
284 if (ipa3_ctx->hdr_mem.phys_base)
285 dma_free_coherent(ipa3_ctx->pdev,
286 ipa3_ctx->hdr_mem.size,
287 ipa3_ctx->hdr_mem.base,
288 ipa3_ctx->hdr_mem.phys_base);
289 ipa3_ctx->hdr_mem = hdr_mem;
290 }
291 }
292
293 if (ipa3_ctx->hdr_proc_ctx_tbl_lcl) {
294 dma_free_coherent(ipa3_ctx->pdev, ctx_mem.size, ctx_mem.base,
295 ctx_mem.phys_base);
296 } else {
297 if (!rc) {
298 if (ipa3_ctx->hdr_proc_ctx_mem.phys_base)
299 dma_free_coherent(ipa3_ctx->pdev,
300 ipa3_ctx->hdr_proc_ctx_mem.size,
301 ipa3_ctx->hdr_proc_ctx_mem.base,
302 ipa3_ctx->hdr_proc_ctx_mem.phys_base);
303 ipa3_ctx->hdr_proc_ctx_mem = ctx_mem;
304 }
305 }
306
307end:
308 if (ctx_cmd_pyld)
309 ipahal_destroy_imm_cmd(ctx_cmd_pyld);
310
311 if (hdr_cmd_pyld)
312 ipahal_destroy_imm_cmd(hdr_cmd_pyld);
313
314 return rc;
315}
316
317static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx,
318 bool add_ref_hdr)
319{
320 struct ipa3_hdr_entry *hdr_entry;
321 struct ipa3_hdr_proc_ctx_entry *entry;
322 struct ipa3_hdr_proc_ctx_offset_entry *offset;
323 u32 bin;
324 struct ipa3_hdr_proc_ctx_tbl *htbl = &ipa3_ctx->hdr_proc_ctx_tbl;
325 int id;
326 int needed_len;
327 int mem_size;
328
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200329 IPADBG_LOW("Add processing type %d hdr_hdl %d\n",
Amir Levy9659e592016-10-27 18:08:27 +0300330 proc_ctx->type, proc_ctx->hdr_hdl);
331
332 if (!HDR_PROC_TYPE_IS_VALID(proc_ctx->type)) {
333 IPAERR("invalid processing type %d\n", proc_ctx->type);
334 return -EINVAL;
335 }
336
337 hdr_entry = ipa3_id_find(proc_ctx->hdr_hdl);
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200338 if (!hdr_entry) {
Amir Levy9659e592016-10-27 18:08:27 +0300339 IPAERR("hdr_hdl is invalid\n");
340 return -EINVAL;
341 }
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200342 if (hdr_entry->cookie != IPA_COOKIE) {
343 IPAERR("Invalid header cookie %u\n", hdr_entry->cookie);
344 WARN_ON(1);
345 return -EINVAL;
346 }
347 IPADBG("Associated header is name=%s is_hdr_proc_ctx=%d\n",
348 hdr_entry->name, hdr_entry->is_hdr_proc_ctx);
Amir Levy9659e592016-10-27 18:08:27 +0300349
350 entry = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_cache, GFP_KERNEL);
351 if (!entry) {
352 IPAERR("failed to alloc proc_ctx object\n");
353 return -ENOMEM;
354 }
355
356 INIT_LIST_HEAD(&entry->link);
357
358 entry->type = proc_ctx->type;
359 entry->hdr = hdr_entry;
360 if (add_ref_hdr)
361 hdr_entry->ref_cnt++;
362 entry->cookie = IPA_COOKIE;
363
364 needed_len = ipahal_get_proc_ctx_needed_len(proc_ctx->type);
365
366 if (needed_len <= ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN0]) {
367 bin = IPA_HDR_PROC_CTX_BIN0;
368 } else if (needed_len <=
369 ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN1]) {
370 bin = IPA_HDR_PROC_CTX_BIN1;
371 } else {
372 IPAERR("unexpected needed len %d\n", needed_len);
373 WARN_ON(1);
374 goto bad_len;
375 }
376
377 mem_size = (ipa3_ctx->hdr_proc_ctx_tbl_lcl) ?
378 IPA_MEM_PART(apps_hdr_proc_ctx_size) :
379 IPA_MEM_PART(apps_hdr_proc_ctx_size_ddr);
380 if (htbl->end + ipa_hdr_proc_ctx_bin_sz[bin] > mem_size) {
381 IPAERR("hdr proc ctx table overflow\n");
382 goto bad_len;
383 }
384
385 if (list_empty(&htbl->head_free_offset_list[bin])) {
386 offset = kmem_cache_zalloc(ipa3_ctx->hdr_proc_ctx_offset_cache,
387 GFP_KERNEL);
388 if (!offset) {
389 IPAERR("failed to alloc offset object\n");
390 goto bad_len;
391 }
392 INIT_LIST_HEAD(&offset->link);
393 /*
394 * for a first item grow, set the bin and offset which are set
395 * in stone
396 */
397 offset->offset = htbl->end;
398 offset->bin = bin;
399 htbl->end += ipa_hdr_proc_ctx_bin_sz[bin];
400 list_add(&offset->link,
401 &htbl->head_offset_list[bin]);
402 } else {
403 /* get the first free slot */
404 offset =
405 list_first_entry(&htbl->head_free_offset_list[bin],
406 struct ipa3_hdr_proc_ctx_offset_entry, link);
407 list_move(&offset->link, &htbl->head_offset_list[bin]);
408 }
409
410 entry->offset_entry = offset;
411 list_add(&entry->link, &htbl->head_proc_ctx_entry_list);
412 htbl->proc_ctx_cnt++;
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200413 IPADBG("add proc ctx of sz=%d cnt=%d ofst=%d\n", needed_len,
Amir Levy9659e592016-10-27 18:08:27 +0300414 htbl->proc_ctx_cnt, offset->offset);
415
416 id = ipa3_id_alloc(entry);
417 if (id < 0) {
418 IPAERR("failed to alloc id\n");
419 WARN_ON(1);
420 }
421 entry->id = id;
422 proc_ctx->proc_ctx_hdl = id;
423 entry->ref_cnt++;
424
425 return 0;
426
427bad_len:
428 if (add_ref_hdr)
429 hdr_entry->ref_cnt--;
430 entry->cookie = 0;
431 kmem_cache_free(ipa3_ctx->hdr_proc_ctx_cache, entry);
432 return -EPERM;
433}
434
435
436static int __ipa_add_hdr(struct ipa_hdr_add *hdr)
437{
438 struct ipa3_hdr_entry *entry;
439 struct ipa_hdr_offset_entry *offset;
440 u32 bin;
441 struct ipa3_hdr_tbl *htbl = &ipa3_ctx->hdr_tbl;
442 int id;
443 int mem_size;
444
445 if (hdr->hdr_len == 0 || hdr->hdr_len > IPA_HDR_MAX_SIZE) {
446 IPAERR("bad parm\n");
447 goto error;
448 }
449
450 if (!HDR_TYPE_IS_VALID(hdr->type)) {
451 IPAERR("invalid hdr type %d\n", hdr->type);
452 goto error;
453 }
454
455 entry = kmem_cache_zalloc(ipa3_ctx->hdr_cache, GFP_KERNEL);
456 if (!entry) {
457 IPAERR("failed to alloc hdr object\n");
458 goto error;
459 }
460
461 INIT_LIST_HEAD(&entry->link);
462
463 memcpy(entry->hdr, hdr->hdr, hdr->hdr_len);
464 entry->hdr_len = hdr->hdr_len;
465 strlcpy(entry->name, hdr->name, IPA_RESOURCE_NAME_MAX);
466 entry->is_partial = hdr->is_partial;
467 entry->type = hdr->type;
468 entry->is_eth2_ofst_valid = hdr->is_eth2_ofst_valid;
469 entry->eth2_ofst = hdr->eth2_ofst;
470 entry->cookie = IPA_COOKIE;
471
472 if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN0])
473 bin = IPA_HDR_BIN0;
474 else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN1])
475 bin = IPA_HDR_BIN1;
476 else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN2])
477 bin = IPA_HDR_BIN2;
478 else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN3])
479 bin = IPA_HDR_BIN3;
480 else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN4])
481 bin = IPA_HDR_BIN4;
482 else {
483 IPAERR("unexpected hdr len %d\n", hdr->hdr_len);
484 goto bad_hdr_len;
485 }
486
487 mem_size = (ipa3_ctx->hdr_tbl_lcl) ? IPA_MEM_PART(apps_hdr_size) :
488 IPA_MEM_PART(apps_hdr_size_ddr);
489
490 /* if header does not fit to table, place it in DDR */
491 if (htbl->end + ipa_hdr_bin_sz[bin] > mem_size) {
492 entry->is_hdr_proc_ctx = true;
493 entry->phys_base = dma_map_single(ipa3_ctx->pdev,
494 entry->hdr,
495 entry->hdr_len,
496 DMA_TO_DEVICE);
497 } else {
498 entry->is_hdr_proc_ctx = false;
499 if (list_empty(&htbl->head_free_offset_list[bin])) {
500 offset = kmem_cache_zalloc(ipa3_ctx->hdr_offset_cache,
501 GFP_KERNEL);
502 if (!offset) {
503 IPAERR("failed to alloc hdr offset object\n");
504 goto bad_hdr_len;
505 }
506 INIT_LIST_HEAD(&offset->link);
507 /*
508 * for a first item grow, set the bin and offset which
509 * are set in stone
510 */
511 offset->offset = htbl->end;
512 offset->bin = bin;
513 htbl->end += ipa_hdr_bin_sz[bin];
514 list_add(&offset->link,
515 &htbl->head_offset_list[bin]);
516 } else {
517 /* get the first free slot */
518 offset =
519 list_first_entry(&htbl->head_free_offset_list[bin],
520 struct ipa_hdr_offset_entry, link);
521 list_move(&offset->link, &htbl->head_offset_list[bin]);
522 }
523
524 entry->offset_entry = offset;
525 }
526
527 list_add(&entry->link, &htbl->head_hdr_entry_list);
528 htbl->hdr_cnt++;
529 if (entry->is_hdr_proc_ctx)
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200530 IPADBG("add hdr of sz=%d hdr_cnt=%d phys_base=%pa\n",
Amir Levy9659e592016-10-27 18:08:27 +0300531 hdr->hdr_len,
532 htbl->hdr_cnt,
533 &entry->phys_base);
534 else
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200535 IPADBG("add hdr of sz=%d hdr_cnt=%d ofst=%d\n",
Amir Levy9659e592016-10-27 18:08:27 +0300536 hdr->hdr_len,
537 htbl->hdr_cnt,
538 entry->offset_entry->offset);
539
540 id = ipa3_id_alloc(entry);
541 if (id < 0) {
542 IPAERR("failed to alloc id\n");
543 WARN_ON(1);
544 }
545 entry->id = id;
546 hdr->hdr_hdl = id;
547 entry->ref_cnt++;
548
549 if (entry->is_hdr_proc_ctx) {
550 struct ipa_hdr_proc_ctx_add proc_ctx;
551
552 IPADBG("adding processing context for header %s\n", hdr->name);
553 proc_ctx.type = IPA_HDR_PROC_NONE;
554 proc_ctx.hdr_hdl = id;
555 if (__ipa_add_hdr_proc_ctx(&proc_ctx, false)) {
556 IPAERR("failed to add hdr proc ctx\n");
557 goto fail_add_proc_ctx;
558 }
559 entry->proc_ctx = ipa3_id_find(proc_ctx.proc_ctx_hdl);
560 }
561
562 return 0;
563
564fail_add_proc_ctx:
565 entry->ref_cnt--;
566 hdr->hdr_hdl = 0;
567 ipa3_id_remove(id);
568 htbl->hdr_cnt--;
569 list_del(&entry->link);
570 dma_unmap_single(ipa3_ctx->pdev, entry->phys_base,
571 entry->hdr_len, DMA_TO_DEVICE);
572bad_hdr_len:
573 entry->cookie = 0;
574 kmem_cache_free(ipa3_ctx->hdr_cache, entry);
575error:
576 return -EPERM;
577}
578
579static int __ipa3_del_hdr_proc_ctx(u32 proc_ctx_hdl, bool release_hdr)
580{
581 struct ipa3_hdr_proc_ctx_entry *entry;
582 struct ipa3_hdr_proc_ctx_tbl *htbl = &ipa3_ctx->hdr_proc_ctx_tbl;
583
584 entry = ipa3_id_find(proc_ctx_hdl);
585 if (!entry || (entry->cookie != IPA_COOKIE)) {
586 IPAERR("bad parm\n");
587 return -EINVAL;
588 }
589
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200590 IPADBG("del proc ctx cnt=%d ofst=%d\n",
Amir Levy9659e592016-10-27 18:08:27 +0300591 htbl->proc_ctx_cnt, entry->offset_entry->offset);
592
593 if (--entry->ref_cnt) {
594 IPADBG("proc_ctx_hdl %x ref_cnt %d\n",
595 proc_ctx_hdl, entry->ref_cnt);
596 return 0;
597 }
598
599 if (release_hdr)
600 __ipa3_del_hdr(entry->hdr->id);
601
602 /* move the offset entry to appropriate free list */
603 list_move(&entry->offset_entry->link,
604 &htbl->head_free_offset_list[entry->offset_entry->bin]);
605 list_del(&entry->link);
606 htbl->proc_ctx_cnt--;
607 entry->cookie = 0;
608 kmem_cache_free(ipa3_ctx->hdr_proc_ctx_cache, entry);
609
610 /* remove the handle from the database */
611 ipa3_id_remove(proc_ctx_hdl);
612
613 return 0;
614}
615
616
617int __ipa3_del_hdr(u32 hdr_hdl)
618{
619 struct ipa3_hdr_entry *entry;
620 struct ipa3_hdr_tbl *htbl = &ipa3_ctx->hdr_tbl;
621
622 entry = ipa3_id_find(hdr_hdl);
623 if (entry == NULL) {
624 IPAERR("lookup failed\n");
625 return -EINVAL;
626 }
627
628 if (!entry || (entry->cookie != IPA_COOKIE)) {
629 IPAERR("bad parm\n");
630 return -EINVAL;
631 }
632
633 if (entry->is_hdr_proc_ctx)
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200634 IPADBG("del hdr of len=%d hdr_cnt=%d phys_base=%pa\n",
Amir Levy9659e592016-10-27 18:08:27 +0300635 entry->hdr_len, htbl->hdr_cnt, &entry->phys_base);
636 else
Gidon Studinski3021a6f2016-11-10 12:48:48 +0200637 IPADBG("del hdr of len=%d hdr_cnt=%d ofst=%d\n",
638 entry->hdr_len, htbl->hdr_cnt,
639 entry->offset_entry->offset);
Amir Levy9659e592016-10-27 18:08:27 +0300640
641 if (--entry->ref_cnt) {
642 IPADBG("hdr_hdl %x ref_cnt %d\n", hdr_hdl, entry->ref_cnt);
643 return 0;
644 }
645
646 if (entry->is_hdr_proc_ctx) {
647 dma_unmap_single(ipa3_ctx->pdev,
648 entry->phys_base,
649 entry->hdr_len,
650 DMA_TO_DEVICE);
651 __ipa3_del_hdr_proc_ctx(entry->proc_ctx->id, false);
652 } else {
653 /* move the offset entry to appropriate free list */
654 list_move(&entry->offset_entry->link,
655 &htbl->head_free_offset_list[entry->offset_entry->bin]);
656 }
657 list_del(&entry->link);
658 htbl->hdr_cnt--;
659 entry->cookie = 0;
660 kmem_cache_free(ipa3_ctx->hdr_cache, entry);
661
662 /* remove the handle from the database */
663 ipa3_id_remove(hdr_hdl);
664
665 return 0;
666}
667
668/**
669 * ipa3_add_hdr() - add the specified headers to SW and optionally commit them
670 * to IPA HW
671 * @hdrs: [inout] set of headers to add
672 *
673 * Returns: 0 on success, negative on failure
674 *
675 * Note: Should not be called from atomic context
676 */
677int ipa3_add_hdr(struct ipa_ioc_add_hdr *hdrs)
678{
679 int i;
680 int result = -EFAULT;
681
682 if (hdrs == NULL || hdrs->num_hdrs == 0) {
683 IPAERR("bad parm\n");
684 return -EINVAL;
685 }
686
687 mutex_lock(&ipa3_ctx->lock);
688 IPADBG("adding %d headers to IPA driver internal data struct\n",
689 hdrs->num_hdrs);
690 for (i = 0; i < hdrs->num_hdrs; i++) {
691 if (__ipa_add_hdr(&hdrs->hdr[i])) {
692 IPAERR("failed to add hdr %d\n", i);
693 hdrs->hdr[i].status = -1;
694 } else {
695 hdrs->hdr[i].status = 0;
696 }
697 }
698
699 if (hdrs->commit) {
700 IPADBG("committing all headers to IPA core");
701 if (ipa3_ctx->ctrl->ipa3_commit_hdr()) {
702 result = -EPERM;
703 goto bail;
704 }
705 }
706 result = 0;
707bail:
708 mutex_unlock(&ipa3_ctx->lock);
709 return result;
710}
711
712/**
713 * ipa3_del_hdr() - Remove the specified headers from SW and optionally commit
714 * them to IPA HW
715 * @hdls: [inout] set of headers to delete
716 *
717 * Returns: 0 on success, negative on failure
718 *
719 * Note: Should not be called from atomic context
720 */
721int ipa3_del_hdr(struct ipa_ioc_del_hdr *hdls)
722{
723 int i;
724 int result = -EFAULT;
725
726 if (hdls == NULL || hdls->num_hdls == 0) {
727 IPAERR("bad parm\n");
728 return -EINVAL;
729 }
730
731 mutex_lock(&ipa3_ctx->lock);
732 for (i = 0; i < hdls->num_hdls; i++) {
733 if (__ipa3_del_hdr(hdls->hdl[i].hdl)) {
734 IPAERR("failed to del hdr %i\n", i);
735 hdls->hdl[i].status = -1;
736 } else {
737 hdls->hdl[i].status = 0;
738 }
739 }
740
741 if (hdls->commit) {
742 if (ipa3_ctx->ctrl->ipa3_commit_hdr()) {
743 result = -EPERM;
744 goto bail;
745 }
746 }
747 result = 0;
748bail:
749 mutex_unlock(&ipa3_ctx->lock);
750 return result;
751}
752
753/**
754 * ipa3_add_hdr_proc_ctx() - add the specified headers to SW
755 * and optionally commit them to IPA HW
756 * @proc_ctxs: [inout] set of processing context headers to add
757 *
758 * Returns: 0 on success, negative on failure
759 *
760 * Note: Should not be called from atomic context
761 */
762int ipa3_add_hdr_proc_ctx(struct ipa_ioc_add_hdr_proc_ctx *proc_ctxs)
763{
764 int i;
765 int result = -EFAULT;
766
767 if (proc_ctxs == NULL || proc_ctxs->num_proc_ctxs == 0) {
768 IPAERR("bad parm\n");
769 return -EINVAL;
770 }
771
772 mutex_lock(&ipa3_ctx->lock);
773 IPADBG("adding %d header processing contextes to IPA driver\n",
774 proc_ctxs->num_proc_ctxs);
775 for (i = 0; i < proc_ctxs->num_proc_ctxs; i++) {
776 if (__ipa_add_hdr_proc_ctx(&proc_ctxs->proc_ctx[i], true)) {
777 IPAERR("failed to add hdr pric ctx %d\n", i);
778 proc_ctxs->proc_ctx[i].status = -1;
779 } else {
780 proc_ctxs->proc_ctx[i].status = 0;
781 }
782 }
783
784 if (proc_ctxs->commit) {
785 IPADBG("committing all headers to IPA core");
786 if (ipa3_ctx->ctrl->ipa3_commit_hdr()) {
787 result = -EPERM;
788 goto bail;
789 }
790 }
791 result = 0;
792bail:
793 mutex_unlock(&ipa3_ctx->lock);
794 return result;
795}
796
797/**
798 * ipa3_del_hdr_proc_ctx() -
799 * Remove the specified processing context headers from SW and
800 * optionally commit them to IPA HW.
801 * @hdls: [inout] set of processing context headers to delete
802 *
803 * Returns: 0 on success, negative on failure
804 *
805 * Note: Should not be called from atomic context
806 */
807int ipa3_del_hdr_proc_ctx(struct ipa_ioc_del_hdr_proc_ctx *hdls)
808{
809 int i;
810 int result;
811
812 if (hdls == NULL || hdls->num_hdls == 0) {
813 IPAERR("bad parm\n");
814 return -EINVAL;
815 }
816
817 mutex_lock(&ipa3_ctx->lock);
818 for (i = 0; i < hdls->num_hdls; i++) {
819 if (__ipa3_del_hdr_proc_ctx(hdls->hdl[i].hdl, true)) {
820 IPAERR("failed to del hdr %i\n", i);
821 hdls->hdl[i].status = -1;
822 } else {
823 hdls->hdl[i].status = 0;
824 }
825 }
826
827 if (hdls->commit) {
828 if (ipa3_ctx->ctrl->ipa3_commit_hdr()) {
829 result = -EPERM;
830 goto bail;
831 }
832 }
833 result = 0;
834bail:
835 mutex_unlock(&ipa3_ctx->lock);
836 return result;
837}
838
839/**
840 * ipa3_commit_hdr() - commit to IPA HW the current header table in SW
841 *
842 * Returns: 0 on success, negative on failure
843 *
844 * Note: Should not be called from atomic context
845 */
846int ipa3_commit_hdr(void)
847{
848 int result = -EFAULT;
849
850 /*
851 * issue a commit on the routing module since routing rules point to
852 * header table entries
853 */
854 if (ipa3_commit_rt(IPA_IP_v4))
855 return -EPERM;
856 if (ipa3_commit_rt(IPA_IP_v6))
857 return -EPERM;
858
859 mutex_lock(&ipa3_ctx->lock);
860 if (ipa3_ctx->ctrl->ipa3_commit_hdr()) {
861 result = -EPERM;
862 goto bail;
863 }
864 result = 0;
865bail:
866 mutex_unlock(&ipa3_ctx->lock);
867 return result;
868}
869
870/**
871 * ipa3_reset_hdr() - reset the current header table in SW (does not commit to
872 * HW)
873 *
874 * Returns: 0 on success, negative on failure
875 *
876 * Note: Should not be called from atomic context
877 */
878int ipa3_reset_hdr(void)
879{
880 struct ipa3_hdr_entry *entry;
881 struct ipa3_hdr_entry *next;
882 struct ipa3_hdr_proc_ctx_entry *ctx_entry;
883 struct ipa3_hdr_proc_ctx_entry *ctx_next;
884 struct ipa_hdr_offset_entry *off_entry;
885 struct ipa_hdr_offset_entry *off_next;
886 struct ipa3_hdr_proc_ctx_offset_entry *ctx_off_entry;
887 struct ipa3_hdr_proc_ctx_offset_entry *ctx_off_next;
888 int i;
889
890 /*
891 * issue a reset on the routing module since routing rules point to
892 * header table entries
893 */
894 if (ipa3_reset_rt(IPA_IP_v4))
895 IPAERR("fail to reset v4 rt\n");
896 if (ipa3_reset_rt(IPA_IP_v6))
897 IPAERR("fail to reset v4 rt\n");
898
899 mutex_lock(&ipa3_ctx->lock);
900 IPADBG("reset hdr\n");
901 list_for_each_entry_safe(entry, next,
902 &ipa3_ctx->hdr_tbl.head_hdr_entry_list, link) {
903
904 /* do not remove the default header */
905 if (!strcmp(entry->name, IPA_LAN_RX_HDR_NAME)) {
906 if (entry->is_hdr_proc_ctx) {
907 IPAERR("default header is proc ctx\n");
908 mutex_unlock(&ipa3_ctx->lock);
909 WARN_ON(1);
910 return -EFAULT;
911 }
912 continue;
913 }
914
915 if (ipa3_id_find(entry->id) == NULL) {
916 mutex_unlock(&ipa3_ctx->lock);
917 WARN_ON(1);
918 return -EFAULT;
919 }
920 if (entry->is_hdr_proc_ctx) {
921 dma_unmap_single(ipa3_ctx->pdev,
922 entry->phys_base,
923 entry->hdr_len,
924 DMA_TO_DEVICE);
925 entry->proc_ctx = NULL;
926 }
927 list_del(&entry->link);
928 entry->ref_cnt = 0;
929 entry->cookie = 0;
930
931 /* remove the handle from the database */
932 ipa3_id_remove(entry->id);
933 kmem_cache_free(ipa3_ctx->hdr_cache, entry);
934
935 }
936 for (i = 0; i < IPA_HDR_BIN_MAX; i++) {
937 list_for_each_entry_safe(off_entry, off_next,
938 &ipa3_ctx->hdr_tbl.head_offset_list[i],
939 link) {
940
941 /*
942 * do not remove the default exception header which is
943 * at offset 0
944 */
945 if (off_entry->offset == 0)
946 continue;
947
948 list_del(&off_entry->link);
949 kmem_cache_free(ipa3_ctx->hdr_offset_cache, off_entry);
950 }
951 list_for_each_entry_safe(off_entry, off_next,
952 &ipa3_ctx->hdr_tbl.head_free_offset_list[i],
953 link) {
954 list_del(&off_entry->link);
955 kmem_cache_free(ipa3_ctx->hdr_offset_cache, off_entry);
956 }
957 }
958 /* there is one header of size 8 */
959 ipa3_ctx->hdr_tbl.end = 8;
960 ipa3_ctx->hdr_tbl.hdr_cnt = 1;
961
962 IPADBG("reset hdr proc ctx\n");
963 list_for_each_entry_safe(
964 ctx_entry,
965 ctx_next,
966 &ipa3_ctx->hdr_proc_ctx_tbl.head_proc_ctx_entry_list,
967 link) {
968
969 if (ipa3_id_find(ctx_entry->id) == NULL) {
970 mutex_unlock(&ipa3_ctx->lock);
971 WARN_ON(1);
972 return -EFAULT;
973 }
974 list_del(&ctx_entry->link);
975 ctx_entry->ref_cnt = 0;
976 ctx_entry->cookie = 0;
977
978 /* remove the handle from the database */
979 ipa3_id_remove(ctx_entry->id);
980 kmem_cache_free(ipa3_ctx->hdr_proc_ctx_cache, ctx_entry);
981
982 }
983 for (i = 0; i < IPA_HDR_PROC_CTX_BIN_MAX; i++) {
984 list_for_each_entry_safe(ctx_off_entry, ctx_off_next,
985 &ipa3_ctx->hdr_proc_ctx_tbl.head_offset_list[i],
986 link) {
987
988 list_del(&ctx_off_entry->link);
989 kmem_cache_free(ipa3_ctx->hdr_proc_ctx_offset_cache,
990 ctx_off_entry);
991 }
992 list_for_each_entry_safe(ctx_off_entry, ctx_off_next,
993 &ipa3_ctx->hdr_proc_ctx_tbl.head_free_offset_list[i],
994 link) {
995 list_del(&ctx_off_entry->link);
996 kmem_cache_free(ipa3_ctx->hdr_proc_ctx_offset_cache,
997 ctx_off_entry);
998 }
999 }
1000 ipa3_ctx->hdr_proc_ctx_tbl.end = 0;
1001 ipa3_ctx->hdr_proc_ctx_tbl.proc_ctx_cnt = 0;
1002 mutex_unlock(&ipa3_ctx->lock);
1003
1004 return 0;
1005}
1006
1007static struct ipa3_hdr_entry *__ipa_find_hdr(const char *name)
1008{
1009 struct ipa3_hdr_entry *entry;
1010
1011 if (strnlen(name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) {
1012 IPAERR("Header name too long: %s\n", name);
1013 return NULL;
1014 }
1015
1016 list_for_each_entry(entry, &ipa3_ctx->hdr_tbl.head_hdr_entry_list,
1017 link) {
1018 if (!strcmp(name, entry->name))
1019 return entry;
1020 }
1021
1022 return NULL;
1023}
1024
1025/**
1026 * ipa3_get_hdr() - Lookup the specified header resource
1027 * @lookup: [inout] header to lookup and its handle
1028 *
1029 * lookup the specified header resource and return handle if it exists
1030 *
1031 * Returns: 0 on success, negative on failure
1032 *
1033 * Note: Should not be called from atomic context
1034 * Caller should call ipa3_put_hdr later if this function succeeds
1035 */
1036int ipa3_get_hdr(struct ipa_ioc_get_hdr *lookup)
1037{
1038 struct ipa3_hdr_entry *entry;
1039 int result = -1;
1040
1041 if (lookup == NULL) {
1042 IPAERR("bad parm\n");
1043 return -EINVAL;
1044 }
1045 mutex_lock(&ipa3_ctx->lock);
1046 entry = __ipa_find_hdr(lookup->name);
1047 if (entry) {
1048 lookup->hdl = entry->id;
1049 result = 0;
1050 }
1051 mutex_unlock(&ipa3_ctx->lock);
1052
1053 return result;
1054}
1055
1056/**
1057 * __ipa3_release_hdr() - drop reference to header and cause
1058 * deletion if reference count permits
1059 * @hdr_hdl: [in] handle of header to be released
1060 *
1061 * Returns: 0 on success, negative on failure
1062 */
1063int __ipa3_release_hdr(u32 hdr_hdl)
1064{
1065 int result = 0;
1066
1067 if (__ipa3_del_hdr(hdr_hdl)) {
1068 IPADBG("fail to del hdr %x\n", hdr_hdl);
1069 result = -EFAULT;
1070 goto bail;
1071 }
1072
1073 /* commit for put */
1074 if (ipa3_ctx->ctrl->ipa3_commit_hdr()) {
1075 IPAERR("fail to commit hdr\n");
1076 result = -EFAULT;
1077 goto bail;
1078 }
1079
1080bail:
1081 return result;
1082}
1083
1084/**
1085 * __ipa3_release_hdr_proc_ctx() - drop reference to processing context
1086 * and cause deletion if reference count permits
1087 * @proc_ctx_hdl: [in] handle of processing context to be released
1088 *
1089 * Returns: 0 on success, negative on failure
1090 */
1091int __ipa3_release_hdr_proc_ctx(u32 proc_ctx_hdl)
1092{
1093 int result = 0;
1094
1095 if (__ipa3_del_hdr_proc_ctx(proc_ctx_hdl, true)) {
1096 IPADBG("fail to del hdr %x\n", proc_ctx_hdl);
1097 result = -EFAULT;
1098 goto bail;
1099 }
1100
1101 /* commit for put */
1102 if (ipa3_ctx->ctrl->ipa3_commit_hdr()) {
1103 IPAERR("fail to commit hdr\n");
1104 result = -EFAULT;
1105 goto bail;
1106 }
1107
1108bail:
1109 return result;
1110}
1111
1112/**
1113 * ipa3_put_hdr() - Release the specified header handle
1114 * @hdr_hdl: [in] the header handle to release
1115 *
1116 * Returns: 0 on success, negative on failure
1117 *
1118 * Note: Should not be called from atomic context
1119 */
1120int ipa3_put_hdr(u32 hdr_hdl)
1121{
1122 struct ipa3_hdr_entry *entry;
1123 int result = -EFAULT;
1124
1125 mutex_lock(&ipa3_ctx->lock);
1126
1127 entry = ipa3_id_find(hdr_hdl);
1128 if (entry == NULL) {
1129 IPAERR("lookup failed\n");
1130 result = -EINVAL;
1131 goto bail;
1132 }
1133
1134 if (entry->cookie != IPA_COOKIE) {
1135 IPAERR("invalid header entry\n");
1136 result = -EINVAL;
1137 goto bail;
1138 }
1139
1140 result = 0;
1141bail:
1142 mutex_unlock(&ipa3_ctx->lock);
1143 return result;
1144}
1145
1146/**
1147 * ipa3_copy_hdr() - Lookup the specified header resource and return a copy of
1148 * it
1149 * @copy: [inout] header to lookup and its copy
1150 *
1151 * lookup the specified header resource and return a copy of it (along with its
1152 * attributes) if it exists, this would be called for partial headers
1153 *
1154 * Returns: 0 on success, negative on failure
1155 *
1156 * Note: Should not be called from atomic context
1157 */
1158int ipa3_copy_hdr(struct ipa_ioc_copy_hdr *copy)
1159{
1160 struct ipa3_hdr_entry *entry;
1161 int result = -EFAULT;
1162
1163 if (copy == NULL) {
1164 IPAERR("bad parm\n");
1165 return -EINVAL;
1166 }
1167 mutex_lock(&ipa3_ctx->lock);
1168 entry = __ipa_find_hdr(copy->name);
1169 if (entry) {
1170 memcpy(copy->hdr, entry->hdr, entry->hdr_len);
1171 copy->hdr_len = entry->hdr_len;
1172 copy->type = entry->type;
1173 copy->is_partial = entry->is_partial;
1174 copy->is_eth2_ofst_valid = entry->is_eth2_ofst_valid;
1175 copy->eth2_ofst = entry->eth2_ofst;
1176 result = 0;
1177 }
1178 mutex_unlock(&ipa3_ctx->lock);
1179
1180 return result;
1181}