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Jiri Olsa43599d12014-05-05 12:53:20 +02001#ifndef _PERF_SYS_H
2#define _PERF_SYS_H
3
Jiri Olsa82baa0e2014-05-05 12:58:31 +02004#include <unistd.h>
5#include <sys/types.h>
6#include <sys/syscall.h>
7#include <linux/types.h>
Arnaldo Carvalho de Melo14f06522016-07-18 17:40:49 -03008#include <linux/compiler.h>
Jiri Olsa82baa0e2014-05-05 12:58:31 +02009#include <linux/perf_event.h>
Arnaldo Carvalho de Melo361c5642015-04-30 12:33:22 -030010#include <asm/barrier.h>
Jiri Olsa43599d12014-05-05 12:53:20 +020011
12#if defined(__i386__)
Jiri Olsa43599d12014-05-05 12:53:20 +020013#define cpu_relax() asm volatile("rep; nop" ::: "memory");
Wang Nan493c3032014-10-24 09:45:26 +080014#define CPUINFO_PROC {"model name"}
Jiri Olsa43599d12014-05-05 12:53:20 +020015#endif
16
17#if defined(__x86_64__)
Jiri Olsa43599d12014-05-05 12:53:20 +020018#define cpu_relax() asm volatile("rep; nop" ::: "memory");
Wang Nan493c3032014-10-24 09:45:26 +080019#define CPUINFO_PROC {"model name"}
Jiri Olsa43599d12014-05-05 12:53:20 +020020#endif
21
22#ifdef __powerpc__
23#include "../../arch/powerpc/include/uapi/asm/unistd.h"
Wang Nan493c3032014-10-24 09:45:26 +080024#define CPUINFO_PROC {"cpu"}
Jiri Olsa43599d12014-05-05 12:53:20 +020025#endif
26
27#ifdef __s390__
Wang Nan493c3032014-10-24 09:45:26 +080028#define CPUINFO_PROC {"vendor_id"}
Jiri Olsa43599d12014-05-05 12:53:20 +020029#endif
30
31#ifdef __sh__
Wang Nan493c3032014-10-24 09:45:26 +080032#define CPUINFO_PROC {"cpu type"}
Jiri Olsa43599d12014-05-05 12:53:20 +020033#endif
34
35#ifdef __hppa__
Wang Nan493c3032014-10-24 09:45:26 +080036#define CPUINFO_PROC {"cpu"}
Jiri Olsa43599d12014-05-05 12:53:20 +020037#endif
38
39#ifdef __sparc__
Wang Nan493c3032014-10-24 09:45:26 +080040#define CPUINFO_PROC {"cpu"}
Jiri Olsa43599d12014-05-05 12:53:20 +020041#endif
42
43#ifdef __alpha__
Wang Nan493c3032014-10-24 09:45:26 +080044#define CPUINFO_PROC {"cpu model"}
Jiri Olsa43599d12014-05-05 12:53:20 +020045#endif
46
47#ifdef __ia64__
Jiri Olsa43599d12014-05-05 12:53:20 +020048#define cpu_relax() asm volatile ("hint @pause" ::: "memory")
Wang Nan493c3032014-10-24 09:45:26 +080049#define CPUINFO_PROC {"model name"}
Jiri Olsa43599d12014-05-05 12:53:20 +020050#endif
51
52#ifdef __arm__
Wang Nan493c3032014-10-24 09:45:26 +080053#define CPUINFO_PROC {"model name", "Processor"}
Jiri Olsa43599d12014-05-05 12:53:20 +020054#endif
55
56#ifdef __aarch64__
Jiri Olsa43599d12014-05-05 12:53:20 +020057#define cpu_relax() asm volatile("yield" ::: "memory")
58#endif
59
60#ifdef __mips__
Wang Nan493c3032014-10-24 09:45:26 +080061#define CPUINFO_PROC {"cpu model"}
Jiri Olsa43599d12014-05-05 12:53:20 +020062#endif
63
64#ifdef __arc__
Wang Nan493c3032014-10-24 09:45:26 +080065#define CPUINFO_PROC {"Processor"}
Jiri Olsa43599d12014-05-05 12:53:20 +020066#endif
67
68#ifdef __metag__
Wang Nan493c3032014-10-24 09:45:26 +080069#define CPUINFO_PROC {"CPU"}
Jiri Olsa43599d12014-05-05 12:53:20 +020070#endif
71
72#ifdef __xtensa__
Wang Nan493c3032014-10-24 09:45:26 +080073#define CPUINFO_PROC {"core ID"}
Jiri Olsa43599d12014-05-05 12:53:20 +020074#endif
75
76#ifdef __tile__
Jiri Olsa43599d12014-05-05 12:53:20 +020077#define cpu_relax() asm volatile ("mfspr zero, PASS" ::: "memory")
Wang Nan493c3032014-10-24 09:45:26 +080078#define CPUINFO_PROC {"model name"}
Jiri Olsa43599d12014-05-05 12:53:20 +020079#endif
80
Jiri Olsa43599d12014-05-05 12:53:20 +020081#ifndef cpu_relax
82#define cpu_relax() barrier()
83#endif
84
Jiri Olsa82baa0e2014-05-05 12:58:31 +020085static inline int
86sys_perf_event_open(struct perf_event_attr *attr,
87 pid_t pid, int cpu, int group_fd,
88 unsigned long flags)
89{
90 int fd;
91
92 fd = syscall(__NR_perf_event_open, attr, pid, cpu,
93 group_fd, flags);
94
95#ifdef HAVE_ATTR_TEST
96 if (unlikely(test_attr__enabled))
97 test_attr__open(attr, pid, cpu, fd, group_fd, flags);
98#endif
99 return fd;
100}
101
Jiri Olsa43599d12014-05-05 12:53:20 +0200102#endif /* _PERF_SYS_H */