David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 1 | /* |
Paul Gortmaker | 3396c78 | 2012-01-27 13:36:01 +0000 | [diff] [blame] | 2 | * drivers/net/ethernet/ibm/emac/core.h |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 3 | * |
| 4 | * Driver for PowerPC 4xx on-chip ethernet controller. |
| 5 | * |
Benjamin Herrenschmidt | 17cf803 | 2007-12-05 11:14:33 +1100 | [diff] [blame] | 6 | * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. |
| 7 | * <benh@kernel.crashing.org> |
| 8 | * |
| 9 | * Based on the arch/ppc version of the driver: |
| 10 | * |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 11 | * Copyright (c) 2004, 2005 Zultys Technologies. |
| 12 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> |
| 13 | * |
| 14 | * Based on original work by |
| 15 | * Armin Kuster <akuster@mvista.com> |
| 16 | * Johnnie Peters <jpeters@mvista.com> |
| 17 | * Copyright 2000, 2001 MontaVista Softare Inc. |
| 18 | * |
| 19 | * This program is free software; you can redistribute it and/or modify it |
| 20 | * under the terms of the GNU General Public License as published by the |
| 21 | * Free Software Foundation; either version 2 of the License, or (at your |
| 22 | * option) any later version. |
| 23 | * |
| 24 | */ |
| 25 | #ifndef __IBM_NEWEMAC_CORE_H |
| 26 | #define __IBM_NEWEMAC_CORE_H |
| 27 | |
| 28 | #include <linux/module.h> |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 29 | #include <linux/list.h> |
| 30 | #include <linux/kernel.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/netdevice.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/spinlock.h> |
Stephen Rothwell | 55b6c8e | 2008-05-23 16:28:54 +1000 | [diff] [blame] | 35 | #include <linux/of_platform.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 36 | #include <linux/slab.h> |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 37 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 38 | #include <asm/io.h> |
| 39 | #include <asm/dcr.h> |
| 40 | |
| 41 | #include "emac.h" |
| 42 | #include "phy.h" |
| 43 | #include "zmii.h" |
| 44 | #include "rgmii.h" |
| 45 | #include "mal.h" |
| 46 | #include "tah.h" |
| 47 | #include "debug.h" |
| 48 | |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 49 | #define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB |
| 50 | #define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 51 | |
| 52 | /* Simple sanity check */ |
| 53 | #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256 |
| 54 | #error Invalid number of buffer descriptors (greater than 256) |
| 55 | #endif |
| 56 | |
| 57 | #define EMAC_MIN_MTU 46 |
| 58 | |
| 59 | /* Maximum L2 header length (VLAN tagged, no FCS) */ |
| 60 | #define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4) |
| 61 | |
| 62 | /* RX BD size for the given MTU */ |
| 63 | static inline int emac_rx_size(int mtu) |
| 64 | { |
| 65 | if (mtu > ETH_DATA_LEN) |
| 66 | return MAL_MAX_RX_SIZE; |
| 67 | else |
| 68 | return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD); |
| 69 | } |
| 70 | |
| 71 | #define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment()) |
| 72 | |
| 73 | #define EMAC_RX_SKB_HEADROOM \ |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 74 | EMAC_DMA_ALIGN(CONFIG_IBM_EMAC_RX_SKB_HEADROOM) |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 75 | |
| 76 | /* Size of RX skb for the given MTU */ |
| 77 | static inline int emac_rx_skb_size(int mtu) |
| 78 | { |
| 79 | int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu)); |
| 80 | return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM; |
| 81 | } |
| 82 | |
| 83 | /* RX DMA sync size */ |
| 84 | static inline int emac_rx_sync_size(int mtu) |
| 85 | { |
| 86 | return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2); |
| 87 | } |
| 88 | |
| 89 | /* Driver statistcs is split into two parts to make it more cache friendly: |
| 90 | * - normal statistics (packet count, etc) |
| 91 | * - error statistics |
| 92 | * |
| 93 | * When statistics is requested by ethtool, these parts are concatenated, |
| 94 | * normal one goes first. |
| 95 | * |
| 96 | * Please, keep these structures in sync with emac_stats_keys. |
| 97 | */ |
| 98 | |
| 99 | /* Normal TX/RX Statistics */ |
| 100 | struct emac_stats { |
| 101 | u64 rx_packets; |
| 102 | u64 rx_bytes; |
| 103 | u64 tx_packets; |
| 104 | u64 tx_bytes; |
| 105 | u64 rx_packets_csum; |
| 106 | u64 tx_packets_csum; |
| 107 | }; |
| 108 | |
| 109 | /* Error statistics */ |
| 110 | struct emac_error_stats { |
| 111 | u64 tx_undo; |
| 112 | |
| 113 | /* Software RX Errors */ |
| 114 | u64 rx_dropped_stack; |
| 115 | u64 rx_dropped_oom; |
| 116 | u64 rx_dropped_error; |
| 117 | u64 rx_dropped_resize; |
| 118 | u64 rx_dropped_mtu; |
| 119 | u64 rx_stopped; |
| 120 | /* BD reported RX errors */ |
| 121 | u64 rx_bd_errors; |
| 122 | u64 rx_bd_overrun; |
| 123 | u64 rx_bd_bad_packet; |
| 124 | u64 rx_bd_runt_packet; |
| 125 | u64 rx_bd_short_event; |
| 126 | u64 rx_bd_alignment_error; |
| 127 | u64 rx_bd_bad_fcs; |
| 128 | u64 rx_bd_packet_too_long; |
| 129 | u64 rx_bd_out_of_range; |
| 130 | u64 rx_bd_in_range; |
| 131 | /* EMAC IRQ reported RX errors */ |
| 132 | u64 rx_parity; |
| 133 | u64 rx_fifo_overrun; |
| 134 | u64 rx_overrun; |
| 135 | u64 rx_bad_packet; |
| 136 | u64 rx_runt_packet; |
| 137 | u64 rx_short_event; |
| 138 | u64 rx_alignment_error; |
| 139 | u64 rx_bad_fcs; |
| 140 | u64 rx_packet_too_long; |
| 141 | u64 rx_out_of_range; |
| 142 | u64 rx_in_range; |
| 143 | |
| 144 | /* Software TX Errors */ |
| 145 | u64 tx_dropped; |
| 146 | /* BD reported TX errors */ |
| 147 | u64 tx_bd_errors; |
| 148 | u64 tx_bd_bad_fcs; |
| 149 | u64 tx_bd_carrier_loss; |
| 150 | u64 tx_bd_excessive_deferral; |
| 151 | u64 tx_bd_excessive_collisions; |
| 152 | u64 tx_bd_late_collision; |
| 153 | u64 tx_bd_multple_collisions; |
| 154 | u64 tx_bd_single_collision; |
| 155 | u64 tx_bd_underrun; |
| 156 | u64 tx_bd_sqe; |
| 157 | /* EMAC IRQ reported TX errors */ |
| 158 | u64 tx_parity; |
| 159 | u64 tx_underrun; |
| 160 | u64 tx_sqe; |
| 161 | u64 tx_errors; |
| 162 | }; |
| 163 | |
| 164 | #define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \ |
| 165 | sizeof(struct emac_error_stats)) \ |
| 166 | / sizeof(u64)) |
| 167 | |
| 168 | struct emac_instance { |
| 169 | struct net_device *ndev; |
| 170 | struct resource rsrc_regs; |
| 171 | struct emac_regs __iomem *emacp; |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 172 | struct platform_device *ofdev; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 173 | struct device_node **blist; /* bootlist entry */ |
| 174 | |
| 175 | /* MAL linkage */ |
| 176 | u32 mal_ph; |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 177 | struct platform_device *mal_dev; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 178 | u32 mal_rx_chan; |
| 179 | u32 mal_tx_chan; |
| 180 | struct mal_instance *mal; |
| 181 | struct mal_commac commac; |
| 182 | |
| 183 | /* PHY infos */ |
| 184 | u32 phy_mode; |
| 185 | u32 phy_map; |
| 186 | u32 phy_address; |
| 187 | u32 phy_feat_exc; |
| 188 | struct mii_phy phy; |
| 189 | struct mutex link_lock; |
| 190 | struct delayed_work link_work; |
| 191 | int link_polling; |
| 192 | |
Victor Gallardo | 9e3cb29 | 2008-10-01 23:37:57 -0700 | [diff] [blame] | 193 | /* GPCS PHY infos */ |
| 194 | u32 gpcs_address; |
| 195 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 196 | /* Shared MDIO if any */ |
| 197 | u32 mdio_ph; |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 198 | struct platform_device *mdio_dev; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 199 | struct emac_instance *mdio_instance; |
| 200 | struct mutex mdio_lock; |
| 201 | |
| 202 | /* ZMII infos if any */ |
| 203 | u32 zmii_ph; |
| 204 | u32 zmii_port; |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 205 | struct platform_device *zmii_dev; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 206 | |
| 207 | /* RGMII infos if any */ |
| 208 | u32 rgmii_ph; |
| 209 | u32 rgmii_port; |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 210 | struct platform_device *rgmii_dev; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 211 | |
| 212 | /* TAH infos if any */ |
| 213 | u32 tah_ph; |
| 214 | u32 tah_port; |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 215 | struct platform_device *tah_dev; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 216 | |
| 217 | /* IRQs */ |
| 218 | int wol_irq; |
| 219 | int emac_irq; |
| 220 | |
| 221 | /* OPB bus frequency in Mhz */ |
| 222 | u32 opb_bus_freq; |
| 223 | |
| 224 | /* Cell index within an ASIC (for clk mgmnt) */ |
| 225 | u32 cell_index; |
| 226 | |
| 227 | /* Max supported MTU */ |
| 228 | u32 max_mtu; |
| 229 | |
| 230 | /* Feature bits (from probe table) */ |
| 231 | unsigned int features; |
| 232 | |
| 233 | /* Tx and Rx fifo sizes & other infos in bytes */ |
| 234 | u32 tx_fifo_size; |
| 235 | u32 tx_fifo_size_gige; |
| 236 | u32 rx_fifo_size; |
| 237 | u32 rx_fifo_size_gige; |
| 238 | u32 fifo_entry_size; |
| 239 | u32 mal_burst_size; /* move to MAL ? */ |
| 240 | |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 241 | /* IAHT and GAHT filter parameterization */ |
| 242 | u32 xaht_slots_shift; |
| 243 | u32 xaht_width_shift; |
| 244 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 245 | /* Descriptor management |
| 246 | */ |
| 247 | struct mal_descriptor *tx_desc; |
| 248 | int tx_cnt; |
| 249 | int tx_slot; |
| 250 | int ack_slot; |
| 251 | |
| 252 | struct mal_descriptor *rx_desc; |
| 253 | int rx_slot; |
| 254 | struct sk_buff *rx_sg_skb; /* 1 */ |
| 255 | int rx_skb_size; |
| 256 | int rx_sync_size; |
| 257 | |
| 258 | struct sk_buff *tx_skb[NUM_TX_BUFF]; |
| 259 | struct sk_buff *rx_skb[NUM_RX_BUFF]; |
| 260 | |
| 261 | /* Stats |
| 262 | */ |
| 263 | struct emac_error_stats estats; |
| 264 | struct net_device_stats nstats; |
| 265 | struct emac_stats stats; |
| 266 | |
| 267 | /* Misc |
| 268 | */ |
| 269 | int reset_failed; |
| 270 | int stop_timeout; /* in us */ |
| 271 | int no_mcast; |
| 272 | int mcast_pending; |
Benjamin Herrenschmidt | 61dbcec | 2007-11-20 14:50:46 +1100 | [diff] [blame] | 273 | int opened; |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 274 | struct work_struct reset_work; |
| 275 | spinlock_t lock; |
| 276 | }; |
| 277 | |
| 278 | /* |
| 279 | * Features of various EMAC implementations |
| 280 | */ |
| 281 | |
| 282 | /* |
| 283 | * No flow control on 40x according to the original driver |
| 284 | */ |
| 285 | #define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001 |
| 286 | /* |
| 287 | * Cell is an EMAC4 |
| 288 | */ |
| 289 | #define EMAC_FTR_EMAC4 0x00000002 |
| 290 | /* |
| 291 | * For the 440SPe, AMCC inexplicably changed the polarity of |
| 292 | * the "operation complete" bit in the MII control register. |
| 293 | */ |
| 294 | #define EMAC_FTR_STACR_OC_INVERT 0x00000004 |
| 295 | /* |
| 296 | * Set if we have a TAH. |
| 297 | */ |
| 298 | #define EMAC_FTR_HAS_TAH 0x00000008 |
| 299 | /* |
| 300 | * Set if we have a ZMII. |
| 301 | */ |
| 302 | #define EMAC_FTR_HAS_ZMII 0x00000010 |
| 303 | /* |
| 304 | * Set if we have a RGMII. |
| 305 | */ |
| 306 | #define EMAC_FTR_HAS_RGMII 0x00000020 |
| 307 | /* |
Benjamin Herrenschmidt | bff713b | 2007-12-05 11:14:29 +1100 | [diff] [blame] | 308 | * Set if we have new type STACR with STAOPC |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 309 | */ |
Benjamin Herrenschmidt | bff713b | 2007-12-05 11:14:29 +1100 | [diff] [blame] | 310 | #define EMAC_FTR_HAS_NEW_STACR 0x00000040 |
Valentine Barshak | 0925ab5 | 2008-04-22 10:46:46 +1000 | [diff] [blame] | 311 | /* |
| 312 | * Set if we need phy clock workaround for 440gx |
| 313 | */ |
| 314 | #define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080 |
Valentine Barshak | 11121e3 | 2008-04-22 10:46:48 +1000 | [diff] [blame] | 315 | /* |
| 316 | * Set if we need phy clock workaround for 440ep or 440gr |
| 317 | */ |
| 318 | #define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100 |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 319 | /* |
| 320 | * The 405EX and 460EX contain the EMAC4SYNC core |
| 321 | */ |
| 322 | #define EMAC_FTR_EMAC4SYNC 0x00000200 |
Victor Gallardo | 9e3cb29 | 2008-10-01 23:37:57 -0700 | [diff] [blame] | 323 | /* |
| 324 | * Set if we need phy clock workaround for 460ex or 460gt |
| 325 | */ |
| 326 | #define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400 |
Duc Dang | ae5d337 | 2012-03-05 00:58:22 +0000 | [diff] [blame] | 327 | /* |
| 328 | * APM821xx requires Jumbo frame size set explicitly |
| 329 | */ |
| 330 | #define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE 0x00000800 |
| 331 | /* |
| 332 | * APM821xx does not support Half Duplex mode |
| 333 | */ |
| 334 | #define EMAC_FTR_APM821XX_NO_HALF_DUPLEX 0x00001000 |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 335 | |
| 336 | /* Right now, we don't quite handle the always/possible masks on the |
| 337 | * most optimal way as we don't have a way to say something like |
| 338 | * always EMAC4. Patches welcome. |
| 339 | */ |
| 340 | enum { |
| 341 | EMAC_FTRS_ALWAYS = 0, |
| 342 | |
| 343 | EMAC_FTRS_POSSIBLE = |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 344 | #ifdef CONFIG_IBM_EMAC_EMAC4 |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 345 | EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC | |
| 346 | EMAC_FTR_HAS_NEW_STACR | |
Valentine Barshak | 0925ab5 | 2008-04-22 10:46:46 +1000 | [diff] [blame] | 347 | EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 348 | #endif |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 349 | #ifdef CONFIG_IBM_EMAC_TAH |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 350 | EMAC_FTR_HAS_TAH | |
| 351 | #endif |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 352 | #ifdef CONFIG_IBM_EMAC_ZMII |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 353 | EMAC_FTR_HAS_ZMII | |
| 354 | #endif |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 355 | #ifdef CONFIG_IBM_EMAC_RGMII |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 356 | EMAC_FTR_HAS_RGMII | |
| 357 | #endif |
Tony Breeds | 3b3bceef | 2011-08-18 21:33:49 -0700 | [diff] [blame] | 358 | #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL |
Josh Boyer | b68d185 | 2008-09-04 02:57:57 +0000 | [diff] [blame] | 359 | EMAC_FTR_NO_FLOW_CONTROL_40x | |
| 360 | #endif |
Victor Gallardo | 9e3cb29 | 2008-10-01 23:37:57 -0700 | [diff] [blame] | 361 | EMAC_FTR_460EX_PHY_CLK_FIX | |
Duc Dang | ae5d337 | 2012-03-05 00:58:22 +0000 | [diff] [blame] | 362 | EMAC_FTR_440EP_PHY_CLK_FIX | |
| 363 | EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE | |
| 364 | EMAC_FTR_APM821XX_NO_HALF_DUPLEX, |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 365 | }; |
| 366 | |
| 367 | static inline int emac_has_feature(struct emac_instance *dev, |
| 368 | unsigned long feature) |
| 369 | { |
| 370 | return (EMAC_FTRS_ALWAYS & feature) || |
| 371 | (EMAC_FTRS_POSSIBLE & dev->features & feature); |
| 372 | } |
| 373 | |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 374 | /* |
| 375 | * Various instances of the EMAC core have varying 1) number of |
| 376 | * address match slots, 2) width of the registers for handling address |
| 377 | * match slots, 3) number of registers for handling address match |
| 378 | * slots and 4) base offset for those registers. |
| 379 | * |
| 380 | * These macros and inlines handle these differences based on |
| 381 | * parameters supplied by the device structure which are, in turn, |
| 382 | * initialized based on the "compatible" entry in the device tree. |
| 383 | */ |
| 384 | |
| 385 | #define EMAC4_XAHT_SLOTS_SHIFT 6 |
| 386 | #define EMAC4_XAHT_WIDTH_SHIFT 4 |
| 387 | |
| 388 | #define EMAC4SYNC_XAHT_SLOTS_SHIFT 8 |
| 389 | #define EMAC4SYNC_XAHT_WIDTH_SHIFT 5 |
| 390 | |
| 391 | #define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift) |
| 392 | #define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift) |
| 393 | #define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \ |
| 394 | (dev)->xaht_width_shift)) |
| 395 | |
| 396 | #define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \ |
| 397 | ((EMAC_XAHT_SLOTS(dev) - 1) - \ |
| 398 | ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \ |
| 399 | (dev)->xaht_slots_shift))) |
| 400 | |
| 401 | #define EMAC_XAHT_SLOT_TO_REG(dev, slot) \ |
| 402 | ((slot) >> (dev)->xaht_width_shift) |
| 403 | |
| 404 | #define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \ |
| 405 | ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \ |
| 406 | ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1))) |
| 407 | |
| 408 | static inline u32 *emac_xaht_base(struct emac_instance *dev) |
| 409 | { |
| 410 | struct emac_regs __iomem *p = dev->emacp; |
| 411 | int offset; |
| 412 | |
| 413 | /* The first IAHT entry always is the base of the block of |
| 414 | * IAHT and GAHT registers. |
| 415 | */ |
| 416 | if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) |
| 417 | offset = offsetof(struct emac_regs, u1.emac4sync.iaht1); |
| 418 | else |
| 419 | offset = offsetof(struct emac_regs, u0.emac4.iaht1); |
| 420 | |
Eric Dumazet | 807540b | 2010-09-23 05:40:09 +0000 | [diff] [blame] | 421 | return (u32 *)((ptrdiff_t)p + offset); |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 422 | } |
| 423 | |
| 424 | static inline u32 *emac_gaht_base(struct emac_instance *dev) |
| 425 | { |
| 426 | /* GAHT registers always come after an identical number of |
| 427 | * IAHT registers. |
| 428 | */ |
Eric Dumazet | 807540b | 2010-09-23 05:40:09 +0000 | [diff] [blame] | 429 | return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev); |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | static inline u32 *emac_iaht_base(struct emac_instance *dev) |
| 433 | { |
| 434 | /* IAHT registers always come before an identical number of |
| 435 | * GAHT registers. |
| 436 | */ |
Eric Dumazet | 807540b | 2010-09-23 05:40:09 +0000 | [diff] [blame] | 437 | return emac_xaht_base(dev); |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 438 | } |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 439 | |
| 440 | /* Ethtool get_regs complex data. |
| 441 | * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH |
| 442 | * when available. |
| 443 | * |
| 444 | * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr, |
| 445 | * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers. |
| 446 | * Each register component is preceded with emac_ethtool_regs_subhdr. |
| 447 | * Order of the optional headers follows their relative bit posititions |
| 448 | * in emac_ethtool_regs_hdr.components |
| 449 | */ |
| 450 | #define EMAC_ETHTOOL_REGS_ZMII 0x00000001 |
| 451 | #define EMAC_ETHTOOL_REGS_RGMII 0x00000002 |
| 452 | #define EMAC_ETHTOOL_REGS_TAH 0x00000004 |
| 453 | |
| 454 | struct emac_ethtool_regs_hdr { |
| 455 | u32 components; |
| 456 | }; |
| 457 | |
| 458 | struct emac_ethtool_regs_subhdr { |
| 459 | u32 version; |
| 460 | u32 index; |
| 461 | }; |
| 462 | |
Grant Erickson | 05781cc | 2008-07-08 08:03:11 +1000 | [diff] [blame] | 463 | #define EMAC_ETHTOOL_REGS_VER 0 |
| 464 | #define EMAC_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ |
| 465 | (dev)->rsrc_regs.start + 1) |
| 466 | #define EMAC4_ETHTOOL_REGS_VER 1 |
| 467 | #define EMAC4_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ |
| 468 | (dev)->rsrc_regs.start + 1) |
| 469 | |
David Gibson | 1d3bb99 | 2007-08-23 13:56:01 +1000 | [diff] [blame] | 470 | #endif /* __IBM_NEWEMAC_CORE_H */ |