Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Dave Airlie |
| 30 | */ |
| 31 | #include <linux/seq_file.h> |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 32 | #include <linux/atomic.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 33 | #include <linux/wait.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 34 | #include <linux/kref.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 36 | #include <linux/firmware.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | #include "radeon_reg.h" |
| 39 | #include "radeon.h" |
Dave Airlie | 99ee7fa | 2010-11-23 11:47:49 +1000 | [diff] [blame] | 40 | #include "radeon_trace.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 42 | /* |
| 43 | * Fences |
| 44 | * Fences mark an event in the GPUs pipeline and are used |
| 45 | * for GPU/CPU synchronization. When the fence is written, |
| 46 | * it is expected that all buffers associated with that fence |
| 47 | * are no longer in use by the associated ring on the GPU and |
| 48 | * that the the relevant GPU caches have been flushed. Whether |
| 49 | * we use a scratch register or memory location depends on the asic |
| 50 | * and whether writeback is enabled. |
| 51 | */ |
| 52 | |
| 53 | /** |
| 54 | * radeon_fence_write - write a fence value |
| 55 | * |
| 56 | * @rdev: radeon_device pointer |
| 57 | * @seq: sequence number to write |
| 58 | * @ring: ring index the fence is associated with |
| 59 | * |
| 60 | * Writes a fence value to memory or a scratch register (all asics). |
| 61 | */ |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 62 | static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring) |
Alex Deucher | b81157d | 2011-06-13 17:39:06 -0400 | [diff] [blame] | 63 | { |
Christian König | bf66625 | 2012-07-09 10:52:39 +0200 | [diff] [blame] | 64 | struct radeon_fence_driver *drv = &rdev->fence_drv[ring]; |
| 65 | if (likely(rdev->wb.enabled || !drv->scratch_reg)) { |
Jerome Glisse | 089920f | 2013-06-06 17:51:21 -0400 | [diff] [blame] | 66 | if (drv->cpu_addr) { |
| 67 | *drv->cpu_addr = cpu_to_le32(seq); |
| 68 | } |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 69 | } else { |
Christian König | bf66625 | 2012-07-09 10:52:39 +0200 | [diff] [blame] | 70 | WREG32(drv->scratch_reg, seq); |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 71 | } |
Alex Deucher | b81157d | 2011-06-13 17:39:06 -0400 | [diff] [blame] | 72 | } |
| 73 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 74 | /** |
| 75 | * radeon_fence_read - read a fence value |
| 76 | * |
| 77 | * @rdev: radeon_device pointer |
| 78 | * @ring: ring index the fence is associated with |
| 79 | * |
| 80 | * Reads a fence value from memory or a scratch register (all asics). |
| 81 | * Returns the value of the fence read from memory or register. |
| 82 | */ |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 83 | static u32 radeon_fence_read(struct radeon_device *rdev, int ring) |
Alex Deucher | b81157d | 2011-06-13 17:39:06 -0400 | [diff] [blame] | 84 | { |
Christian König | bf66625 | 2012-07-09 10:52:39 +0200 | [diff] [blame] | 85 | struct radeon_fence_driver *drv = &rdev->fence_drv[ring]; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 86 | u32 seq = 0; |
Alex Deucher | b81157d | 2011-06-13 17:39:06 -0400 | [diff] [blame] | 87 | |
Christian König | bf66625 | 2012-07-09 10:52:39 +0200 | [diff] [blame] | 88 | if (likely(rdev->wb.enabled || !drv->scratch_reg)) { |
Jerome Glisse | 089920f | 2013-06-06 17:51:21 -0400 | [diff] [blame] | 89 | if (drv->cpu_addr) { |
| 90 | seq = le32_to_cpu(*drv->cpu_addr); |
| 91 | } else { |
| 92 | seq = lower_32_bits(atomic64_read(&drv->last_seq)); |
| 93 | } |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 94 | } else { |
Christian König | bf66625 | 2012-07-09 10:52:39 +0200 | [diff] [blame] | 95 | seq = RREG32(drv->scratch_reg); |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 96 | } |
Alex Deucher | b81157d | 2011-06-13 17:39:06 -0400 | [diff] [blame] | 97 | return seq; |
| 98 | } |
| 99 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 100 | /** |
| 101 | * radeon_fence_emit - emit a fence on the requested ring |
| 102 | * |
| 103 | * @rdev: radeon_device pointer |
| 104 | * @fence: radeon fence object |
| 105 | * @ring: ring index the fence is associated with |
| 106 | * |
| 107 | * Emits a fence command on the requested ring (all asics). |
| 108 | * Returns 0 on success, -ENOMEM on failure. |
| 109 | */ |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 110 | int radeon_fence_emit(struct radeon_device *rdev, |
| 111 | struct radeon_fence **fence, |
| 112 | int ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 113 | { |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 114 | /* we are protected by the ring emission mutex */ |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 115 | *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL); |
| 116 | if ((*fence) == NULL) { |
| 117 | return -ENOMEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 118 | } |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 119 | kref_init(&((*fence)->kref)); |
| 120 | (*fence)->rdev = rdev; |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 121 | (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring]; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 122 | (*fence)->ring = ring; |
| 123 | radeon_fence_ring_emit(rdev, ring, *fence); |
Christian König | 1d78416 | 2014-01-23 14:24:17 +0100 | [diff] [blame] | 124 | trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 125 | return 0; |
| 126 | } |
| 127 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 128 | /** |
| 129 | * radeon_fence_process - process a fence |
| 130 | * |
| 131 | * @rdev: radeon_device pointer |
| 132 | * @ring: ring index the fence is associated with |
| 133 | * |
| 134 | * Checks the current fence value and wakes the fence queue |
| 135 | * if the sequence number has increased (all asics). |
| 136 | */ |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 137 | void radeon_fence_process(struct radeon_device *rdev, int ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 138 | { |
Christian König | f492c17 | 2012-09-13 10:33:47 +0200 | [diff] [blame] | 139 | uint64_t seq, last_seq, last_emitted; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 140 | unsigned count_loop = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 141 | bool wake = false; |
| 142 | |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 143 | /* Note there is a scenario here for an infinite loop but it's |
| 144 | * very unlikely to happen. For it to happen, the current polling |
| 145 | * process need to be interrupted by another process and another |
| 146 | * process needs to update the last_seq btw the atomic read and |
| 147 | * xchg of the current process. |
| 148 | * |
| 149 | * More over for this to go in infinite loop there need to be |
| 150 | * continuously new fence signaled ie radeon_fence_read needs |
| 151 | * to return a different value each time for both the currently |
| 152 | * polling process and the other process that xchg the last_seq |
| 153 | * btw atomic read and xchg of the current process. And the |
| 154 | * value the other process set as last seq must be higher than |
| 155 | * the seq value we just read. Which means that current process |
| 156 | * need to be interrupted after radeon_fence_read and before |
| 157 | * atomic xchg. |
| 158 | * |
| 159 | * To be even more safe we count the number of time we loop and |
| 160 | * we bail after 10 loop just accepting the fact that we might |
| 161 | * have temporarly set the last_seq not to the true real last |
| 162 | * seq but to an older one. |
| 163 | */ |
| 164 | last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq); |
| 165 | do { |
Christian König | f492c17 | 2012-09-13 10:33:47 +0200 | [diff] [blame] | 166 | last_emitted = rdev->fence_drv[ring].sync_seq[ring]; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 167 | seq = radeon_fence_read(rdev, ring); |
| 168 | seq |= last_seq & 0xffffffff00000000LL; |
| 169 | if (seq < last_seq) { |
Christian König | f492c17 | 2012-09-13 10:33:47 +0200 | [diff] [blame] | 170 | seq &= 0xffffffff; |
| 171 | seq |= last_emitted & 0xffffffff00000000LL; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 172 | } |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 173 | |
Christian König | f492c17 | 2012-09-13 10:33:47 +0200 | [diff] [blame] | 174 | if (seq <= last_seq || seq > last_emitted) { |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 175 | break; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 176 | } |
| 177 | /* If we loop over we don't want to return without |
| 178 | * checking if a fence is signaled as it means that the |
| 179 | * seq we just read is different from the previous on. |
| 180 | */ |
| 181 | wake = true; |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 182 | last_seq = seq; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 183 | if ((count_loop++) > 10) { |
| 184 | /* We looped over too many time leave with the |
| 185 | * fact that we might have set an older fence |
| 186 | * seq then the current real last seq as signaled |
| 187 | * by the hw. |
| 188 | */ |
| 189 | break; |
| 190 | } |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 191 | } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq); |
| 192 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 193 | if (wake) |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 194 | wake_up_all(&rdev->fence_queue); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 195 | } |
| 196 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 197 | /** |
| 198 | * radeon_fence_destroy - destroy a fence |
| 199 | * |
| 200 | * @kref: fence kref |
| 201 | * |
| 202 | * Frees the fence object (all asics). |
| 203 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 204 | static void radeon_fence_destroy(struct kref *kref) |
| 205 | { |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 206 | struct radeon_fence *fence; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 207 | |
| 208 | fence = container_of(kref, struct radeon_fence, kref); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 209 | kfree(fence); |
| 210 | } |
| 211 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 212 | /** |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 213 | * radeon_fence_seq_signaled - check if a fence sequence number has signaled |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 214 | * |
| 215 | * @rdev: radeon device pointer |
| 216 | * @seq: sequence number |
| 217 | * @ring: ring index the fence is associated with |
| 218 | * |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 219 | * Check if the last signaled fence sequnce number is >= the requested |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 220 | * sequence number (all asics). |
| 221 | * Returns true if the fence has signaled (current fence value |
| 222 | * is >= requested value) or false if it has not (current fence |
| 223 | * value is < the requested value. Helper function for |
| 224 | * radeon_fence_signaled(). |
| 225 | */ |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 226 | static bool radeon_fence_seq_signaled(struct radeon_device *rdev, |
| 227 | u64 seq, unsigned ring) |
| 228 | { |
| 229 | if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) { |
| 230 | return true; |
| 231 | } |
| 232 | /* poll new last sequence at least once */ |
| 233 | radeon_fence_process(rdev, ring); |
| 234 | if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) { |
| 235 | return true; |
| 236 | } |
| 237 | return false; |
| 238 | } |
| 239 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 240 | /** |
| 241 | * radeon_fence_signaled - check if a fence has signaled |
| 242 | * |
| 243 | * @fence: radeon fence object |
| 244 | * |
| 245 | * Check if the requested fence has signaled (all asics). |
| 246 | * Returns true if the fence has signaled or false if it has not. |
| 247 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 248 | bool radeon_fence_signaled(struct radeon_fence *fence) |
| 249 | { |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 250 | if (!fence) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | return true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 252 | } |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 253 | if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) { |
| 254 | return true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 255 | } |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 256 | if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) { |
| 257 | fence->seq = RADEON_FENCE_SIGNALED_SEQ; |
| 258 | return true; |
| 259 | } |
| 260 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 261 | } |
| 262 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 263 | /** |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 264 | * radeon_fence_any_seq_signaled - check if any sequence number is signaled |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 265 | * |
| 266 | * @rdev: radeon device pointer |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 267 | * @seq: sequence numbers |
| 268 | * |
| 269 | * Check if the last signaled fence sequnce number is >= the requested |
| 270 | * sequence number (all asics). |
| 271 | * Returns true if any has signaled (current value is >= requested value) |
| 272 | * or false if it has not. Helper function for radeon_fence_wait_seq. |
| 273 | */ |
| 274 | static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq) |
| 275 | { |
| 276 | unsigned i; |
| 277 | |
| 278 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 279 | if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) |
| 280 | return true; |
| 281 | } |
| 282 | return false; |
| 283 | } |
| 284 | |
| 285 | /** |
| 286 | * radeon_fence_wait_seq - wait for a specific sequence numbers |
| 287 | * |
| 288 | * @rdev: radeon device pointer |
| 289 | * @target_seq: sequence number(s) we want to wait for |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 290 | * @intr: use interruptable sleep |
| 291 | * @lock_ring: whether the ring should be locked or not |
| 292 | * |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 293 | * Wait for the requested sequence number(s) to be written by any ring |
| 294 | * (all asics). Sequnce number array is indexed by ring id. |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 295 | * @intr selects whether to use interruptable (true) or non-interruptable |
| 296 | * (false) sleep when waiting for the sequence number. Helper function |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 297 | * for radeon_fence_wait_*(). |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 298 | * Returns 0 if the sequence number has passed, error for all other cases. |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 299 | * -EDEADLK is returned when a GPU lockup has been detected. |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 300 | */ |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 301 | static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq, |
| 302 | bool intr, bool lock_ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | { |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 304 | uint64_t last_seq[RADEON_NUM_RINGS]; |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 305 | bool signaled; |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 306 | int i, r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 307 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 308 | while (!radeon_fence_any_seq_signaled(rdev, target_seq)) { |
| 309 | |
| 310 | /* Save current sequence values, used to check for GPU lockups */ |
| 311 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 312 | if (!target_seq[i]) |
| 313 | continue; |
| 314 | |
| 315 | last_seq[i] = atomic64_read(&rdev->fence_drv[i].last_seq); |
Christian König | 1d78416 | 2014-01-23 14:24:17 +0100 | [diff] [blame] | 316 | trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]); |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 317 | radeon_irq_kms_sw_irq_get(rdev, i); |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 318 | } |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 319 | |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 320 | if (intr) { |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 321 | r = wait_event_interruptible_timeout(rdev->fence_queue, ( |
| 322 | (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)) |
| 323 | || rdev->needs_reset), RADEON_FENCE_JIFFIES_TIMEOUT); |
| 324 | } else { |
| 325 | r = wait_event_timeout(rdev->fence_queue, ( |
| 326 | (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)) |
| 327 | || rdev->needs_reset), RADEON_FENCE_JIFFIES_TIMEOUT); |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 328 | } |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 329 | |
| 330 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 331 | if (!target_seq[i]) |
| 332 | continue; |
| 333 | |
| 334 | radeon_irq_kms_sw_irq_put(rdev, i); |
Christian König | 1d78416 | 2014-01-23 14:24:17 +0100 | [diff] [blame] | 335 | trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]); |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 336 | } |
| 337 | |
| 338 | if (unlikely(r < 0)) |
Thomas Hellstrom | 5cc6fba | 2009-12-07 18:36:19 +0100 | [diff] [blame] | 339 | return r; |
Christian König | 25a9e35 | 2012-05-02 15:11:10 +0200 | [diff] [blame] | 340 | |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 341 | if (unlikely(!signaled)) { |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 342 | if (rdev->needs_reset) |
| 343 | return -EDEADLK; |
| 344 | |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 345 | /* we were interrupted for some reason and fence |
| 346 | * isn't signaled yet, resume waiting */ |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 347 | if (r) |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 348 | continue; |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 349 | |
| 350 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 351 | if (!target_seq[i]) |
| 352 | continue; |
| 353 | |
| 354 | if (last_seq[i] != atomic64_read(&rdev->fence_drv[i].last_seq)) |
| 355 | break; |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 356 | } |
Christian König | 25a9e35 | 2012-05-02 15:11:10 +0200 | [diff] [blame] | 357 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 358 | if (i != RADEON_NUM_RINGS) |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 359 | continue; |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 360 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 361 | if (lock_ring) |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 362 | mutex_lock(&rdev->ring_lock); |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 363 | |
| 364 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 365 | if (!target_seq[i]) |
| 366 | continue; |
| 367 | |
| 368 | if (radeon_ring_is_lockup(rdev, i, &rdev->ring[i])) |
| 369 | break; |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 370 | } |
| 371 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 372 | if (i < RADEON_NUM_RINGS) { |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 373 | /* good news we believe it's a lockup */ |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 374 | dev_warn(rdev->dev, "GPU lockup (waiting for " |
| 375 | "0x%016llx last fence id 0x%016llx on" |
| 376 | " ring %d)\n", |
| 377 | target_seq[i], last_seq[i], i); |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 378 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 379 | /* remember that we need an reset */ |
| 380 | rdev->needs_reset = true; |
| 381 | if (lock_ring) |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 382 | mutex_unlock(&rdev->ring_lock); |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 383 | wake_up_all(&rdev->fence_queue); |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 384 | return -EDEADLK; |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 385 | } |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 386 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 387 | if (lock_ring) |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 388 | mutex_unlock(&rdev->ring_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 389 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 390 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 391 | return 0; |
| 392 | } |
| 393 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 394 | /** |
| 395 | * radeon_fence_wait - wait for a fence to signal |
| 396 | * |
| 397 | * @fence: radeon fence object |
| 398 | * @intr: use interruptable sleep |
| 399 | * |
| 400 | * Wait for the requested fence to signal (all asics). |
| 401 | * @intr selects whether to use interruptable (true) or non-interruptable |
| 402 | * (false) sleep when waiting for the fence. |
| 403 | * Returns 0 if the fence has passed, error for all other cases. |
| 404 | */ |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 405 | int radeon_fence_wait(struct radeon_fence *fence, bool intr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 406 | { |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 407 | uint64_t seq[RADEON_NUM_RINGS] = {}; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 408 | int r; |
| 409 | |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 410 | if (fence == NULL) { |
| 411 | WARN(1, "Querying an invalid fence : %p !\n", fence); |
| 412 | return -EINVAL; |
Christian König | 25a9e35 | 2012-05-02 15:11:10 +0200 | [diff] [blame] | 413 | } |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 414 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 415 | seq[fence->ring] = fence->seq; |
| 416 | if (seq[fence->ring] == RADEON_FENCE_SIGNALED_SEQ) |
| 417 | return 0; |
| 418 | |
| 419 | r = radeon_fence_wait_seq(fence->rdev, seq, intr, true); |
| 420 | if (r) |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 421 | return r; |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 422 | |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 423 | fence->seq = RADEON_FENCE_SIGNALED_SEQ; |
| 424 | return 0; |
| 425 | } |
| 426 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 427 | /** |
| 428 | * radeon_fence_wait_any - wait for a fence to signal on any ring |
| 429 | * |
| 430 | * @rdev: radeon device pointer |
| 431 | * @fences: radeon fence object(s) |
| 432 | * @intr: use interruptable sleep |
| 433 | * |
| 434 | * Wait for any requested fence to signal (all asics). Fence |
| 435 | * array is indexed by ring id. @intr selects whether to use |
| 436 | * interruptable (true) or non-interruptable (false) sleep when |
| 437 | * waiting for the fences. Used by the suballocator. |
| 438 | * Returns 0 if any fence has passed, error for all other cases. |
| 439 | */ |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 440 | int radeon_fence_wait_any(struct radeon_device *rdev, |
| 441 | struct radeon_fence **fences, |
| 442 | bool intr) |
| 443 | { |
| 444 | uint64_t seq[RADEON_NUM_RINGS]; |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 445 | unsigned i, num_rings = 0; |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 446 | int r; |
| 447 | |
| 448 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 449 | seq[i] = 0; |
| 450 | |
| 451 | if (!fences[i]) { |
| 452 | continue; |
| 453 | } |
| 454 | |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 455 | seq[i] = fences[i]->seq; |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 456 | ++num_rings; |
| 457 | |
| 458 | /* test if something was allready signaled */ |
| 459 | if (seq[i] == RADEON_FENCE_SIGNALED_SEQ) |
| 460 | return 0; |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 461 | } |
| 462 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 463 | /* nothing to wait for ? */ |
| 464 | if (num_rings == 0) |
| 465 | return -ENOENT; |
| 466 | |
| 467 | r = radeon_fence_wait_seq(rdev, seq, intr, true); |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 468 | if (r) { |
| 469 | return r; |
| 470 | } |
| 471 | return 0; |
| 472 | } |
| 473 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 474 | /** |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 475 | * radeon_fence_wait_locked - wait for a fence to signal |
| 476 | * |
| 477 | * @fence: radeon fence object |
| 478 | * |
| 479 | * Wait for the requested fence to signal (all asics). |
| 480 | * Returns 0 if the fence has passed, error for all other cases. |
| 481 | */ |
| 482 | int radeon_fence_wait_locked(struct radeon_fence *fence) |
| 483 | { |
| 484 | uint64_t seq[RADEON_NUM_RINGS] = {}; |
| 485 | int r; |
| 486 | |
| 487 | if (fence == NULL) { |
| 488 | WARN(1, "Querying an invalid fence : %p !\n", fence); |
| 489 | return -EINVAL; |
| 490 | } |
| 491 | |
| 492 | seq[fence->ring] = fence->seq; |
| 493 | if (seq[fence->ring] == RADEON_FENCE_SIGNALED_SEQ) |
| 494 | return 0; |
| 495 | |
| 496 | r = radeon_fence_wait_seq(fence->rdev, seq, false, false); |
| 497 | if (r) |
| 498 | return r; |
| 499 | |
| 500 | fence->seq = RADEON_FENCE_SIGNALED_SEQ; |
| 501 | return 0; |
| 502 | } |
| 503 | |
| 504 | /** |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 505 | * radeon_fence_wait_next_locked - wait for the next fence to signal |
| 506 | * |
| 507 | * @rdev: radeon device pointer |
| 508 | * @ring: ring index the fence is associated with |
| 509 | * |
| 510 | * Wait for the next fence on the requested ring to signal (all asics). |
| 511 | * Returns 0 if the next fence has passed, error for all other cases. |
| 512 | * Caller must hold ring lock. |
| 513 | */ |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 514 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring) |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 515 | { |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 516 | uint64_t seq[RADEON_NUM_RINGS] = {}; |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 517 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 518 | seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL; |
| 519 | if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) { |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 520 | /* nothing to wait for, last_seq is |
| 521 | already the last emited fence */ |
| 522 | return -ENOENT; |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 523 | } |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 524 | return radeon_fence_wait_seq(rdev, seq, false, false); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 525 | } |
| 526 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 527 | /** |
| 528 | * radeon_fence_wait_empty_locked - wait for all fences to signal |
| 529 | * |
| 530 | * @rdev: radeon device pointer |
| 531 | * @ring: ring index the fence is associated with |
| 532 | * |
| 533 | * Wait for all fences on the requested ring to signal (all asics). |
| 534 | * Returns 0 if the fences have passed, error for all other cases. |
| 535 | * Caller must hold ring lock. |
| 536 | */ |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 537 | int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 538 | { |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 539 | uint64_t seq[RADEON_NUM_RINGS] = {}; |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 540 | int r; |
Christian König | 7ecc45e | 2012-06-29 11:33:12 +0200 | [diff] [blame] | 541 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 542 | seq[ring] = rdev->fence_drv[ring].sync_seq[ring]; |
Christian König | 721529b | 2013-11-05 14:09:54 +0100 | [diff] [blame] | 543 | if (!seq[ring]) |
| 544 | return 0; |
| 545 | |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 546 | r = radeon_fence_wait_seq(rdev, seq, false, false); |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 547 | if (r) { |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 548 | if (r == -EDEADLK) |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 549 | return -EDEADLK; |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 550 | |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 551 | dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n", |
| 552 | ring, r); |
Christian König | 7ecc45e | 2012-06-29 11:33:12 +0200 | [diff] [blame] | 553 | } |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 554 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 555 | } |
| 556 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 557 | /** |
| 558 | * radeon_fence_ref - take a ref on a fence |
| 559 | * |
| 560 | * @fence: radeon fence object |
| 561 | * |
| 562 | * Take a reference on a fence (all asics). |
| 563 | * Returns the fence. |
| 564 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 565 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence) |
| 566 | { |
| 567 | kref_get(&fence->kref); |
| 568 | return fence; |
| 569 | } |
| 570 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 571 | /** |
| 572 | * radeon_fence_unref - remove a ref on a fence |
| 573 | * |
| 574 | * @fence: radeon fence object |
| 575 | * |
| 576 | * Remove a reference on a fence (all asics). |
| 577 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 578 | void radeon_fence_unref(struct radeon_fence **fence) |
| 579 | { |
| 580 | struct radeon_fence *tmp = *fence; |
| 581 | |
| 582 | *fence = NULL; |
| 583 | if (tmp) { |
Paul Bolle | cdb650a | 2011-02-27 01:34:08 +0100 | [diff] [blame] | 584 | kref_put(&tmp->kref, radeon_fence_destroy); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 585 | } |
| 586 | } |
| 587 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 588 | /** |
| 589 | * radeon_fence_count_emitted - get the count of emitted fences |
| 590 | * |
| 591 | * @rdev: radeon device pointer |
| 592 | * @ring: ring index the fence is associated with |
| 593 | * |
| 594 | * Get the number of fences emitted on the requested ring (all asics). |
| 595 | * Returns the number of emitted fences on the ring. Used by the |
| 596 | * dynpm code to ring track activity. |
| 597 | */ |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 598 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 599 | { |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 600 | uint64_t emitted; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 601 | |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 602 | /* We are not protected by ring lock when reading the last sequence |
| 603 | * but it's ok to report slightly wrong fence count here. |
| 604 | */ |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 605 | radeon_fence_process(rdev, ring); |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 606 | emitted = rdev->fence_drv[ring].sync_seq[ring] |
| 607 | - atomic64_read(&rdev->fence_drv[ring].last_seq); |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 608 | /* to avoid 32bits warp around */ |
| 609 | if (emitted > 0x10000000) { |
| 610 | emitted = 0x10000000; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 611 | } |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 612 | return (unsigned)emitted; |
Christian König | 47492a2 | 2011-10-20 12:38:09 +0200 | [diff] [blame] | 613 | } |
| 614 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 615 | /** |
| 616 | * radeon_fence_need_sync - do we need a semaphore |
| 617 | * |
| 618 | * @fence: radeon fence object |
| 619 | * @dst_ring: which ring to check against |
| 620 | * |
| 621 | * Check if the fence needs to be synced against another ring |
| 622 | * (all asics). If so, we need to emit a semaphore. |
| 623 | * Returns true if we need to sync with another ring, false if |
| 624 | * not. |
| 625 | */ |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 626 | bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring) |
| 627 | { |
| 628 | struct radeon_fence_driver *fdrv; |
| 629 | |
| 630 | if (!fence) { |
| 631 | return false; |
| 632 | } |
| 633 | |
| 634 | if (fence->ring == dst_ring) { |
| 635 | return false; |
| 636 | } |
| 637 | |
| 638 | /* we are protected by the ring mutex */ |
| 639 | fdrv = &fence->rdev->fence_drv[dst_ring]; |
| 640 | if (fence->seq <= fdrv->sync_seq[fence->ring]) { |
| 641 | return false; |
| 642 | } |
| 643 | |
| 644 | return true; |
| 645 | } |
| 646 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 647 | /** |
| 648 | * radeon_fence_note_sync - record the sync point |
| 649 | * |
| 650 | * @fence: radeon fence object |
| 651 | * @dst_ring: which ring to check against |
| 652 | * |
| 653 | * Note the sequence number at which point the fence will |
| 654 | * be synced with the requested ring (all asics). |
| 655 | */ |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 656 | void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring) |
| 657 | { |
| 658 | struct radeon_fence_driver *dst, *src; |
| 659 | unsigned i; |
| 660 | |
| 661 | if (!fence) { |
| 662 | return; |
| 663 | } |
| 664 | |
| 665 | if (fence->ring == dst_ring) { |
| 666 | return; |
| 667 | } |
| 668 | |
| 669 | /* we are protected by the ring mutex */ |
| 670 | src = &fence->rdev->fence_drv[fence->ring]; |
| 671 | dst = &fence->rdev->fence_drv[dst_ring]; |
| 672 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 673 | if (i == dst_ring) { |
| 674 | continue; |
| 675 | } |
| 676 | dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]); |
| 677 | } |
| 678 | } |
| 679 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 680 | /** |
| 681 | * radeon_fence_driver_start_ring - make the fence driver |
| 682 | * ready for use on the requested ring. |
| 683 | * |
| 684 | * @rdev: radeon device pointer |
| 685 | * @ring: ring index to start the fence driver on |
| 686 | * |
| 687 | * Make the fence driver ready for processing (all asics). |
| 688 | * Not all asics have all rings, so each asic will only |
| 689 | * start the fence driver on the rings it has. |
| 690 | * Returns 0 for success, errors for failure. |
| 691 | */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 692 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 693 | { |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 694 | uint64_t index; |
| 695 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 696 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 697 | radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); |
Jerome Glisse | 86a1881 | 2012-12-12 16:43:15 -0500 | [diff] [blame] | 698 | if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) { |
Christian König | 581bc3a | 2013-04-24 14:11:09 +0200 | [diff] [blame] | 699 | rdev->fence_drv[ring].scratch_reg = 0; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 700 | if (ring != R600_RING_TYPE_UVD_INDEX) { |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 701 | index = R600_WB_EVENT_OFFSET + ring * 4; |
| 702 | rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4]; |
| 703 | rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + |
| 704 | index; |
| 705 | |
| 706 | } else { |
| 707 | /* put fence directly behind firmware */ |
Christian König | 4ad9c1c | 2013-08-05 14:10:55 +0200 | [diff] [blame] | 708 | index = ALIGN(rdev->uvd_fw->size, 8); |
Christian König | d7c605a | 2013-04-14 12:47:59 +0200 | [diff] [blame] | 709 | rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index; |
| 710 | rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 711 | } |
| 712 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 713 | } else { |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 714 | r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg); |
| 715 | if (r) { |
| 716 | dev_err(rdev->dev, "fence failed to get scratch register\n"); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 717 | return r; |
| 718 | } |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 719 | index = RADEON_WB_SCRATCH_OFFSET + |
| 720 | rdev->fence_drv[ring].scratch_reg - |
| 721 | rdev->scratch.reg_base; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 722 | rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4]; |
| 723 | rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 724 | } |
Christian König | 31be618 | 2012-07-07 13:10:39 +0200 | [diff] [blame] | 725 | radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring); |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 726 | rdev->fence_drv[ring].initialized = true; |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 727 | dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n", |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 728 | ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr); |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 729 | return 0; |
| 730 | } |
| 731 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 732 | /** |
| 733 | * radeon_fence_driver_init_ring - init the fence driver |
| 734 | * for the requested ring. |
| 735 | * |
| 736 | * @rdev: radeon device pointer |
| 737 | * @ring: ring index to start the fence driver on |
| 738 | * |
| 739 | * Init the fence driver for the requested ring (all asics). |
| 740 | * Helper function for radeon_fence_driver_init(). |
| 741 | */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 742 | static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring) |
| 743 | { |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 744 | int i; |
| 745 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 746 | rdev->fence_drv[ring].scratch_reg = -1; |
| 747 | rdev->fence_drv[ring].cpu_addr = NULL; |
| 748 | rdev->fence_drv[ring].gpu_addr = 0; |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 749 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
| 750 | rdev->fence_drv[ring].sync_seq[i] = 0; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 751 | atomic64_set(&rdev->fence_drv[ring].last_seq, 0); |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 752 | rdev->fence_drv[ring].initialized = false; |
| 753 | } |
| 754 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 755 | /** |
| 756 | * radeon_fence_driver_init - init the fence driver |
| 757 | * for all possible rings. |
| 758 | * |
| 759 | * @rdev: radeon device pointer |
| 760 | * |
| 761 | * Init the fence driver for all possible rings (all asics). |
| 762 | * Not all asics have all rings, so each asic will only |
| 763 | * start the fence driver on the rings it has using |
| 764 | * radeon_fence_driver_start_ring(). |
| 765 | * Returns 0 for success. |
| 766 | */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 767 | int radeon_fence_driver_init(struct radeon_device *rdev) |
| 768 | { |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 769 | int ring; |
| 770 | |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 771 | init_waitqueue_head(&rdev->fence_queue); |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 772 | for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { |
| 773 | radeon_fence_driver_init_ring(rdev, ring); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 774 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 775 | if (radeon_debugfs_fence_init(rdev)) { |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 776 | dev_err(rdev->dev, "fence debugfs file creation failed\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 777 | } |
| 778 | return 0; |
| 779 | } |
| 780 | |
Alex Deucher | d66b7ec | 2012-07-17 14:02:37 -0400 | [diff] [blame] | 781 | /** |
| 782 | * radeon_fence_driver_fini - tear down the fence driver |
| 783 | * for all possible rings. |
| 784 | * |
| 785 | * @rdev: radeon device pointer |
| 786 | * |
| 787 | * Tear down the fence driver for all possible rings (all asics). |
| 788 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 789 | void radeon_fence_driver_fini(struct radeon_device *rdev) |
| 790 | { |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 791 | int ring, r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 792 | |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 793 | mutex_lock(&rdev->ring_lock); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 794 | for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { |
| 795 | if (!rdev->fence_drv[ring].initialized) |
| 796 | continue; |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 797 | r = radeon_fence_wait_empty_locked(rdev, ring); |
| 798 | if (r) { |
| 799 | /* no need to trigger GPU reset as we are unloading */ |
| 800 | radeon_fence_driver_force_completion(rdev); |
| 801 | } |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 802 | wake_up_all(&rdev->fence_queue); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 803 | radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 804 | rdev->fence_drv[ring].initialized = false; |
| 805 | } |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 806 | mutex_unlock(&rdev->ring_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 807 | } |
| 808 | |
Jerome Glisse | 76903b9 | 2012-12-17 10:29:06 -0500 | [diff] [blame] | 809 | /** |
| 810 | * radeon_fence_driver_force_completion - force all fence waiter to complete |
| 811 | * |
| 812 | * @rdev: radeon device pointer |
| 813 | * |
| 814 | * In case of GPU reset failure make sure no process keep waiting on fence |
| 815 | * that will never complete. |
| 816 | */ |
| 817 | void radeon_fence_driver_force_completion(struct radeon_device *rdev) |
| 818 | { |
| 819 | int ring; |
| 820 | |
| 821 | for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { |
| 822 | if (!rdev->fence_drv[ring].initialized) |
| 823 | continue; |
| 824 | radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring); |
| 825 | } |
| 826 | } |
| 827 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 828 | |
| 829 | /* |
| 830 | * Fence debugfs |
| 831 | */ |
| 832 | #if defined(CONFIG_DEBUG_FS) |
| 833 | static int radeon_debugfs_fence_info(struct seq_file *m, void *data) |
| 834 | { |
| 835 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 836 | struct drm_device *dev = node->minor->dev; |
| 837 | struct radeon_device *rdev = dev->dev_private; |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 838 | int i, j; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 839 | |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 840 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 841 | if (!rdev->fence_drv[i].initialized) |
| 842 | continue; |
| 843 | |
Christian König | e290b63 | 2013-12-12 09:42:39 +0100 | [diff] [blame] | 844 | radeon_fence_process(rdev, i); |
| 845 | |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 846 | seq_printf(m, "--- ring %d ---\n", i); |
Dave Airlie | d3029b4 | 2012-05-09 17:27:29 +0100 | [diff] [blame] | 847 | seq_printf(m, "Last signaled fence 0x%016llx\n", |
| 848 | (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq)); |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 849 | seq_printf(m, "Last emitted 0x%016llx\n", |
| 850 | rdev->fence_drv[i].sync_seq[i]); |
| 851 | |
| 852 | for (j = 0; j < RADEON_NUM_RINGS; ++j) { |
| 853 | if (i != j && rdev->fence_drv[j].initialized) |
| 854 | seq_printf(m, "Last sync to ring %d 0x%016llx\n", |
| 855 | j, rdev->fence_drv[i].sync_seq[j]); |
| 856 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 857 | } |
| 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | static struct drm_info_list radeon_debugfs_fence_list[] = { |
| 862 | {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL}, |
| 863 | }; |
| 864 | #endif |
| 865 | |
| 866 | int radeon_debugfs_fence_init(struct radeon_device *rdev) |
| 867 | { |
| 868 | #if defined(CONFIG_DEBUG_FS) |
| 869 | return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1); |
| 870 | #else |
| 871 | return 0; |
| 872 | #endif |
| 873 | } |