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wanzongshun7ec80dd2008-12-03 03:55:38 +01001/*
2 * linux/arch/arm/mach-w90x900/time.c
3 *
4 * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
5 *
wanzongshun58b53692009-08-14 15:36:44 +01006 * Copyright (c) 2009 Nuvoton technology corporation
wanzongshun7ec80dd2008-12-03 03:55:38 +01007 * All rights reserved.
8 *
9 * Wan ZongShun <mcuos.com@gmail.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/leds.h>
wanzongshun58b53692009-08-14 15:36:44 +010026#include <linux/clocksource.h>
27#include <linux/clockchips.h>
wanzongshun7ec80dd2008-12-03 03:55:38 +010028
29#include <asm/mach-types.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/time.h>
32
wanzongshun7ec80dd2008-12-03 03:55:38 +010033#include <mach/map.h>
34#include <mach/regs-timer.h>
35
Russell Kinge5bc9e22011-11-07 18:02:39 +000036#include "nuc9xx.h"
37
wanzongshun58b53692009-08-14 15:36:44 +010038#define RESETINT 0x1f
39#define PERIOD (0x01 << 27)
40#define ONESHOT (0x00 << 27)
41#define COUNTEN (0x01 << 30)
42#define INTEN (0x01 << 29)
43
44#define TICKS_PER_SEC 100
45#define PRESCALE 0x63 /* Divider = prescale + 1 */
46
Li Jie1368c512009-12-31 15:57:53 +010047#define TDR_SHIFT 24
Li Jie1368c512009-12-31 15:57:53 +010048
49static unsigned int timer0_load;
wanzongshun58b53692009-08-14 15:36:44 +010050
wanzongshun35c92212009-08-21 07:07:46 +010051static void nuc900_clockevent_setmode(enum clock_event_mode mode,
wanzongshun58b53692009-08-14 15:36:44 +010052 struct clock_event_device *clk)
wanzongshun7ec80dd2008-12-03 03:55:38 +010053{
wanzongshun58b53692009-08-14 15:36:44 +010054 unsigned int val;
55
56 val = __raw_readl(REG_TCSR0);
57 val &= ~(0x03 << 27);
58
59 switch (mode) {
60 case CLOCK_EVT_MODE_PERIODIC:
61 __raw_writel(timer0_load, REG_TICR0);
62 val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
63 break;
64
65 case CLOCK_EVT_MODE_ONESHOT:
66 val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
67 break;
68
69 case CLOCK_EVT_MODE_UNUSED:
70 case CLOCK_EVT_MODE_SHUTDOWN:
71 case CLOCK_EVT_MODE_RESUME:
72 break;
73 }
74
75 __raw_writel(val, REG_TCSR0);
76}
77
wanzongshun35c92212009-08-21 07:07:46 +010078static int nuc900_clockevent_setnextevent(unsigned long evt,
wanzongshun58b53692009-08-14 15:36:44 +010079 struct clock_event_device *clk)
80{
81 unsigned int val;
82
83 __raw_writel(evt, REG_TICR0);
84
85 val = __raw_readl(REG_TCSR0);
86 val |= (COUNTEN | INTEN | PRESCALE);
87 __raw_writel(val, REG_TCSR0);
88
wanzongshun7ec80dd2008-12-03 03:55:38 +010089 return 0;
90}
91
wanzongshun35c92212009-08-21 07:07:46 +010092static struct clock_event_device nuc900_clockevent_device = {
93 .name = "nuc900-timer0",
wanzongshun58b53692009-08-14 15:36:44 +010094 .shift = 32,
Li Jie1368c512009-12-31 15:57:53 +010095 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
wanzongshun35c92212009-08-21 07:07:46 +010096 .set_mode = nuc900_clockevent_setmode,
97 .set_next_event = nuc900_clockevent_setnextevent,
wanzongshun58b53692009-08-14 15:36:44 +010098 .rating = 300,
99};
100
wanzongshun7ec80dd2008-12-03 03:55:38 +0100101/*IRQ handler for the timer*/
102
wanzongshun35c92212009-08-21 07:07:46 +0100103static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100104{
wanzongshun35c92212009-08-21 07:07:46 +0100105 struct clock_event_device *evt = &nuc900_clockevent_device;
wanzongshun58b53692009-08-14 15:36:44 +0100106
wanzongshun7ec80dd2008-12-03 03:55:38 +0100107 __raw_writel(0x01, REG_TISR); /* clear TIF0 */
wanzongshun58b53692009-08-14 15:36:44 +0100108
109 evt->event_handler(evt);
wanzongshun7ec80dd2008-12-03 03:55:38 +0100110 return IRQ_HANDLED;
111}
112
wanzongshun35c92212009-08-21 07:07:46 +0100113static struct irqaction nuc900_timer0_irq = {
114 .name = "nuc900-timer0",
wanzongshun7ec80dd2008-12-03 03:55:38 +0100115 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
wanzongshun35c92212009-08-21 07:07:46 +0100116 .handler = nuc900_timer0_interrupt,
wanzongshun7ec80dd2008-12-03 03:55:38 +0100117};
118
Li Jie1368c512009-12-31 15:57:53 +0100119static void __init nuc900_clockevents_init(void)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100120{
Li Jie1368c512009-12-31 15:57:53 +0100121 unsigned int rate;
122 struct clk *clk = clk_get(NULL, "timer0");
123
124 BUG_ON(IS_ERR(clk));
125
126 __raw_writel(0x00, REG_TCSR0);
127
128 clk_enable(clk);
129 rate = clk_get_rate(clk) / (PRESCALE + 1);
130
131 timer0_load = (rate / TICKS_PER_SEC);
132
133 __raw_writel(RESETINT, REG_TISR);
134 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
135
wanzongshun35c92212009-08-21 07:07:46 +0100136 nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
137 nuc900_clockevent_device.shift);
138 nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
139 &nuc900_clockevent_device);
140 nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
141 &nuc900_clockevent_device);
142 nuc900_clockevent_device.cpumask = cpumask_of(0);
wanzongshun58b53692009-08-14 15:36:44 +0100143
wanzongshun35c92212009-08-21 07:07:46 +0100144 clockevents_register_device(&nuc900_clockevent_device);
wanzongshun7ec80dd2008-12-03 03:55:38 +0100145}
146
Li Jie1368c512009-12-31 15:57:53 +0100147static void __init nuc900_clocksource_init(void)
wanzongshun58b53692009-08-14 15:36:44 +0100148{
149 unsigned int val;
Li Jie1368c512009-12-31 15:57:53 +0100150 unsigned int rate;
151 struct clk *clk = clk_get(NULL, "timer1");
152
153 BUG_ON(IS_ERR(clk));
154
155 __raw_writel(0x00, REG_TCSR1);
156
157 clk_enable(clk);
158 rate = clk_get_rate(clk) / (PRESCALE + 1);
wanzongshun58b53692009-08-14 15:36:44 +0100159
160 __raw_writel(0xffffffff, REG_TICR1);
161
162 val = __raw_readl(REG_TCSR1);
Li Jie1368c512009-12-31 15:57:53 +0100163 val |= (COUNTEN | PERIOD | PRESCALE);
wanzongshun58b53692009-08-14 15:36:44 +0100164 __raw_writel(val, REG_TCSR1);
165
Russell King6fa5d5f2011-05-08 15:34:39 +0100166 clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200,
167 TDR_SHIFT, clocksource_mmio_readl_down);
wanzongshun58b53692009-08-14 15:36:44 +0100168}
169
wanzongshun35c92212009-08-21 07:07:46 +0100170static void __init nuc900_timer_init(void)
wanzongshun58b53692009-08-14 15:36:44 +0100171{
Li Jie1368c512009-12-31 15:57:53 +0100172 nuc900_clocksource_init();
173 nuc900_clockevents_init();
wanzongshun7ec80dd2008-12-03 03:55:38 +0100174}
175
wanzongshun35c92212009-08-21 07:07:46 +0100176struct sys_timer nuc900_timer = {
177 .init = nuc900_timer_init,
wanzongshun7ec80dd2008-12-03 03:55:38 +0100178};