Jay Cliburn | 305282b | 2008-02-02 19:50:04 -0600 | [diff] [blame^] | 1 | /* atlx_hw.h -- common hardware definitions for Attansic network drivers |
| 2 | * |
| 3 | * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. |
| 4 | * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> |
| 5 | * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com> |
| 6 | * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
| 7 | * |
| 8 | * Derived from Intel e1000 driver |
| 9 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the Free |
| 13 | * Software Foundation; either version 2 of the License, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 19 | * more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License along with |
| 22 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 23 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 24 | */ |
| 25 | |
| 26 | #ifndef ATLX_H |
| 27 | #define ATLX_H |
| 28 | |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/types.h> |
| 31 | |
| 32 | #define ATLX_DRIVER_VERSION "2.1.1" |
| 33 | MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \ |
| 34 | Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>"); |
| 35 | MODULE_LICENSE("GPL"); |
| 36 | MODULE_VERSION(ATLX_DRIVER_VERSION); |
| 37 | |
| 38 | #define ATLX_ERR_PHY 2 |
| 39 | #define ATLX_ERR_PHY_SPEED 7 |
| 40 | #define ATLX_ERR_PHY_RES 8 |
| 41 | |
| 42 | #define SPEED_0 0xffff |
| 43 | #define SPEED_10 10 |
| 44 | #define SPEED_100 100 |
| 45 | #define SPEED_1000 1000 |
| 46 | #define HALF_DUPLEX 1 |
| 47 | #define FULL_DUPLEX 2 |
| 48 | |
| 49 | #define MEDIA_TYPE_AUTO_SENSOR 0 |
| 50 | |
| 51 | /* register definitions */ |
| 52 | #define REG_PM_CTRLSTAT 0x44 |
| 53 | |
| 54 | #define REG_PCIE_CAP_LIST 0x58 |
| 55 | |
| 56 | #define REG_VPD_CAP 0x6C |
| 57 | #define VPD_CAP_ID_MASK 0xFF |
| 58 | #define VPD_CAP_ID_SHIFT 0 |
| 59 | #define VPD_CAP_NEXT_PTR_MASK 0xFF |
| 60 | #define VPD_CAP_NEXT_PTR_SHIFT 8 |
| 61 | #define VPD_CAP_VPD_ADDR_MASK 0x7FFF |
| 62 | #define VPD_CAP_VPD_ADDR_SHIFT 16 |
| 63 | #define VPD_CAP_VPD_FLAG 0x80000000 |
| 64 | |
| 65 | #define REG_VPD_DATA 0x70 |
| 66 | |
| 67 | #define REG_SPI_FLASH_CTRL 0x200 |
| 68 | #define SPI_FLASH_CTRL_STS_NON_RDY 0x1 |
| 69 | #define SPI_FLASH_CTRL_STS_WEN 0x2 |
| 70 | #define SPI_FLASH_CTRL_STS_WPEN 0x80 |
| 71 | #define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF |
| 72 | #define SPI_FLASH_CTRL_DEV_STS_SHIFT 0 |
| 73 | #define SPI_FLASH_CTRL_INS_MASK 0x7 |
| 74 | #define SPI_FLASH_CTRL_INS_SHIFT 8 |
| 75 | #define SPI_FLASH_CTRL_START 0x800 |
| 76 | #define SPI_FLASH_CTRL_EN_VPD 0x2000 |
| 77 | #define SPI_FLASH_CTRL_LDSTART 0x8000 |
| 78 | #define SPI_FLASH_CTRL_CS_HI_MASK 0x3 |
| 79 | #define SPI_FLASH_CTRL_CS_HI_SHIFT 16 |
| 80 | #define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3 |
| 81 | #define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18 |
| 82 | #define SPI_FLASH_CTRL_CLK_LO_MASK 0x3 |
| 83 | #define SPI_FLASH_CTRL_CLK_LO_SHIFT 20 |
| 84 | #define SPI_FLASH_CTRL_CLK_HI_MASK 0x3 |
| 85 | #define SPI_FLASH_CTRL_CLK_HI_SHIFT 22 |
| 86 | #define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3 |
| 87 | #define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24 |
| 88 | #define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3 |
| 89 | #define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26 |
| 90 | #define SPI_FLASH_CTRL_WAIT_READY 0x10000000 |
| 91 | |
| 92 | #define REG_SPI_ADDR 0x204 |
| 93 | |
| 94 | #define REG_SPI_DATA 0x208 |
| 95 | |
| 96 | #define REG_SPI_FLASH_CONFIG 0x20C |
| 97 | #define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF |
| 98 | #define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0 |
| 99 | #define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3 |
| 100 | #define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24 |
| 101 | #define SPI_FLASH_CONFIG_LD_EXIST 0x4000000 |
| 102 | |
| 103 | #define REG_SPI_FLASH_OP_PROGRAM 0x210 |
| 104 | #define REG_SPI_FLASH_OP_SC_ERASE 0x211 |
| 105 | #define REG_SPI_FLASH_OP_CHIP_ERASE 0x212 |
| 106 | #define REG_SPI_FLASH_OP_RDID 0x213 |
| 107 | #define REG_SPI_FLASH_OP_WREN 0x214 |
| 108 | #define REG_SPI_FLASH_OP_RDSR 0x215 |
| 109 | #define REG_SPI_FLASH_OP_WRSR 0x216 |
| 110 | #define REG_SPI_FLASH_OP_READ 0x217 |
| 111 | |
| 112 | #define REG_TWSI_CTRL 0x218 |
| 113 | #define TWSI_CTRL_LD_OFFSET_MASK 0xFF |
| 114 | #define TWSI_CTRL_LD_OFFSET_SHIFT 0 |
| 115 | #define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 |
| 116 | #define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 |
| 117 | #define TWSI_CTRL_SW_LDSTART 0x800 |
| 118 | #define TWSI_CTRL_HW_LDSTART 0x1000 |
| 119 | #define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F |
| 120 | #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 |
| 121 | #define TWSI_CTRL_LD_EXIST 0x400000 |
| 122 | #define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 |
| 123 | #define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 |
| 124 | #define TWSI_CTRL_FREQ_SEL_100K 0 |
| 125 | #define TWSI_CTRL_FREQ_SEL_200K 1 |
| 126 | #define TWSI_CTRL_FREQ_SEL_300K 2 |
| 127 | #define TWSI_CTRL_FREQ_SEL_400K 3 |
| 128 | #define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */ |
| 129 | #define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 |
| 130 | #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 |
| 131 | |
| 132 | #define REG_PCIE_DEV_MISC_CTRL 0x21C |
| 133 | #define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2 |
| 134 | #define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1 |
| 135 | #define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4 |
| 136 | #define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8 |
| 137 | #define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10 |
| 138 | |
| 139 | #define REG_PCIE_PHYMISC 0x1000 |
| 140 | #define PCIE_PHYMISC_FORCE_RCV_DET 0x4 |
| 141 | |
| 142 | #define REG_PCIE_DLL_TX_CTRL1 0x1104 |
| 143 | #define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400 |
| 144 | #define PCIE_DLL_TX_CTRL1_DEF 0x568 |
| 145 | |
| 146 | #define REG_LTSSM_TEST_MODE 0x12FC |
| 147 | #define LTSSM_TEST_MODE_DEF 0x6500 |
| 148 | |
| 149 | /* Master Control Register */ |
| 150 | #define REG_MASTER_CTRL 0x1400 |
| 151 | #define MASTER_CTRL_SOFT_RST 0x1 |
| 152 | #define MASTER_CTRL_MTIMER_EN 0x2 |
| 153 | #define MASTER_CTRL_ITIMER_EN 0x4 |
| 154 | #define MASTER_CTRL_MANUAL_INT 0x8 |
| 155 | #define MASTER_CTRL_REV_NUM_SHIFT 16 |
| 156 | #define MASTER_CTRL_REV_NUM_MASK 0xFF |
| 157 | #define MASTER_CTRL_DEV_ID_SHIFT 24 |
| 158 | #define MASTER_CTRL_DEV_ID_MASK 0xFF |
| 159 | |
| 160 | /* Timer Initial Value Register */ |
| 161 | #define REG_MANUAL_TIMER_INIT 0x1404 |
| 162 | |
| 163 | /* IRQ Moderator Timer Initial Value Register */ |
| 164 | #define REG_IRQ_MODU_TIMER_INIT 0x1408 |
| 165 | |
| 166 | #define REG_PHY_ENABLE 0x140C |
| 167 | |
| 168 | /* IRQ Anti-Lost Timer Initial Value Register */ |
| 169 | #define REG_CMBDISDMA_TIMER 0x140E |
| 170 | |
| 171 | /* Block IDLE Status Register */ |
| 172 | #define REG_IDLE_STATUS 0x1410 |
| 173 | |
| 174 | /* MDIO Control Register */ |
| 175 | #define REG_MDIO_CTRL 0x1414 |
| 176 | #define MDIO_DATA_MASK 0xFFFF |
| 177 | #define MDIO_DATA_SHIFT 0 |
| 178 | #define MDIO_REG_ADDR_MASK 0x1F |
| 179 | #define MDIO_REG_ADDR_SHIFT 16 |
| 180 | #define MDIO_RW 0x200000 |
| 181 | #define MDIO_SUP_PREAMBLE 0x400000 |
| 182 | #define MDIO_START 0x800000 |
| 183 | #define MDIO_CLK_SEL_SHIFT 24 |
| 184 | #define MDIO_CLK_25_4 0 |
| 185 | #define MDIO_CLK_25_6 2 |
| 186 | #define MDIO_CLK_25_8 3 |
| 187 | #define MDIO_CLK_25_10 4 |
| 188 | #define MDIO_CLK_25_14 5 |
| 189 | #define MDIO_CLK_25_20 6 |
| 190 | #define MDIO_CLK_25_28 7 |
| 191 | #define MDIO_BUSY 0x8000000 |
| 192 | |
| 193 | /* MII PHY Status Register */ |
| 194 | #define REG_PHY_STATUS 0x1418 |
| 195 | |
| 196 | /* BIST Control and Status Register0 (for the Packet Memory) */ |
| 197 | #define REG_BIST0_CTRL 0x141C |
| 198 | #define BIST0_NOW 0x1 |
| 199 | #define BIST0_SRAM_FAIL 0x2 |
| 200 | #define BIST0_FUSE_FLAG 0x4 |
| 201 | #define REG_BIST1_CTRL 0x1420 |
| 202 | #define BIST1_NOW 0x1 |
| 203 | #define BIST1_SRAM_FAIL 0x2 |
| 204 | #define BIST1_FUSE_FLAG 0x4 |
| 205 | |
| 206 | /* SerDes Lock Detect Control and Status Register */ |
| 207 | #define REG_SERDES_LOCK 0x1424 |
| 208 | #define SERDES_LOCK_DETECT 1 |
| 209 | #define SERDES_LOCK_DETECT_EN 2 |
| 210 | |
| 211 | /* MAC Control Register */ |
| 212 | #define REG_MAC_CTRL 0x1480 |
| 213 | #define MAC_CTRL_TX_EN 1 |
| 214 | #define MAC_CTRL_RX_EN 2 |
| 215 | #define MAC_CTRL_TX_FLOW 4 |
| 216 | #define MAC_CTRL_RX_FLOW 8 |
| 217 | #define MAC_CTRL_LOOPBACK 0x10 |
| 218 | #define MAC_CTRL_DUPLX 0x20 |
| 219 | #define MAC_CTRL_ADD_CRC 0x40 |
| 220 | #define MAC_CTRL_PAD 0x80 |
| 221 | #define MAC_CTRL_LENCHK 0x100 |
| 222 | #define MAC_CTRL_HUGE_EN 0x200 |
| 223 | #define MAC_CTRL_PRMLEN_SHIFT 10 |
| 224 | #define MAC_CTRL_PRMLEN_MASK 0xF |
| 225 | #define MAC_CTRL_RMV_VLAN 0x4000 |
| 226 | #define MAC_CTRL_PROMIS_EN 0x8000 |
| 227 | #define MAC_CTRL_MC_ALL_EN 0x2000000 |
| 228 | #define MAC_CTRL_BC_EN 0x4000000 |
| 229 | |
| 230 | /* MAC IPG/IFG Control Register */ |
| 231 | #define REG_MAC_IPG_IFG 0x1484 |
| 232 | #define MAC_IPG_IFG_IPGT_SHIFT 0 |
| 233 | #define MAC_IPG_IFG_IPGT_MASK 0x7F |
| 234 | #define MAC_IPG_IFG_MIFG_SHIFT 8 |
| 235 | #define MAC_IPG_IFG_MIFG_MASK 0xFF |
| 236 | #define MAC_IPG_IFG_IPGR1_SHIFT 16 |
| 237 | #define MAC_IPG_IFG_IPGR1_MASK 0x7F |
| 238 | #define MAC_IPG_IFG_IPGR2_SHIFT 24 |
| 239 | #define MAC_IPG_IFG_IPGR2_MASK 0x7F |
| 240 | |
| 241 | /* MAC STATION ADDRESS */ |
| 242 | #define REG_MAC_STA_ADDR 0x1488 |
| 243 | |
| 244 | /* Hash table for multicast address */ |
| 245 | #define REG_RX_HASH_TABLE 0x1490 |
| 246 | |
| 247 | /* MAC Half-Duplex Control Register */ |
| 248 | #define REG_MAC_HALF_DUPLX_CTRL 0x1498 |
| 249 | #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 |
| 250 | #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF |
| 251 | #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 |
| 252 | #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF |
| 253 | #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 |
| 254 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 |
| 255 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 |
| 256 | #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 |
| 257 | #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 |
| 258 | #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF |
| 259 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 |
| 260 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF |
| 261 | |
| 262 | /* Maximum Frame Length Control Register */ |
| 263 | #define REG_MTU 0x149C |
| 264 | |
| 265 | /* Wake-On-Lan control register */ |
| 266 | #define REG_WOL_CTRL 0x14A0 |
| 267 | #define WOL_PATTERN_EN 0x1 |
| 268 | #define WOL_PATTERN_PME_EN 0x2 |
| 269 | #define WOL_MAGIC_EN 0x4 |
| 270 | #define WOL_MAGIC_PME_EN 0x8 |
| 271 | #define WOL_LINK_CHG_EN 0x10 |
| 272 | #define WOL_LINK_CHG_PME_EN 0x20 |
| 273 | #define WOL_PATTERN_ST 0x100 |
| 274 | #define WOL_MAGIC_ST 0x200 |
| 275 | #define WOL_LINKCHG_ST 0x400 |
| 276 | #define WOL_PT0_EN 0x10000 |
| 277 | #define WOL_PT1_EN 0x20000 |
| 278 | #define WOL_PT2_EN 0x40000 |
| 279 | #define WOL_PT3_EN 0x80000 |
| 280 | #define WOL_PT4_EN 0x100000 |
| 281 | #define WOL_PT0_MATCH 0x1000000 |
| 282 | #define WOL_PT1_MATCH 0x2000000 |
| 283 | #define WOL_PT2_MATCH 0x4000000 |
| 284 | #define WOL_PT3_MATCH 0x8000000 |
| 285 | #define WOL_PT4_MATCH 0x10000000 |
| 286 | |
| 287 | /* Internal SRAM Partition Register, high 32 bits */ |
| 288 | #define REG_SRAM_RFD_ADDR 0x1500 |
| 289 | |
| 290 | /* Descriptor Control register, high 32 bits */ |
| 291 | #define REG_DESC_BASE_ADDR_HI 0x1540 |
| 292 | |
| 293 | /* Interrupt Status Register */ |
| 294 | #define REG_ISR 0x1600 |
| 295 | #define ISR_UR_DETECTED 0x1000000 |
| 296 | #define ISR_FERR_DETECTED 0x2000000 |
| 297 | #define ISR_NFERR_DETECTED 0x4000000 |
| 298 | #define ISR_CERR_DETECTED 0x8000000 |
| 299 | #define ISR_PHY_LINKDOWN 0x10000000 |
| 300 | #define ISR_DIS_INT 0x80000000 |
| 301 | |
| 302 | /* Interrupt Mask Register */ |
| 303 | #define REG_IMR 0x1604 |
| 304 | |
| 305 | #define REG_RFD_RRD_IDX 0x1800 |
| 306 | #define REG_TPD_IDX 0x1804 |
| 307 | |
| 308 | /* MII definitions */ |
| 309 | |
| 310 | /* PHY Common Register */ |
| 311 | #define MII_ATLX_CR 0x09 |
| 312 | #define MII_ATLX_SR 0x0A |
| 313 | #define MII_ATLX_ESR 0x0F |
| 314 | #define MII_ATLX_PSCR 0x10 |
| 315 | #define MII_ATLX_PSSR 0x11 |
| 316 | |
| 317 | /* PHY Control Register */ |
| 318 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, |
| 319 | * 00=10 |
| 320 | */ |
| 321 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ |
| 322 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
| 323 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
| 324 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ |
| 325 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
| 326 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
| 327 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, |
| 328 | * 00=10 |
| 329 | */ |
| 330 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
| 331 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
| 332 | #define MII_CR_SPEED_MASK 0x2040 |
| 333 | #define MII_CR_SPEED_1000 0x0040 |
| 334 | #define MII_CR_SPEED_100 0x2000 |
| 335 | #define MII_CR_SPEED_10 0x0000 |
| 336 | |
| 337 | /* PHY Status Register */ |
| 338 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */ |
| 339 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ |
| 340 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
| 341 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ |
| 342 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ |
| 343 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
| 344 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ |
| 345 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */ |
| 346 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ |
| 347 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ |
| 348 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ |
| 349 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ |
| 350 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ |
| 351 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ |
| 352 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ |
| 353 | |
| 354 | /* Link partner ability register */ |
| 355 | #define MII_LPA_SLCT 0x001f /* Same as advertise selector */ |
| 356 | #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ |
| 357 | #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ |
| 358 | #define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ |
| 359 | #define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ |
| 360 | #define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */ |
| 361 | #define MII_LPA_PAUSE 0x0400 /* PAUSE */ |
| 362 | #define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */ |
| 363 | #define MII_LPA_RFAULT 0x2000 /* Link partner faulted */ |
| 364 | #define MII_LPA_LPACK 0x4000 /* Link partner acked us */ |
| 365 | #define MII_LPA_NPAGE 0x8000 /* Next page bit */ |
| 366 | |
| 367 | /* Autoneg Advertisement Register */ |
| 368 | #define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */ |
| 369 | #define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ |
| 370 | #define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ |
| 371 | #define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ |
| 372 | #define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ |
| 373 | #define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ |
| 374 | #define MII_AR_PAUSE 0x0400 /* Pause operation desired */ |
| 375 | #define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */ |
| 376 | #define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ |
| 377 | #define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */ |
| 378 | #define MII_AR_SPEED_MASK 0x01E0 |
| 379 | #define MII_AR_DEFAULT_CAP_MASK 0x0DE0 |
| 380 | |
| 381 | /* 1000BASE-T Control Register */ |
| 382 | #define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */ |
| 383 | #define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */ |
| 384 | #define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device, |
| 385 | * 0=DTE device */ |
| 386 | #define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master, |
| 387 | * 0=Configure PHY as Slave */ |
| 388 | #define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config, |
| 389 | * 0=Auto Master/Slave config |
| 390 | */ |
| 391 | #define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ |
| 392 | #define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ |
| 393 | #define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */ |
| 394 | #define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */ |
| 395 | #define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */ |
| 396 | #define MII_ATLX_CR_1000T_SPEED_MASK 0x0300 |
| 397 | #define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300 |
| 398 | |
| 399 | /* 1000BASE-T Status Register */ |
| 400 | #define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ |
| 401 | #define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ |
| 402 | #define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ |
| 403 | #define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ |
| 404 | #define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master |
| 405 | * 0=Slave |
| 406 | */ |
| 407 | #define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config |
| 408 | * fault */ |
| 409 | #define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12 |
| 410 | #define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13 |
| 411 | |
| 412 | /* Extended Status Register */ |
| 413 | #define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ |
| 414 | #define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ |
| 415 | #define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ |
| 416 | #define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ |
| 417 | |
| 418 | /* ATLX PHY Specific Control Register */ |
| 419 | #define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */ |
| 420 | #define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */ |
| 421 | #define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ |
| 422 | #define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008 |
| 423 | #define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low |
| 424 | * 0=CLK125 toggling |
| 425 | */ |
| 426 | #define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, |
| 427 | * Manual MDI configuration |
| 428 | */ |
| 429 | #define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ |
| 430 | #define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover |
| 431 | * 100BASE-TX/10BASE-T: MDI |
| 432 | * Mode */ |
| 433 | #define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled |
| 434 | * all speeds. |
| 435 | */ |
| 436 | #define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended |
| 437 | * 10BASE-T distance |
| 438 | * (Lower 10BASE-T RX |
| 439 | * Threshold) |
| 440 | * 0=Normal 10BASE-T RX |
| 441 | * Threshold |
| 442 | */ |
| 443 | #define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in |
| 444 | * 100BASE-TX |
| 445 | * 0=MII interface in |
| 446 | * 100BASE-TX |
| 447 | */ |
| 448 | #define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */ |
| 449 | #define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ |
| 450 | #define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |
| 451 | #define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1 |
| 452 | #define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5 |
| 453 | #define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 |
| 454 | |
| 455 | /* ATLX PHY Specific Status Register */ |
| 456 | #define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ |
| 457 | #define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ |
| 458 | #define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
| 459 | #define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */ |
| 460 | #define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */ |
| 461 | #define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ |
| 462 | |
| 463 | /* PCI Command Register Bit Definitions */ |
| 464 | #define PCI_REG_COMMAND 0x04 /* PCI Command Register */ |
| 465 | #define CMD_IO_SPACE 0x0001 |
| 466 | #define CMD_MEMORY_SPACE 0x0002 |
| 467 | #define CMD_BUS_MASTER 0x0004 |
| 468 | |
| 469 | /* Wake Up Filter Control */ |
| 470 | #define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
| 471 | #define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
| 472 | #define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
| 473 | #define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ |
| 474 | #define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
| 475 | |
| 476 | #define ADVERTISE_10_HALF 0x0001 |
| 477 | #define ADVERTISE_10_FULL 0x0002 |
| 478 | #define ADVERTISE_100_HALF 0x0004 |
| 479 | #define ADVERTISE_100_FULL 0x0008 |
| 480 | #define ADVERTISE_1000_HALF 0x0010 |
| 481 | #define ADVERTISE_1000_FULL 0x0020 |
| 482 | #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */ |
| 483 | #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */ |
| 484 | |
| 485 | #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
| 486 | #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ |
| 487 | |
| 488 | /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */ |
| 489 | #define EEPROM_SUM 0xBABA |
| 490 | #define NODE_ADDRESS_SIZE 6 |
| 491 | |
| 492 | struct atlx_spi_flash_dev { |
| 493 | const char *manu_name; /* manufacturer id */ |
| 494 | /* op-code */ |
| 495 | u8 cmd_wrsr; |
| 496 | u8 cmd_read; |
| 497 | u8 cmd_program; |
| 498 | u8 cmd_wren; |
| 499 | u8 cmd_wrdi; |
| 500 | u8 cmd_rdsr; |
| 501 | u8 cmd_rdid; |
| 502 | u8 cmd_sector_erase; |
| 503 | u8 cmd_chip_erase; |
| 504 | }; |
| 505 | |
| 506 | #endif /* ATLX_H */ |