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Andrew Lunn7e0a6b82014-05-26 21:29:49 +02001/*
2 * Device Tree file for LaCie 5Big Network v2
3 *
4 * Copyright (C) 2014
5 *
6 * Andrew Lunn <andrew@lunn.ch>
7 *
8 * Based on netxbig_v2-setup.c,
9 * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14*/
15
16/dts-v1/;
17
18#include "kirkwood.dtsi"
19#include "kirkwood-6281.dtsi"
20#include "kirkwood-netxbig.dtsi"
21
22/ {
23 model = "LaCie 5Big Network v2";
24 compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
25
26 memory {
27 device_type = "memory";
28 reg = <0x00000000 0x20000000>;
29 };
30
31};
32
33&regulators {
Simon Guinot2d4cd2c2014-07-08 16:42:24 +020034 regulator@2 {
35 compatible = "regulator-fixed";
36 reg = <2>;
37 regulator-name = "hdd1power";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 enable-active-high;
41 regulator-always-on;
42 regulator-boot-on;
43 gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
44 };
45
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020046 regulator@3 {
47 compatible = "regulator-fixed";
48 reg = <3>;
49 regulator-name = "hdd2power";
50 regulator-min-microvolt = <5000000>;
51 regulator-max-microvolt = <5000000>;
52 enable-active-high;
53 regulator-always-on;
54 regulator-boot-on;
Jason Cooperd854fa82014-06-21 19:21:13 +000055 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020056 };
57
58 regulator@4 {
59 compatible = "regulator-fixed";
60 reg = <4>;
61 regulator-name = "hdd3power";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 enable-active-high;
65 regulator-always-on;
66 regulator-boot-on;
Jason Cooperd854fa82014-06-21 19:21:13 +000067 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020068 };
69
70 regulator@5 {
71 compatible = "regulator-fixed";
72 reg = <5>;
73 regulator-name = "hdd4power";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 enable-active-high;
77 regulator-always-on;
78 regulator-boot-on;
Jason Cooperd854fa82014-06-21 19:21:13 +000079 gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020080 };
Simon Guinot2d4cd2c2014-07-08 16:42:24 +020081
82 clocks {
83 g762_clk: g762-oscillator {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <32768>;
87 };
88 };
Simon Guinot767361f2015-09-26 23:02:35 +020089
90 netxbig-leds {
91 blue-sata2 {
92 label = "netxbig:blue:sata2";
93 mode-addr = <5>;
94 mode-val = <NETXBIG_LED_OFF 0
95 NETXBIG_LED_ON 7
96 NETXBIG_LED_SATA 1
97 NETXBIG_LED_TIMER1 3>;
98 bright-addr = <2>;
99 max-brightness = <7>;
100 };
101 red-sata2 {
102 label = "netxbig:red:sata2";
103 mode-addr = <5>;
104 mode-val = <NETXBIG_LED_OFF 0
105 NETXBIG_LED_ON 2
106 NETXBIG_LED_TIMER1 4>;
107 bright-addr = <2>;
108 max-brightness = <7>;
109 };
110 blue-sata3 {
111 label = "netxbig:blue:sata3";
112 mode-addr = <6>;
113 mode-val = <NETXBIG_LED_OFF 0
114 NETXBIG_LED_ON 7
115 NETXBIG_LED_SATA 1
116 NETXBIG_LED_TIMER1 3>;
117 bright-addr = <2>;
118 max-brightness = <7>;
119 };
120 red-sata3 {
121 label = "netxbig:red:sata3";
122 mode-addr = <6>;
123 mode-val = <NETXBIG_LED_OFF 0
124 NETXBIG_LED_ON 2
125 NETXBIG_LED_TIMER1 4>;
126 bright-addr = <2>;
127 max-brightness = <7>;
128 };
129 blue-sata4 {
130 label = "netxbig:blue:sata4";
131 mode-addr = <7>;
132 mode-val = <NETXBIG_LED_OFF 0
133 NETXBIG_LED_ON 7
134 NETXBIG_LED_SATA 1
135 NETXBIG_LED_TIMER1 3>;
136 bright-addr = <2>;
137 max-brightness = <7>;
138 };
139 red-sata4 {
140 label = "netxbig:red:sata4";
141 mode-addr = <7>;
142 mode-val = <NETXBIG_LED_OFF 0
143 NETXBIG_LED_ON 2
144 NETXBIG_LED_TIMER1 4>;
145 bright-addr = <2>;
146 max-brightness = <7>;
147 };
148 };
Andrew Lunn7e0a6b82014-05-26 21:29:49 +0200149};
150
151&mdio {
152 ethphy1: ethernet-phy@1 {
153 reg = <0>;
154 };
155};
156
157&eth1 {
158 status = "okay";
159 ethernet1-port@0 {
160 phy-handle = <&ethphy1>;
161 };
162};
163
Simon Guinot2d4cd2c2014-07-08 16:42:24 +0200164
165&i2c0 {
166 g762@3e {
167 compatible = "gmt,g762";
168 reg = <0x3e>;
169 clocks = <&g762_clk>;
170 };
171};