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gerrit-public.fairphone.software / kernel / msm-4.9 / 309f15d8bbe122c5fd0f1b1a2aa1ab79a66608b6 / . / arch / arm / boot / dts / omap3.dtsi
blob: 2008648b8c9f908d8d5d04d30687e3fd87af2199 [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard71fdc6e2013-06-11 16:49:46 +0200[diff] [blame]12#include <dt-bindings/interrupt-controller/irq.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]13#include <dt-bindings/pinctrl/omap.h>
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]14
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]15/ {
16 compatible = "ti,omap3430", "ti,omap3";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]17 interrupt-parent = <&intc>;
Javier Martinez Canillas008a2eb2016-08-31 12:35:18 +0200[diff] [blame]18 #address-cells = <1>;
19 #size-cells = <1>;
Javier Martinez Canillas5921b262016-12-19 11:44:34 -0300[diff] [blame]20 chosen { };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]21
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]22 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]29 };
30
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]31 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]32 #address-cells = <1>;
33 #size-cells = <0>;
34
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]35 cpu@0 {
36 compatible = "arm,cortex-a8";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]37 device_type = "cpu";
38 reg = <0x0>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]39
40 clocks = <&dpll1_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]44 };
45 };
46
Javier Martinez Canillas2995a9e2016-04-01 16:20:20 -0400[diff] [blame]47 pmu@54000000 {
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]48 compatible = "arm,cortex-a8-pmu";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]49 reg = <0x54000000 0x800000>;
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]50 interrupts = <3>;
51 ti,hwmods = "debugss";
52 };
53
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]54 /*
Christoph Fritz161e89a2013-03-29 17:32:05 +0100[diff] [blame]55 * The soc node represents the soc top level view. It is used for IPs
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]56 * that are not memory mapped in the MPU view or for the MPU itself.
57 */
58 soc {
59 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]60 mpu {
61 compatible = "ti,omap3-mpu";
62 ti,hwmods = "mpu";
63 };
64
Suman Anna4c051602014-04-22 17:23:37 -0500[diff] [blame]65 iva: iva {
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]66 compatible = "ti,iva2.2";
67 ti,hwmods = "iva";
68
69 dsp {
70 compatible = "ti,omap3-c64";
71 };
72 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]73 };
74
75 /*
76 * XXX: Use a flat representation of the OMAP3 interconnect.
77 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]78 * Since it will not bring real advantage to represent that in DT for
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]79 * the moment, just use a fake OCP bus entry to represent the whole bus
80 * hierarchy.
81 */
Javier Martinez Canillasf515f812016-08-01 12:46:55 -0400[diff] [blame]82 ocp@68000000 {
Tony Lindgrenaa25729c2014-11-05 09:21:23 -0800[diff] [blame]83 compatible = "ti,omap3-l3-smx", "simple-bus";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]84 reg = <0x68000000 0x10000>;
85 interrupts = <9 10>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 ti,hwmods = "l3_main";
90
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]91 l4_core: l4@48000000 {
92 compatible = "ti,omap3-l4-core", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x48000000 0x1000000>;
96
97 scm: scm@2000 {
98 compatible = "ti,omap3-scm", "simple-bus";
99 reg = <0x2000 0x2000>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 0x2000 0x2000>;
103
104 omap3_pmx_core: pinmux@30 {
105 compatible = "ti,omap3-padconf",
106 "pinctrl-single";
107 reg = <0x30 0x238>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 #interrupt-cells = <1>;
111 interrupt-controller;
112 pinctrl-single,register-width = <16>;
113 pinctrl-single,function-mask = <0xff1f>;
114 };
115
116 scm_conf: scm_conf@270 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]117 compatible = "syscon", "simple-bus";
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]118 reg = <0x270 0x330>;
119 #address-cells = <1>;
120 #size-cells = <1>;
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]121 ranges = <0 0x270 0x330>;
122
Javier Martinez Canillas308cfda2016-04-01 16:20:18 -0400[diff] [blame]123 pbias_regulator: pbias_regulator@2b0 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]124 compatible = "ti,pbias-omap3", "ti,pbias-omap";
125 reg = <0x2b0 0x4>;
126 syscon = <&scm_conf>;
127 pbias_mmc_reg: pbias_mmc_omap2430 {
128 regulator-name = "pbias_mmc_omap2430";
129 regulator-min-microvolt = <1800000>;
130 regulator-max-microvolt = <3000000>;
131 };
132 };
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]133
134 scm_clocks: clocks {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 };
138 };
139
140 scm_clockdomains: clockdomains {
141 };
142
143 omap3_pmx_wkup: pinmux@a00 {
144 compatible = "ti,omap3-padconf",
145 "pinctrl-single";
146 reg = <0xa00 0x5c>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <16>;
152 pinctrl-single,function-mask = <0xff1f>;
153 };
154 };
155 };
156
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]157 aes: aes@480c5000 {
158 compatible = "ti,omap3-aes";
159 ti,hwmods = "aes";
160 reg = <0x480c5000 0x50>;
161 interrupts = <0>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]162 dmas = <&sdma 65 &sdma 66>;
163 dma-names = "tx", "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]164 };
165
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]166 prm: prm@48306000 {
167 compatible = "ti,omap3-prm";
168 reg = <0x48306000 0x4000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500[diff] [blame]169 interrupts = <11>;
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]170
171 prm_clocks: clocks {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 };
175
176 prm_clockdomains: clockdomains {
177 };
178 };
179
180 cm: cm@48004000 {
181 compatible = "ti,omap3-cm";
182 reg = <0x48004000 0x4000>;
183
184 cm_clocks: clocks {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188
189 cm_clockdomains: clockdomains {
190 };
191 };
192
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]193 counter32k: counter@48320000 {
194 compatible = "ti,omap-counter32k";
195 reg = <0x48320000 0x20>;
196 ti,hwmods = "counter_32k";
197 };
198
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]199 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]200 compatible = "ti,omap3-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]201 interrupt-controller;
202 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]203 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]204 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]205
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]206 sdma: dma-controller@48056000 {
207 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
208 reg = <0x48056000 0x1000>;
209 interrupts = <12>,
210 <13>,
211 <14>,
212 <15>;
213 #dma-cells = <1>;
Peter Ujfalusi7e8d25d2015-02-20 15:42:03 +0200[diff] [blame]214 dma-channels = <32>;
215 dma-requests = <96>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]216 };
217
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]218 gpio1: gpio@48310000 {
219 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]220 reg = <0x48310000 0x200>;
221 interrupts = <29>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]222 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]223 ti,gpio-always-on;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]227 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]228 };
229
230 gpio2: gpio@49050000 {
231 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]232 reg = <0x49050000 0x200>;
233 interrupts = <30>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]234 ti,hwmods = "gpio2";
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]238 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]239 };
240
241 gpio3: gpio@49052000 {
242 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]243 reg = <0x49052000 0x200>;
244 interrupts = <31>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]245 ti,hwmods = "gpio3";
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]249 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]250 };
251
252 gpio4: gpio@49054000 {
253 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]254 reg = <0x49054000 0x200>;
255 interrupts = <32>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]256 ti,hwmods = "gpio4";
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]260 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]261 };
262
263 gpio5: gpio@49056000 {
264 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]265 reg = <0x49056000 0x200>;
266 interrupts = <33>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]267 ti,hwmods = "gpio5";
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]271 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]272 };
273
274 gpio6: gpio@49058000 {
275 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]276 reg = <0x49058000 0x200>;
277 interrupts = <34>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]278 ti,hwmods = "gpio6";
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]282 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]283 };
284
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]285 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]286 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]287 reg = <0x4806a000 0x2000>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]288 interrupts-extended = <&intc 72>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]289 dmas = <&sdma 49 &sdma 50>;
290 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]291 ti,hwmods = "uart1";
292 clock-frequency = <48000000>;
293 };
294
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]295 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]296 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]297 reg = <0x4806c000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]298 interrupts-extended = <&intc 73>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]299 dmas = <&sdma 51 &sdma 52>;
300 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]301 ti,hwmods = "uart2";
302 clock-frequency = <48000000>;
303 };
304
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]305 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]306 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]307 reg = <0x49020000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]308 interrupts-extended = <&intc 74>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]309 dmas = <&sdma 53 &sdma 54>;
310 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]311 ti,hwmods = "uart3";
312 clock-frequency = <48000000>;
313 };
314
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]315 i2c1: i2c@48070000 {
316 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]317 reg = <0x48070000 0x80>;
318 interrupts = <56>;
319 dmas = <&sdma 27 &sdma 28>;
320 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]321 #address-cells = <1>;
322 #size-cells = <0>;
323 ti,hwmods = "i2c1";
324 };
325
326 i2c2: i2c@48072000 {
327 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]328 reg = <0x48072000 0x80>;
329 interrupts = <57>;
330 dmas = <&sdma 29 &sdma 30>;
331 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]332 #address-cells = <1>;
333 #size-cells = <0>;
334 ti,hwmods = "i2c2";
335 };
336
337 i2c3: i2c@48060000 {
338 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]339 reg = <0x48060000 0x80>;
340 interrupts = <61>;
341 dmas = <&sdma 25 &sdma 26>;
342 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]343 #address-cells = <1>;
344 #size-cells = <0>;
345 ti,hwmods = "i2c3";
346 };
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]347
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]348 mailbox: mailbox@48094000 {
349 compatible = "ti,omap3-mailbox";
350 ti,hwmods = "mailbox";
351 reg = <0x48094000 0x200>;
352 interrupts = <26>;
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]353 #mbox-cells = <1>;
Suman Anna41ffada2014-07-11 16:44:34 -0500[diff] [blame]354 ti,mbox-num-users = <2>;
355 ti,mbox-num-fifos = <2>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]356 mbox_dsp: dsp {
357 ti,mbox-tx = <0 0 0>;
358 ti,mbox-rx = <1 0 0>;
359 };
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]360 };
361
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]362 mcspi1: spi@48098000 {
363 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]364 reg = <0x48098000 0x100>;
365 interrupts = <65>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]366 #address-cells = <1>;
367 #size-cells = <0>;
368 ti,hwmods = "mcspi1";
369 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]370 dmas = <&sdma 35>,
371 <&sdma 36>,
372 <&sdma 37>,
373 <&sdma 38>,
374 <&sdma 39>,
375 <&sdma 40>,
376 <&sdma 41>,
377 <&sdma 42>;
378 dma-names = "tx0", "rx0", "tx1", "rx1",
379 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]380 };
381
382 mcspi2: spi@4809a000 {
383 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]384 reg = <0x4809a000 0x100>;
385 interrupts = <66>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]386 #address-cells = <1>;
387 #size-cells = <0>;
388 ti,hwmods = "mcspi2";
389 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]390 dmas = <&sdma 43>,
391 <&sdma 44>,
392 <&sdma 45>,
393 <&sdma 46>;
394 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]395 };
396
397 mcspi3: spi@480b8000 {
398 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]399 reg = <0x480b8000 0x100>;
400 interrupts = <91>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]401 #address-cells = <1>;
402 #size-cells = <0>;
403 ti,hwmods = "mcspi3";
404 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]405 dmas = <&sdma 15>,
406 <&sdma 16>,
407 <&sdma 23>,
408 <&sdma 24>;
409 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]410 };
411
412 mcspi4: spi@480ba000 {
413 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]414 reg = <0x480ba000 0x100>;
415 interrupts = <48>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]416 #address-cells = <1>;
417 #size-cells = <0>;
418 ti,hwmods = "mcspi4";
419 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]420 dmas = <&sdma 70>, <&sdma 71>;
421 dma-names = "tx0", "rx0";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]422 };
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]423
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]424 hdqw1w: 1w@480b2000 {
425 compatible = "ti,omap3-1w";
426 reg = <0x480b2000 0x1000>;
427 interrupts = <58>;
428 ti,hwmods = "hdq1w";
429 };
430
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]431 mmc1: mmc@4809c000 {
432 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]433 reg = <0x4809c000 0x200>;
434 interrupts = <83>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]435 ti,hwmods = "mmc1";
436 ti,dual-volt;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]437 dmas = <&sdma 61>, <&sdma 62>;
438 dma-names = "tx", "rx";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame]439 pbias-supply = <&pbias_mmc_reg>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]440 };
441
442 mmc2: mmc@480b4000 {
443 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]444 reg = <0x480b4000 0x200>;
445 interrupts = <86>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]446 ti,hwmods = "mmc2";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]447 dmas = <&sdma 47>, <&sdma 48>;
448 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]449 };
450
451 mmc3: mmc@480ad000 {
452 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]453 reg = <0x480ad000 0x200>;
454 interrupts = <94>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]455 ti,hwmods = "mmc3";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]456 dmas = <&sdma 77>, <&sdma 78>;
457 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]458 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]459
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]460 mmu_isp: mmu@480bd400 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]461 #iommu-cells = <0>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]462 compatible = "ti,omap2-iommu";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]463 reg = <0x480bd400 0x80>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]464 interrupts = <24>;
465 ti,hwmods = "mmu_isp";
466 ti,#tlb-entries = <8>;
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]467 };
468
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]469 mmu_iva: mmu@5d000000 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]470 #iommu-cells = <0>;
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]471 compatible = "ti,omap2-iommu";
472 reg = <0x5d000000 0x80>;
473 interrupts = <28>;
474 ti,hwmods = "mmu_iva";
475 status = "disabled";
476 };
477
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]478 wdt2: wdt@48314000 {
479 compatible = "ti,omap3-wdt";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]480 reg = <0x48314000 0x80>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]481 ti,hwmods = "wd_timer2";
482 };
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]483
484 mcbsp1: mcbsp@48074000 {
485 compatible = "ti,omap3-mcbsp";
486 reg = <0x48074000 0xff>;
487 reg-names = "mpu";
488 interrupts = <16>, /* OCP compliant interrupt */
489 <59>, /* TX interrupt */
490 <60>; /* RX interrupt */
491 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]492 ti,buffer-size = <128>;
493 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]494 dmas = <&sdma 31>,
495 <&sdma 32>;
496 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]497 clocks = <&mcbsp1_fck>;
498 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]499 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]500 };
501
502 mcbsp2: mcbsp@49022000 {
503 compatible = "ti,omap3-mcbsp";
504 reg = <0x49022000 0xff>,
505 <0x49028000 0xff>;
506 reg-names = "mpu", "sidetone";
507 interrupts = <17>, /* OCP compliant interrupt */
508 <62>, /* TX interrupt */
509 <63>, /* RX interrupt */
510 <4>; /* Sidetone */
511 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]512 ti,buffer-size = <1280>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]513 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]514 dmas = <&sdma 33>,
515 <&sdma 34>;
516 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]517 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
518 clock-names = "fck", "ick";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]519 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]520 };
521
522 mcbsp3: mcbsp@49024000 {
523 compatible = "ti,omap3-mcbsp";
524 reg = <0x49024000 0xff>,
525 <0x4902a000 0xff>;
526 reg-names = "mpu", "sidetone";
527 interrupts = <22>, /* OCP compliant interrupt */
528 <89>, /* TX interrupt */
529 <90>, /* RX interrupt */
530 <5>; /* Sidetone */
531 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]532 ti,buffer-size = <128>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]533 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]534 dmas = <&sdma 17>,
535 <&sdma 18>;
536 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]537 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
538 clock-names = "fck", "ick";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]539 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]540 };
541
542 mcbsp4: mcbsp@49026000 {
543 compatible = "ti,omap3-mcbsp";
544 reg = <0x49026000 0xff>;
545 reg-names = "mpu";
546 interrupts = <23>, /* OCP compliant interrupt */
547 <54>, /* TX interrupt */
548 <55>; /* RX interrupt */
549 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]550 ti,buffer-size = <128>;
551 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]552 dmas = <&sdma 19>,
553 <&sdma 20>;
554 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]555 clocks = <&mcbsp4_fck>;
556 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]557 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]558 };
559
560 mcbsp5: mcbsp@48096000 {
561 compatible = "ti,omap3-mcbsp";
562 reg = <0x48096000 0xff>;
563 reg-names = "mpu";
564 interrupts = <27>, /* OCP compliant interrupt */
565 <81>, /* TX interrupt */
566 <82>; /* RX interrupt */
567 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]568 ti,buffer-size = <128>;
569 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]570 dmas = <&sdma 21>,
571 <&sdma 22>;
572 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]573 clocks = <&mcbsp5_fck>;
574 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]575 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]576 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]577
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]578 sham: sham@480c3000 {
579 compatible = "ti,omap3-sham";
580 ti,hwmods = "sham";
581 reg = <0x480c3000 0x64>;
582 interrupts = <49>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]583 dmas = <&sdma 69>;
584 dma-names = "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]585 };
586
587 smartreflex_core: smartreflex@480cb000 {
588 compatible = "ti,omap3-smartreflex-core";
589 ti,hwmods = "smartreflex_core";
590 reg = <0x480cb000 0x400>;
591 interrupts = <19>;
592 };
593
594 smartreflex_mpu_iva: smartreflex@480c9000 {
595 compatible = "ti,omap3-smartreflex-iva";
596 ti,hwmods = "smartreflex_mpu_iva";
597 reg = <0x480c9000 0x400>;
598 interrupts = <18>;
599 };
600
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]601 timer1: timer@48318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]602 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]603 reg = <0x48318000 0x400>;
604 interrupts = <37>;
605 ti,hwmods = "timer1";
606 ti,timer-alwon;
607 };
608
609 timer2: timer@49032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]610 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]611 reg = <0x49032000 0x400>;
612 interrupts = <38>;
613 ti,hwmods = "timer2";
614 };
615
616 timer3: timer@49034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]617 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]618 reg = <0x49034000 0x400>;
619 interrupts = <39>;
620 ti,hwmods = "timer3";
621 };
622
623 timer4: timer@49036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]624 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]625 reg = <0x49036000 0x400>;
626 interrupts = <40>;
627 ti,hwmods = "timer4";
628 };
629
630 timer5: timer@49038000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]631 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]632 reg = <0x49038000 0x400>;
633 interrupts = <41>;
634 ti,hwmods = "timer5";
635 ti,timer-dsp;
636 };
637
638 timer6: timer@4903a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]639 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]640 reg = <0x4903a000 0x400>;
641 interrupts = <42>;
642 ti,hwmods = "timer6";
643 ti,timer-dsp;
644 };
645
646 timer7: timer@4903c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]647 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]648 reg = <0x4903c000 0x400>;
649 interrupts = <43>;
650 ti,hwmods = "timer7";
651 ti,timer-dsp;
652 };
653
654 timer8: timer@4903e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]655 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]656 reg = <0x4903e000 0x400>;
657 interrupts = <44>;
658 ti,hwmods = "timer8";
659 ti,timer-pwm;
660 ti,timer-dsp;
661 };
662
663 timer9: timer@49040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]664 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]665 reg = <0x49040000 0x400>;
666 interrupts = <45>;
667 ti,hwmods = "timer9";
668 ti,timer-pwm;
669 };
670
671 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]672 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]673 reg = <0x48086000 0x400>;
674 interrupts = <46>;
675 ti,hwmods = "timer10";
676 ti,timer-pwm;
677 };
678
679 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]680 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]681 reg = <0x48088000 0x400>;
682 interrupts = <47>;
683 ti,hwmods = "timer11";
684 ti,timer-pwm;
685 };
686
687 timer12: timer@48304000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]688 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]689 reg = <0x48304000 0x400>;
690 interrupts = <95>;
691 ti,hwmods = "timer12";
692 ti,timer-alwon;
693 ti,timer-secure;
694 };
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]695
696 usbhstll: usbhstll@48062000 {
697 compatible = "ti,usbhs-tll";
698 reg = <0x48062000 0x1000>;
699 interrupts = <78>;
700 ti,hwmods = "usb_tll_hs";
701 };
702
703 usbhshost: usbhshost@48064000 {
704 compatible = "ti,usbhs-host";
705 reg = <0x48064000 0x400>;
706 ti,hwmods = "usb_host_hs";
707 #address-cells = <1>;
708 #size-cells = <1>;
709 ranges;
710
711 usbhsohci: ohci@48064400 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]712 compatible = "ti,ohci-omap3";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]713 reg = <0x48064400 0x400>;
714 interrupt-parent = <&intc>;
715 interrupts = <76>;
716 };
717
718 usbhsehci: ehci@48064800 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]719 compatible = "ti,ehci-omap";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]720 reg = <0x48064800 0x400>;
721 interrupt-parent = <&intc>;
722 interrupts = <77>;
723 };
724 };
725
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]726 gpmc: gpmc@6e000000 {
727 compatible = "ti,omap3430-gpmc";
728 ti,hwmods = "gpmc";
Javier Martinez Canillas41644e72013-02-27 02:30:51 +0100[diff] [blame]729 reg = <0x6e000000 0x02d0>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]730 interrupts = <20>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]731 dmas = <&sdma 4>;
732 dma-names = "rxtx";
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]733 gpmc,num-cs = <8>;
734 gpmc,num-waitpins = <4>;
735 #address-cells = <2>;
736 #size-cells = <1>;
Roger Quadros44e47162016-02-23 18:37:25 +0200[diff] [blame]737 interrupt-controller;
738 #interrupt-cells = <2>;
Roger Quadros94f56c82016-04-07 13:25:34 +0300[diff] [blame]739 gpio-controller;
740 #gpio-cells = <2>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]741 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]742
743 usb_otg_hs: usb_otg_hs@480ab000 {
744 compatible = "ti,omap3-musb";
745 reg = <0x480ab000 0x1000>;
Tony Lindgren304e71e2013-05-14 20:28:15 -0700[diff] [blame]746 interrupts = <92>, <93>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]747 interrupt-names = "mc", "dma";
748 ti,hwmods = "usb_otg_hs";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]749 multipoint = <1>;
750 num-eps = <16>;
751 ram-bits = <12>;
752 };
Tomi Valkeinenb8a7e422013-03-19 11:38:13 +0200[diff] [blame]753
754 dss: dss@48050000 {
755 compatible = "ti,omap3-dss";
756 reg = <0x48050000 0x200>;
757 status = "disabled";
758 ti,hwmods = "dss_core";
759 clocks = <&dss1_alwon_fck>;
760 clock-names = "fck";
761 #address-cells = <1>;
762 #size-cells = <1>;
763 ranges;
764
765 dispc@48050400 {
766 compatible = "ti,omap3-dispc";
767 reg = <0x48050400 0x400>;
768 interrupts = <25>;
769 ti,hwmods = "dss_dispc";
770 clocks = <&dss1_alwon_fck>;
771 clock-names = "fck";
772 };
773
774 dsi: encoder@4804fc00 {
775 compatible = "ti,omap3-dsi";
776 reg = <0x4804fc00 0x200>,
777 <0x4804fe00 0x40>,
778 <0x4804ff00 0x20>;
779 reg-names = "proto", "phy", "pll";
780 interrupts = <25>;
781 status = "disabled";
782 ti,hwmods = "dss_dsi1";
783 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
784 clock-names = "fck", "sys_clk";
785 };
786
787 rfbi: encoder@48050800 {
788 compatible = "ti,omap3-rfbi";
789 reg = <0x48050800 0x100>;
790 status = "disabled";
791 ti,hwmods = "dss_rfbi";
792 clocks = <&dss1_alwon_fck>, <&dss_ick>;
793 clock-names = "fck", "ick";
794 };
795
796 venc: encoder@48050c00 {
797 compatible = "ti,omap3-venc";
798 reg = <0x48050c00 0x100>;
799 status = "disabled";
800 ti,hwmods = "dss_venc";
801 clocks = <&dss_tv_fck>;
802 clock-names = "fck";
803 };
804 };
Sebastian Reichel782e25a2014-05-10 18:37:49 +0200[diff] [blame]805
806 ssi: ssi-controller@48058000 {
807 compatible = "ti,omap3-ssi";
808 ti,hwmods = "ssi";
809
810 status = "disabled";
811
812 reg = <0x48058000 0x1000>,
813 <0x48059000 0x1000>;
814 reg-names = "sys",
815 "gdd";
816
817 interrupts = <71>;
818 interrupt-names = "gdd_mpu";
819
820 #address-cells = <1>;
821 #size-cells = <1>;
822 ranges;
823
824 ssi_port1: ssi-port@4805a000 {
825 compatible = "ti,omap3-ssi-port";
826
827 reg = <0x4805a000 0x800>,
828 <0x4805a800 0x800>;
829 reg-names = "tx",
830 "rx";
831
832 interrupt-parent = <&intc>;
833 interrupts = <67>,
834 <68>;
835 };
836
837 ssi_port2: ssi-port@4805b000 {
838 compatible = "ti,omap3-ssi-port";
839
840 reg = <0x4805b000 0x800>,
841 <0x4805b800 0x800>;
842 reg-names = "tx",
843 "rx";
844
845 interrupt-parent = <&intc>;
846 interrupts = <69>,
847 <70>;
848 };
849 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]850 };
851};
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]852
853/include/ "omap3xxx-clocks.dtsi"