blob: 9c97f7e651a00a07e4f9cc7f56bb8ec8a9878aa4 [file] [log] [blame]
Srinivas Kandagatla15969b42013-06-25 12:15:23 +01001
2/*
3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#include "st-pincfg.h"
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000011#include <dt-bindings/interrupt-controller/arm-gic.h>
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010012/ {
13
14 aliases {
Lee Jonesdc62bfd2014-05-27 14:53:00 +020015 gpio0 = &pio0;
16 gpio1 = &pio1;
17 gpio2 = &pio2;
18 gpio3 = &pio3;
19 gpio4 = &pio4;
20 gpio5 = &pio40;
21 gpio6 = &pio5;
22 gpio7 = &pio6;
23 gpio8 = &pio7;
24 gpio9 = &pio8;
25 gpio10 = &pio9;
26 gpio11 = &pio10;
27 gpio12 = &pio11;
28 gpio13 = &pio12;
29 gpio14 = &pio30;
30 gpio15 = &pio31;
31 gpio16 = &pio13;
32 gpio17 = &pio14;
33 gpio18 = &pio15;
34 gpio19 = &pio16;
35 gpio20 = &pio17;
36 gpio21 = &pio18;
37 gpio22 = &pio100;
38 gpio23 = &pio101;
39 gpio24 = &pio102;
40 gpio25 = &pio103;
41 gpio26 = &pio104;
42 gpio27 = &pio105;
43 gpio28 = &pio106;
44 gpio29 = &pio107;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010045 };
46
47 soc {
48 pin-controller-sbc {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "st,stih416-sbc-pinctrl";
52 st,syscfg = <&syscfg_sbc>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000053 reg = <0xfe61f080 0x4>;
54 reg-names = "irqmux";
55 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +020056 interrupt-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010057 ranges = <0 0xfe610000 0x6000>;
58
Lee Jonesdc62bfd2014-05-27 14:53:00 +020059 pio0: gpio@fe610000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010060 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +020061 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000062 interrupt-controller;
63 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010064 reg = <0 0x100>;
65 st,bank-name = "PIO0";
66 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +020067 pio1: gpio@fe611000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010068 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +020069 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000070 interrupt-controller;
71 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010072 reg = <0x1000 0x100>;
73 st,bank-name = "PIO1";
74 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +020075 pio2: gpio@fe612000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010076 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +020077 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000078 interrupt-controller;
79 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010080 reg = <0x2000 0x100>;
81 st,bank-name = "PIO2";
82 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +020083 pio3: gpio@fe613000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010084 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +020085 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000086 interrupt-controller;
87 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010088 reg = <0x3000 0x100>;
89 st,bank-name = "PIO3";
90 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +020091 pio4: gpio@fe614000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010092 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +020093 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000094 interrupt-controller;
95 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010096 reg = <0x4000 0x100>;
97 st,bank-name = "PIO4";
98 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +020099 pio40: gpio@fe615000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100100 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200101 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000102 interrupt-controller;
103 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100104 reg = <0x5000 0x100>;
105 st,bank-name = "PIO40";
106 st,retime-pin-mask = <0x7f>;
107 };
108
Srinivas Kandagatlae0637352013-11-11 13:20:44 +0000109 rc{
110 pinctrl_ir: ir0 {
111 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200112 ir = <&pio4 0 ALT2 IN>;
Srinivas Kandagatlae0637352013-11-11 13:20:44 +0000113 };
114 };
115 };
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100116 sbc_serial1 {
117 pinctrl_sbc_serial1: sbc_serial1 {
118 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200119 tx = <&pio2 6 ALT3 OUT>;
120 rx = <&pio2 7 ALT3 IN>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100121 };
122 };
123 };
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100124
Gabriel FERNANDEZ948d8ff2014-04-11 17:07:00 +0200125 keyscan {
126 pinctrl_keyscan: keyscan {
127 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200128 keyin0 = <&pio0 2 ALT2 IN>;
129 keyin1 = <&pio0 3 ALT2 IN>;
130 keyin2 = <&pio0 4 ALT2 IN>;
131 keyin3 = <&pio2 6 ALT2 IN>;
Gabriel FERNANDEZ948d8ff2014-04-11 17:07:00 +0200132
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200133 keyout0 = <&pio1 6 ALT2 OUT>;
134 keyout1 = <&pio1 7 ALT2 OUT>;
135 keyout2 = <&pio0 6 ALT2 OUT>;
136 keyout3 = <&pio2 7 ALT2 OUT>;
Gabriel FERNANDEZ948d8ff2014-04-11 17:07:00 +0200137 };
138 };
139 };
140
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100141 sbc_i2c0 {
142 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
143 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200144 sda = <&pio4 6 ALT1 BIDIR>;
145 scl = <&pio4 5 ALT1 BIDIR>;
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100146 };
147 };
148 };
149
Peter Griffin401a5262014-11-17 17:47:00 +0100150 usb {
151 pinctrl_usb3: usb3 {
152 st,pins {
153 oc-detect = <&pio40 0 ALT1 IN>;
154 pwr-enable = <&pio40 1 ALT1 OUT>;
155 };
156 };
157 };
158
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100159 sbc_i2c1 {
160 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
161 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200162 sda = <&pio3 2 ALT2 BIDIR>;
163 scl = <&pio3 1 ALT2 BIDIR>;
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100164 };
165 };
166 };
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000167
168 gmac1 {
169 pinctrl_mii1: mii1 {
170 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200171 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
172 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
173 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
174 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
175 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
176 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
177 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
178 col = <&pio0 7 ALT1 IN BYPASS 1000>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000179
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200180 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
181 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
182 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
183 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
184 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
185 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
186 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
187 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000188
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200189 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
190 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
191 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
192 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000193 };
194 };
195 pinctrl_rgmii1: rgmii1-0 {
196 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200197 txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
198 txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
199 txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
200 txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
201 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
202 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000203
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200204 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
205 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
206 rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
207 rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
208 rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
209 rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000210
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200211 rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
212 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
213 phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000214
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200215 clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000216 };
217 };
218 };
Lee Jones9723bac2015-05-12 14:51:00 +0200219
220 pwm1 {
221 pinctrl_pwm1_chan0_default: pwm1-0-default {
222 st,pins {
223 pwm-out = <&pio3 0 ALT1 OUT>;
Lee Jones65bb4992016-08-16 11:34:00 +0200224 pwm-capturein = <&pio3 2 ALT1 IN>;
225
Lee Jones9723bac2015-05-12 14:51:00 +0200226 };
227 };
228 pinctrl_pwm1_chan1_default: pwm1-1-default {
229 st,pins {
230 pwm-out = <&pio4 4 ALT1 OUT>;
Lee Jones65bb4992016-08-16 11:34:00 +0200231 pwm-capturein = <&pio4 3 ALT1 IN>;
Lee Jones9723bac2015-05-12 14:51:00 +0200232 };
233 };
234 pinctrl_pwm1_chan2_default: pwm1-2-default {
235 st,pins {
236 pwm-out = <&pio4 6 ALT3 OUT>;
237 };
238 };
239 pinctrl_pwm1_chan3_default: pwm1-3-default {
240 st,pins {
241 pwm-out = <&pio4 7 ALT3 OUT>;
242 };
243 };
244 };
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100245 };
246
247 pin-controller-front {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 compatible = "st,stih416-front-pinctrl";
251 st,syscfg = <&syscfg_front>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000252 reg = <0xfee0f080 0x4>;
253 reg-names = "irqmux";
254 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200255 interrupt-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100256 ranges = <0 0xfee00000 0x10000>;
257
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200258 pio5: gpio@fee00000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100259 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200260 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000261 interrupt-controller;
262 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100263 reg = <0 0x100>;
264 st,bank-name = "PIO5";
265 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200266 pio6: gpio@fee01000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100267 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200268 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000269 interrupt-controller;
270 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100271 reg = <0x1000 0x100>;
272 st,bank-name = "PIO6";
273 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200274 pio7: gpio@fee02000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100275 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200276 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000277 interrupt-controller;
278 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100279 reg = <0x2000 0x100>;
280 st,bank-name = "PIO7";
281 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200282 pio8: gpio@fee03000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100283 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200284 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000285 interrupt-controller;
286 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100287 reg = <0x3000 0x100>;
288 st,bank-name = "PIO8";
289 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200290 pio9: gpio@fee04000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100291 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200292 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000293 interrupt-controller;
294 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100295 reg = <0x4000 0x100>;
296 st,bank-name = "PIO9";
297 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200298 pio10: gpio@fee05000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100299 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200300 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000301 interrupt-controller;
302 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100303 reg = <0x5000 0x100>;
304 st,bank-name = "PIO10";
305 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200306 pio11: gpio@fee06000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100307 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200308 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000309 interrupt-controller;
310 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100311 reg = <0x6000 0x100>;
312 st,bank-name = "PIO11";
313 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200314 pio12: gpio@fee07000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100315 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200316 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000317 interrupt-controller;
318 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100319 reg = <0x7000 0x100>;
320 st,bank-name = "PIO12";
321 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200322 pio30: gpio@fee08000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100323 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200324 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000325 interrupt-controller;
326 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100327 reg = <0x8000 0x100>;
328 st,bank-name = "PIO30";
329 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200330 pio31: gpio@fee09000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100331 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200332 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000333 interrupt-controller;
334 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100335 reg = <0x9000 0x100>;
336 st,bank-name = "PIO31";
337 };
Srinivas Kandagatla334ab912013-07-09 08:26:24 +0100338
Lee Jones9723bac2015-05-12 14:51:00 +0200339 pwm0 {
340 pinctrl_pwm0_chan0_default: pwm0-0-default {
341 st,pins {
342 pwm-out = <&pio9 7 ALT2 OUT>;
Lee Jones65bb4992016-08-16 11:34:00 +0200343 pwm-capturein = <&pio9 6 ALT2 IN>;
Lee Jones9723bac2015-05-12 14:51:00 +0200344 };
345 };
346 };
347
Srinivas Kandagatla334ab912013-07-09 08:26:24 +0100348 serial2-oe {
349 pinctrl_serial2_oe: serial2-1 {
350 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200351 output-enable = <&pio11 3 ALT2 OUT>;
Srinivas Kandagatla334ab912013-07-09 08:26:24 +0100352 };
353 };
354 };
355
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100356 i2c0 {
357 pinctrl_i2c0_default: i2c0-default {
358 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200359 sda = <&pio9 3 ALT1 BIDIR>;
360 scl = <&pio9 2 ALT1 BIDIR>;
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100361 };
362 };
363 };
364
Peter Griffin401a5262014-11-17 17:47:00 +0100365 usb {
366 pinctrl_usb0: usb0 {
367 st,pins {
368 oc-detect = <&pio9 4 ALT1 IN>;
369 pwr-enable = <&pio9 5 ALT1 OUT>;
370 };
371 };
372 };
373
374
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100375 i2c1 {
376 pinctrl_i2c1_default: i2c1-default {
377 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200378 sda = <&pio12 1 ALT1 BIDIR>;
379 scl = <&pio12 0 ALT1 BIDIR>;
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100380 };
381 };
382 };
Lee Jones77f8d9b2014-03-21 11:33:07 +0000383
384 fsm {
385 pinctrl_fsm: fsm {
386 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200387 spi-fsm-clk = <&pio12 2 ALT1 OUT>;
388 spi-fsm-cs = <&pio12 3 ALT1 OUT>;
389 spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
390 spi-fsm-miso = <&pio12 5 ALT1 IN>;
391 spi-fsm-hol = <&pio12 6 ALT1 OUT>;
392 spi-fsm-wp = <&pio12 7 ALT1 OUT>;
Lee Jones77f8d9b2014-03-21 11:33:07 +0000393 };
394 };
395 };
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100396 };
397
398 pin-controller-rear {
399 #address-cells = <1>;
400 #size-cells = <1>;
401 compatible = "st,stih416-rear-pinctrl";
402 st,syscfg = <&syscfg_rear>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000403 reg = <0xfe82f080 0x4>;
404 reg-names = "irqmux";
405 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200406 interrupt-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100407 ranges = <0 0xfe820000 0x6000>;
408
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200409 pio13: gpio@fe820000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100410 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200411 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000412 interrupt-controller;
413 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100414 reg = <0 0x100>;
415 st,bank-name = "PIO13";
416 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200417 pio14: gpio@fe821000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100418 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200419 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000420 interrupt-controller;
421 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100422 reg = <0x1000 0x100>;
423 st,bank-name = "PIO14";
424 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200425 pio15: gpio@fe822000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100426 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200427 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000428 interrupt-controller;
429 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100430 reg = <0x2000 0x100>;
431 st,bank-name = "PIO15";
432 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200433 pio16: gpio@fe823000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100434 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200435 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000436 interrupt-controller;
437 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100438 reg = <0x3000 0x100>;
439 st,bank-name = "PIO16";
440 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200441 pio17: gpio@fe824000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100442 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200443 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000444 interrupt-controller;
445 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100446 reg = <0x4000 0x100>;
447 st,bank-name = "PIO17";
448 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200449 pio18: gpio@fe825000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100450 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200451 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000452 interrupt-controller;
453 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100454 reg = <0x5000 0x100>;
455 st,bank-name = "PIO18";
456 st,retime-pin-mask = <0xf>;
457 };
458
459 serial2 {
460 pinctrl_serial2: serial2-0 {
461 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200462 tx = <&pio17 4 ALT2 OUT>;
463 rx = <&pio17 5 ALT2 IN>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100464 };
465 };
466 };
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000467
468 gmac0 {
469 pinctrl_mii0: mii0 {
470 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200471 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
472 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
473 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
474 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
475 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
476 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000477
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200478 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
479 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
480 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
481 col = <&pio15 3 ALT2 IN BYPASS 1000>;
482 mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
483 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000484
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200485 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
486 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
487 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
488 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
489 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
490 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
491 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
492 phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000493 };
494 };
495
496 pinctrl_gmii0: gmii0 {
497 st,pins {
498 };
499 };
500 pinctrl_rgmii0: rgmii0 {
501 st,pins {
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200502 phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
503 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
504 txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
505 txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
506 txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
507 txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
508 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000509
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200510 mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
511 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000512
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200513 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
514 rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>;
515 rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>;
516 rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>;
517 rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
518 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000519
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200520 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
Srinivas Kandagatlad25ea582014-01-29 16:20:12 +0000521 };
522 };
523 };
Peter Griffin8106d212014-07-09 17:07:00 +0200524
525 mmc0 {
526 pinctrl_mmc0: mmc0 {
527 st,pins {
528 mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
529 data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
530 data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
531 data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
532 data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
533 cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
534 wp = <&pio15 3 ALT4 IN>;
535 data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
536 data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
537 data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
538 data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
539 pwr = <&pio17 1 ALT4 OUT>;
540 cd = <&pio17 2 ALT4 IN>;
541 led = <&pio17 3 ALT4 OUT>;
542 };
543 };
544 };
545 mmc1 {
546 pinctrl_mmc1: mmc1 {
547 st,pins {
548 mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
549 data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
550 data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
551 data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
552 data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
553 cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
554 data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
555 data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
556 data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
557 data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
558 pwr = <&pio16 2 ALT3 OUT>;
559 nreset = <&pio13 6 ALT3 OUT>;
560 };
561 };
562 };
Peter Griffin401a5262014-11-17 17:47:00 +0100563
564 usb {
565 pinctrl_usb1: usb1 {
566 st,pins {
567 oc-detect = <&pio18 0 ALT1 IN>;
568 pwr-enable = <&pio18 1 ALT1 OUT>;
569 };
570 };
571 pinctrl_usb2: usb2 {
572 st,pins {
573 oc-detect = <&pio18 2 ALT1 IN>;
574 pwr-enable = <&pio18 3 ALT1 OUT>;
575 };
576 };
577 };
Lee Jones9723bac2015-05-12 14:51:00 +0200578
579 pwm0 {
580 pinctrl_pwm0_chan1_default: pwm0-1-default {
581 st,pins {
582 pwm-out = <&pio13 2 ALT2 OUT>;
Lee Jones65bb4992016-08-16 11:34:00 +0200583 pwm-capturein = <&pio13 1 ALT2 IN>;
Lee Jones9723bac2015-05-12 14:51:00 +0200584 };
585 };
586 pinctrl_pwm0_chan2_default: pwm0-2-default {
587 st,pins {
588 pwm-out = <&pio15 2 ALT4 OUT>;
589 };
590 };
591 pinctrl_pwm0_chan3_default: pwm0-3-default {
592 st,pins {
593 pwm-out = <&pio17 4 ALT1 OUT>;
594 };
595 };
596 };
597
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100598 };
599
600 pin-controller-fvdp-fe {
601 #address-cells = <1>;
602 #size-cells = <1>;
603 compatible = "st,stih416-fvdp-fe-pinctrl";
604 st,syscfg = <&syscfg_fvdp_fe>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000605 reg = <0xfd6bf080 0x4>;
606 reg-names = "irqmux";
607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200608 interrupt-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100609 ranges = <0 0xfd6b0000 0x3000>;
610
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200611 pio100: gpio@fd6b0000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100612 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200613 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000614 interrupt-controller;
615 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100616 reg = <0 0x100>;
617 st,bank-name = "PIO100";
618 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200619 pio101: gpio@fd6b1000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100620 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200621 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000622 interrupt-controller;
623 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100624 reg = <0x1000 0x100>;
625 st,bank-name = "PIO101";
626 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200627 pio102: gpio@fd6b2000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100628 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200629 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000630 interrupt-controller;
631 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100632 reg = <0x2000 0x100>;
633 st,bank-name = "PIO102";
634 };
635 };
636
637 pin-controller-fvdp-lite {
638 #address-cells = <1>;
639 #size-cells = <1>;
640 compatible = "st,stih416-fvdp-lite-pinctrl";
641 st,syscfg = <&syscfg_fvdp_lite>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000642 reg = <0xfd33f080 0x4>;
643 reg-names = "irqmux";
644 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200645 interrupt-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100646 ranges = <0 0xfd330000 0x5000>;
647
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200648 pio103: gpio@fd330000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100649 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200650 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000651 interrupt-controller;
652 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100653 reg = <0 0x100>;
654 st,bank-name = "PIO103";
655 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200656 pio104: gpio@fd331000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100657 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200658 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000659 interrupt-controller;
660 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100661 reg = <0x1000 0x100>;
662 st,bank-name = "PIO104";
663 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200664 pio105: gpio@fd332000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100665 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200666 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000667 interrupt-controller;
668 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100669 reg = <0x2000 0x100>;
670 st,bank-name = "PIO105";
671 };
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200672 pio106: gpio@fd333000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100673 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200674 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000675 interrupt-controller;
676 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100677 reg = <0x3000 0x100>;
678 st,bank-name = "PIO106";
679 };
680
Lee Jonesdc62bfd2014-05-27 14:53:00 +0200681 pio107: gpio@fd334000 {
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100682 gpio-controller;
Patrice Chotard973b9322016-08-04 11:51:17 +0200683 #gpio-cells = <2>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000684 interrupt-controller;
685 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100686 reg = <0x4000 0x100>;
687 st,bank-name = "PIO107";
688 st,retime-pin-mask = <0xf>;
689 };
690 };
691 };
692};