blob: b4bfa5586c233a48b3aeba14b53c3187e245b753 [file] [log] [blame]
Marc Dietrichcc2afa42011-11-01 10:37:05 +00001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Marc Dietrichcc2afa42011-11-01 10:37:05 +00005
6/ {
7 model = "Toshiba AC100 / Dynabook AZ";
8 compatible = "compal,paz00", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080013 serial0 = &uarta;
14 serial1 = &uartc;
Stephen Warren553c0a22013-12-09 14:43:59 -070015 };
16
Jon Hunterf5bbb322016-02-09 13:51:59 +000017 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060021 memory {
Marc Dietrichcc2afa42011-11-01 10:37:05 +000022 reg = <0x00000000 0x20000000>;
23 };
24
Stephen Warren58ecb232013-11-25 17:53:16 -070025 host1x@50000000 {
Marc Dietrich58168982013-12-21 21:38:13 +010026 dc@54200000 {
27 rgb {
28 status = "okay";
29
30 nvidia,panel = <&panel>;
31 };
32 };
33
Stephen Warren58ecb232013-11-25 17:53:16 -070034 hdmi@54280000 {
Stephen Warren11a3c862013-01-02 14:53:22 -070035 status = "okay";
36
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39
40 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070041 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
42 GPIO_ACTIVE_HIGH>;
Stephen Warren11a3c862013-01-02 14:53:22 -070043 };
44 };
45
Stephen Warren58ecb232013-11-25 17:53:16 -070046 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060047 pinctrl-names = "default";
48 pinctrl-0 = <&state_default>;
49
50 state_default: pinmux {
51 ata {
52 nvidia,pins = "ata", "atc", "atd", "ate",
53 "dap2", "gmb", "gmc", "gmd", "spia",
54 "spib", "spic", "spid", "spie";
55 nvidia,function = "gmi";
56 };
57 atb {
58 nvidia,pins = "atb", "gma", "gme";
59 nvidia,function = "sdio4";
60 };
61 cdev1 {
62 nvidia,pins = "cdev1";
63 nvidia,function = "plla_out";
64 };
65 cdev2 {
66 nvidia,pins = "cdev2";
67 nvidia,function = "pllp_out4";
68 };
69 crtp {
70 nvidia,pins = "crtp";
71 nvidia,function = "crt";
72 };
73 csus {
74 nvidia,pins = "csus";
75 nvidia,function = "pllc_out1";
76 };
77 dap1 {
78 nvidia,pins = "dap1";
79 nvidia,function = "dap1";
80 };
81 dap3 {
82 nvidia,pins = "dap3";
83 nvidia,function = "dap3";
84 };
85 dap4 {
86 nvidia,pins = "dap4";
87 nvidia,function = "dap4";
88 };
89 ddc {
90 nvidia,pins = "ddc";
91 nvidia,function = "i2c2";
92 };
93 dta {
94 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
95 nvidia,function = "rsvd1";
96 };
97 dtf {
98 nvidia,pins = "dtf";
99 nvidia,function = "i2c3";
100 };
101 gpu {
102 nvidia,pins = "gpu", "sdb", "sdd";
103 nvidia,function = "pwm";
104 };
105 gpu7 {
106 nvidia,pins = "gpu7";
107 nvidia,function = "rtck";
108 };
109 gpv {
110 nvidia,pins = "gpv", "slxa", "slxk";
111 nvidia,function = "pcie";
112 };
113 hdint {
114 nvidia,pins = "hdint", "pta";
115 nvidia,function = "hdmi";
116 };
117 i2cp {
118 nvidia,pins = "i2cp";
119 nvidia,function = "i2cp";
120 };
121 irrx {
122 nvidia,pins = "irrx", "irtx";
123 nvidia,function = "uarta";
124 };
125 kbca {
126 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
127 nvidia,function = "kbc";
128 };
129 kbcb {
130 nvidia,pins = "kbcb", "kbcd";
131 nvidia,function = "sdio2";
132 };
133 lcsn {
134 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
135 "ld3", "ld4", "ld5", "ld6", "ld7",
136 "ld8", "ld9", "ld10", "ld11", "ld12",
137 "ld13", "ld14", "ld15", "ld16", "ld17",
138 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
139 "lhs", "lm0", "lm1", "lpp", "lpw0",
140 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
141 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
142 "lvs";
143 nvidia,function = "displaya";
144 };
145 owc {
146 nvidia,pins = "owc";
147 nvidia,function = "owr";
148 };
149 pmc {
150 nvidia,pins = "pmc";
151 nvidia,function = "pwr_on";
152 };
153 rm {
154 nvidia,pins = "rm";
155 nvidia,function = "i2c1";
156 };
157 sdc {
158 nvidia,pins = "sdc";
159 nvidia,function = "twc";
160 };
161 sdio1 {
162 nvidia,pins = "sdio1";
163 nvidia,function = "sdio1";
164 };
165 slxc {
166 nvidia,pins = "slxc", "slxd";
167 nvidia,function = "spi4";
168 };
169 spdi {
170 nvidia,pins = "spdi", "spdo";
171 nvidia,function = "rsvd2";
172 };
173 spif {
174 nvidia,pins = "spif", "uac";
175 nvidia,function = "rsvd4";
176 };
177 spig {
178 nvidia,pins = "spig", "spih";
179 nvidia,function = "spi2_alt";
180 };
181 uaa {
182 nvidia,pins = "uaa", "uab", "uda";
183 nvidia,function = "ulpi";
184 };
185 uad {
186 nvidia,pins = "uad";
187 nvidia,function = "spdif";
188 };
189 uca {
190 nvidia,pins = "uca", "ucb";
191 nvidia,function = "uartc";
192 };
193 conf_ata {
194 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600195 "cdev1", "cdev2", "dap1", "dap2", "dtf",
196 "gma", "gmb", "gmc", "gmd", "gme",
197 "gpu", "gpu7", "gpv", "i2cp", "pta",
198 "rm", "sdio1", "slxk", "spdo", "uac",
199 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
201 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600202 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600203 conf_ck32 {
204 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
205 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600207 };
208 conf_crtp {
209 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
210 "dtc", "dte", "slxa", "slxc", "slxd",
211 "spdi";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530212 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600214 };
215 conf_csus {
216 nvidia,pins = "csus", "spia", "spib", "spid",
217 "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530218 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600220 };
221 conf_ddc {
222 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
223 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
224 "spic", "spig", "uaa", "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530225 nvidia,pull = <TEGRA_PIN_PULL_UP>;
226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600227 };
228 conf_dta {
229 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
230 "spie", "spih", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600233 };
234 conf_hdint {
235 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
236 "ld3", "ld4", "ld5", "ld6", "ld7",
237 "ld8", "ld9", "ld10", "ld11", "ld12",
238 "ld13", "ld14", "ld15", "ld16", "ld17",
239 "ldc", "ldi", "lhs", "lsc0", "lspi",
240 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600242 };
243 conf_lc {
244 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530245 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600246 };
247 conf_lcsn {
248 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
249 "lm0", "lm1", "lpp", "lpw0", "lpw1",
250 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
251 "lvp0", "lvp1", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530252 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600253 };
254 conf_ld17_0 {
255 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
256 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530257 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600258 };
259 };
260 };
261
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600262 i2s@70002800 {
263 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600264 };
265
266 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600267 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600268 };
269
Stephen Warrenc04abb32012-05-11 17:03:26 -0600270 serial@70006200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600271 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600272 };
273
Marc Dietrich58168982013-12-21 21:38:13 +0100274 pwm: pwm@7000a000 {
275 status = "okay";
276 };
277
278 lvds_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600279 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000280 clock-frequency = <400000>;
Leon Romanovsky613e9652012-02-02 22:13:35 +0200281
282 alc5632: alc5632@1e {
283 compatible = "realtek,alc5632";
284 reg = <0x1e>;
285 gpio-controller;
286 #gpio-cells = <2>;
287 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000288 };
289
Stephen Warren11a3c862013-01-02 14:53:22 -0700290 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600291 status = "okay";
Stephen Warren11a3c862013-01-02 14:53:22 -0700292 clock-frequency = <100000>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000293 };
294
Stephen Warren58ecb232013-11-25 17:53:16 -0700295 nvec@7000c500 {
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000296 compatible = "nvidia,nvec";
Stephen Warrenba04c282012-05-11 16:28:59 -0600297 reg = <0x7000c500 0x100>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700298 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600299 #address-cells = <1>;
300 #size-cells = <0>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000301 clock-frequency = <80000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700302 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000303 slave-addr = <138>;
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300304 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
Thierry Reding067cc282014-07-25 12:40:02 -0600305 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
Prashant Gaikwadd409b3a2013-01-11 13:31:23 +0530306 clock-names = "div-clk", "fast-clk";
Stephen Warren3393d422013-11-06 14:01:16 -0700307 resets = <&tegra_car 67>;
308 reset-names = "i2c";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000309 };
310
311 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600312 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000313 clock-frequency = <400000>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100314
Stephen Warren217b8f02012-06-21 14:24:57 -0600315 pmic: tps6586x@34 {
316 compatible = "ti,tps6586x";
317 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700318 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600319
320 #gpio-cells = <2>;
321 gpio-controller;
322
323 sys-supply = <&p5valw_reg>;
324 vin-sm0-supply = <&sys_reg>;
325 vin-sm1-supply = <&sys_reg>;
326 vin-sm2-supply = <&sys_reg>;
327 vinldo01-supply = <&sm2_reg>;
328 vinldo23-supply = <&sm2_reg>;
329 vinldo4-supply = <&sm2_reg>;
330 vinldo678-supply = <&sm2_reg>;
331 vinldo9-supply = <&sm2_reg>;
332
333 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600334 sys_reg: sys {
Stephen Warren217b8f02012-06-21 14:24:57 -0600335 regulator-name = "vdd_sys";
336 regulator-always-on;
337 };
338
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600339 sm0 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600340 regulator-name = "+1.2vs_sm0,vdd_core";
341 regulator-min-microvolt = <1200000>;
342 regulator-max-microvolt = <1200000>;
343 regulator-always-on;
344 };
345
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600346 sm1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600347 regulator-name = "+1.0vs_sm1,vdd_cpu";
348 regulator-min-microvolt = <1000000>;
349 regulator-max-microvolt = <1000000>;
350 regulator-always-on;
351 };
352
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600353 sm2_reg: sm2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600354 regulator-name = "+3.7vs_sm2,vin_ldo*";
355 regulator-min-microvolt = <3700000>;
356 regulator-max-microvolt = <3700000>;
357 regulator-always-on;
358 };
359
360 /* LDO0 is not connected to anything */
361
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600362 ldo1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600363 regulator-name = "+1.1vs_ldo1,avdd_pll*";
364 regulator-min-microvolt = <1100000>;
365 regulator-max-microvolt = <1100000>;
366 regulator-always-on;
367 };
368
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600369 ldo2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600370 regulator-name = "+1.2vs_ldo2,vdd_rtc";
371 regulator-min-microvolt = <1200000>;
372 regulator-max-microvolt = <1200000>;
373 };
374
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600375 ldo3 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600376 regulator-name = "+3.3vs_ldo3,avdd_usb*";
377 regulator-min-microvolt = <3300000>;
378 regulator-max-microvolt = <3300000>;
379 regulator-always-on;
380 };
381
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600382 ldo4 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600383 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 regulator-always-on;
387 };
388
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600389 ldo5 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600390 regulator-name = "+2.85vs_ldo5,vcore_mmc";
391 regulator-min-microvolt = <2850000>;
392 regulator-max-microvolt = <2850000>;
393 regulator-always-on;
394 };
395
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600396 ldo6 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600397 /*
398 * Research indicates this should be
399 * 1.8v; other boards that use this
400 * rail for the same purpose need it
401 * set to 1.8v. The schematic signal
402 * name is incorrect; perhaps copied
403 * from an incorrect NVIDIA reference.
404 */
405 regulator-name = "+2.85vs_ldo6,avdd_vdac";
406 regulator-min-microvolt = <1800000>;
407 regulator-max-microvolt = <1800000>;
408 };
409
Stephen Warren11a3c862013-01-02 14:53:22 -0700410 hdmi_vdd_reg: ldo7 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600411 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
412 regulator-min-microvolt = <3300000>;
413 regulator-max-microvolt = <3300000>;
414 };
415
Stephen Warren11a3c862013-01-02 14:53:22 -0700416 hdmi_pll_reg: ldo8 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600417 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
418 regulator-min-microvolt = <1800000>;
419 regulator-max-microvolt = <1800000>;
420 };
421
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600422 ldo9 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600423 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
424 regulator-min-microvolt = <2850000>;
425 regulator-max-microvolt = <2850000>;
426 regulator-always-on;
427 };
428
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600429 ldo_rtc {
Stephen Warren217b8f02012-06-21 14:24:57 -0600430 regulator-name = "+3.3vs_rtc";
431 regulator-min-microvolt = <3300000>;
432 regulator-max-microvolt = <3300000>;
433 regulator-always-on;
434 };
435 };
436 };
437
Marc Dietrich1266f892012-01-31 19:53:21 +0100438 adt7461@4c {
439 compatible = "adi,adt7461";
440 reg = <0x4c>;
441 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000442 };
443
Stephen Warren58ecb232013-11-25 17:53:16 -0700444 pmc@7000e400 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600445 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800446 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800447 nvidia,cpu-pwr-good-time = <2000>;
448 nvidia,cpu-pwr-off-time = <0>;
449 nvidia,core-pwr-good-time = <3845 3845>;
450 nvidia,core-pwr-off-time = <0>;
451 nvidia,sys-clock-req-active-high;
Stephen Warren217b8f02012-06-21 14:24:57 -0600452 };
453
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600454 usb@c5000000 {
455 status = "okay";
456 };
457
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530458 usb-phy@c5000000 {
459 status = "okay";
460 };
461
Stephen Warrenc04abb32012-05-11 17:03:26 -0600462 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600463 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700464 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
465 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530466 };
467
468 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530469 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700470 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
471 GPIO_ACTIVE_LOW>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000472 };
473
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600474 usb@c5008000 {
475 status = "okay";
476 };
477
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530478 usb-phy@c5008000 {
479 status = "okay";
480 };
481
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000482 sdhci@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600483 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700484 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
485 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
486 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400487 bus-width = <4>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000488 };
489
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000490 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600491 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400492 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600493 non-removable;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000494 };
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100495
Marc Dietrich58168982013-12-21 21:38:13 +0100496 backlight: backlight {
497 compatible = "pwm-backlight";
498
499 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
500 pwms = <&pwm 0 5000000>;
501
502 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
503 default-brightness-level = <10>;
504
505 backlight-boot-off;
506 };
507
Joseph Lo7021d122013-04-03 19:31:27 +0800508 clocks {
509 compatible = "simple-bus";
510 #address-cells = <1>;
511 #size-cells = <0>;
512
Stephen Warren58ecb232013-11-25 17:53:16 -0700513 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800514 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200515 reg = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800516 #clock-cells = <0>;
517 clock-frequency = <32768>;
518 };
519 };
520
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100521 gpio-keys {
522 compatible = "gpio-keys";
523
524 power {
525 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700526 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530527 linux,code = <KEY_POWER>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000528 wakeup-source;
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100529 };
530 };
Marc Dietrich80c94732012-01-28 20:03:08 +0100531
532 gpio-leds {
533 compatible = "gpio-leds";
534
535 wifi {
536 label = "wifi-led";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700537 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Marc Dietrich80c94732012-01-28 20:03:08 +0100538 linux,default-trigger = "rfkill0";
539 };
540 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600541
Marc Dietrich58168982013-12-21 21:38:13 +0100542 panel: panel {
543 compatible = "samsung,ltn101nt05", "simple-panel";
544
545 ddc-i2c-bus = <&lvds_ddc>;
546 power-supply = <&vdd_pnl_reg>;
547 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
548
549 backlight = <&backlight>;
550 };
551
Stephen Warren217b8f02012-06-21 14:24:57 -0600552 regulators {
553 compatible = "simple-bus";
554 #address-cells = <1>;
555 #size-cells = <0>;
556
557 p5valw_reg: regulator@0 {
558 compatible = "regulator-fixed";
559 reg = <0>;
560 regulator-name = "+5valw";
561 regulator-min-microvolt = <5000000>;
562 regulator-max-microvolt = <5000000>;
563 regulator-always-on;
564 };
Marc Dietrich58168982013-12-21 21:38:13 +0100565
566 vdd_pnl_reg: regulator@1 {
567 compatible = "regulator-fixed";
568 reg = <1>;
569 regulator-name = "+3VS,vdd_pnl";
570 regulator-min-microvolt = <3300000>;
571 regulator-max-microvolt = <3300000>;
Marc Dietriche8b6d432016-12-09 10:20:38 +0100572 regulator-boot-on;
Marc Dietrich58168982013-12-21 21:38:13 +0100573 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
574 enable-active-high;
575 };
Stephen Warren217b8f02012-06-21 14:24:57 -0600576 };
577
Stephen Warrenc04abb32012-05-11 17:03:26 -0600578 sound {
579 compatible = "nvidia,tegra-audio-alc5632-paz00",
580 "nvidia,tegra-audio-alc5632";
581
582 nvidia,model = "Compal PAZ00";
583
584 nvidia,audio-routing =
585 "Int Spk", "SPKOUT",
586 "Int Spk", "SPKOUTN",
587 "Headset Mic", "MICBIAS1",
588 "MIC1", "Headset Mic",
589 "Headset Stereophone", "HPR",
590 "Headset Stereophone", "HPL",
591 "DMICDAT", "Digital Mic";
592
593 nvidia,audio-codec = <&alc5632>;
594 nvidia,i2s-controller = <&tegra_i2s1>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700595 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
596 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600597
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300598 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
Thierry Reding067cc282014-07-25 12:40:02 -0600599 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
600 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600601 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600602 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000603};