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Gyungoh Yooa91d2f82012-08-15 10:28:46 -06001/*
2 * Functions to access MAX8907 power management chip.
3 *
4 * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
5 * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __LINUX_MFD_MAX8907_H
13#define __LINUX_MFD_MAX8907_H
14
15#include <linux/mutex.h>
16#include <linux/pm.h>
17
18#define MAX8907_GEN_I2C_ADDR (0x78 >> 1)
19#define MAX8907_ADC_I2C_ADDR (0x8e >> 1)
20#define MAX8907_RTC_I2C_ADDR (0xd0 >> 1)
21
22/* MAX8907 register map */
23#define MAX8907_REG_SYSENSEL 0x00
24#define MAX8907_REG_ON_OFF_IRQ1 0x01
25#define MAX8907_REG_ON_OFF_IRQ1_MASK 0x02
26#define MAX8907_REG_ON_OFF_STAT 0x03
27#define MAX8907_REG_SDCTL1 0x04
28#define MAX8907_REG_SDSEQCNT1 0x05
29#define MAX8907_REG_SDV1 0x06
30#define MAX8907_REG_SDCTL2 0x07
31#define MAX8907_REG_SDSEQCNT2 0x08
32#define MAX8907_REG_SDV2 0x09
33#define MAX8907_REG_SDCTL3 0x0A
34#define MAX8907_REG_SDSEQCNT3 0x0B
35#define MAX8907_REG_SDV3 0x0C
36#define MAX8907_REG_ON_OFF_IRQ2 0x0D
37#define MAX8907_REG_ON_OFF_IRQ2_MASK 0x0E
38#define MAX8907_REG_RESET_CNFG 0x0F
39#define MAX8907_REG_LDOCTL16 0x10
40#define MAX8907_REG_LDOSEQCNT16 0x11
41#define MAX8907_REG_LDO16VOUT 0x12
42#define MAX8907_REG_SDBYSEQCNT 0x13
43#define MAX8907_REG_LDOCTL17 0x14
44#define MAX8907_REG_LDOSEQCNT17 0x15
45#define MAX8907_REG_LDO17VOUT 0x16
46#define MAX8907_REG_LDOCTL1 0x18
47#define MAX8907_REG_LDOSEQCNT1 0x19
48#define MAX8907_REG_LDO1VOUT 0x1A
49#define MAX8907_REG_LDOCTL2 0x1C
50#define MAX8907_REG_LDOSEQCNT2 0x1D
51#define MAX8907_REG_LDO2VOUT 0x1E
52#define MAX8907_REG_LDOCTL3 0x20
53#define MAX8907_REG_LDOSEQCNT3 0x21
54#define MAX8907_REG_LDO3VOUT 0x22
55#define MAX8907_REG_LDOCTL4 0x24
56#define MAX8907_REG_LDOSEQCNT4 0x25
57#define MAX8907_REG_LDO4VOUT 0x26
58#define MAX8907_REG_LDOCTL5 0x28
59#define MAX8907_REG_LDOSEQCNT5 0x29
60#define MAX8907_REG_LDO5VOUT 0x2A
61#define MAX8907_REG_LDOCTL6 0x2C
62#define MAX8907_REG_LDOSEQCNT6 0x2D
63#define MAX8907_REG_LDO6VOUT 0x2E
64#define MAX8907_REG_LDOCTL7 0x30
65#define MAX8907_REG_LDOSEQCNT7 0x31
66#define MAX8907_REG_LDO7VOUT 0x32
67#define MAX8907_REG_LDOCTL8 0x34
68#define MAX8907_REG_LDOSEQCNT8 0x35
69#define MAX8907_REG_LDO8VOUT 0x36
70#define MAX8907_REG_LDOCTL9 0x38
71#define MAX8907_REG_LDOSEQCNT9 0x39
72#define MAX8907_REG_LDO9VOUT 0x3A
73#define MAX8907_REG_LDOCTL10 0x3C
74#define MAX8907_REG_LDOSEQCNT10 0x3D
75#define MAX8907_REG_LDO10VOUT 0x3E
76#define MAX8907_REG_LDOCTL11 0x40
77#define MAX8907_REG_LDOSEQCNT11 0x41
78#define MAX8907_REG_LDO11VOUT 0x42
79#define MAX8907_REG_LDOCTL12 0x44
80#define MAX8907_REG_LDOSEQCNT12 0x45
81#define MAX8907_REG_LDO12VOUT 0x46
82#define MAX8907_REG_LDOCTL13 0x48
83#define MAX8907_REG_LDOSEQCNT13 0x49
84#define MAX8907_REG_LDO13VOUT 0x4A
85#define MAX8907_REG_LDOCTL14 0x4C
86#define MAX8907_REG_LDOSEQCNT14 0x4D
87#define MAX8907_REG_LDO14VOUT 0x4E
88#define MAX8907_REG_LDOCTL15 0x50
89#define MAX8907_REG_LDOSEQCNT15 0x51
90#define MAX8907_REG_LDO15VOUT 0x52
91#define MAX8907_REG_OUT5VEN 0x54
92#define MAX8907_REG_OUT5VSEQ 0x55
93#define MAX8907_REG_OUT33VEN 0x58
94#define MAX8907_REG_OUT33VSEQ 0x59
95#define MAX8907_REG_LDOCTL19 0x5C
96#define MAX8907_REG_LDOSEQCNT19 0x5D
97#define MAX8907_REG_LDO19VOUT 0x5E
98#define MAX8907_REG_LBCNFG 0x60
99#define MAX8907_REG_SEQ1CNFG 0x64
100#define MAX8907_REG_SEQ2CNFG 0x65
101#define MAX8907_REG_SEQ3CNFG 0x66
102#define MAX8907_REG_SEQ4CNFG 0x67
103#define MAX8907_REG_SEQ5CNFG 0x68
104#define MAX8907_REG_SEQ6CNFG 0x69
105#define MAX8907_REG_SEQ7CNFG 0x6A
106#define MAX8907_REG_LDOCTL18 0x72
107#define MAX8907_REG_LDOSEQCNT18 0x73
108#define MAX8907_REG_LDO18VOUT 0x74
109#define MAX8907_REG_BBAT_CNFG 0x78
110#define MAX8907_REG_CHG_CNTL1 0x7C
111#define MAX8907_REG_CHG_CNTL2 0x7D
112#define MAX8907_REG_CHG_IRQ1 0x7E
113#define MAX8907_REG_CHG_IRQ2 0x7F
114#define MAX8907_REG_CHG_IRQ1_MASK 0x80
115#define MAX8907_REG_CHG_IRQ2_MASK 0x81
116#define MAX8907_REG_CHG_STAT 0x82
117#define MAX8907_REG_WLED_MODE_CNTL 0x84
118#define MAX8907_REG_ILED_CNTL 0x84
119#define MAX8907_REG_II1RR 0x8E
120#define MAX8907_REG_II2RR 0x8F
121#define MAX8907_REG_LDOCTL20 0x9C
122#define MAX8907_REG_LDOSEQCNT20 0x9D
123#define MAX8907_REG_LDO20VOUT 0x9E
124
125/* RTC register map */
126#define MAX8907_REG_RTC_SEC 0x00
127#define MAX8907_REG_RTC_MIN 0x01
128#define MAX8907_REG_RTC_HOURS 0x02
129#define MAX8907_REG_RTC_WEEKDAY 0x03
130#define MAX8907_REG_RTC_DATE 0x04
131#define MAX8907_REG_RTC_MONTH 0x05
132#define MAX8907_REG_RTC_YEAR1 0x06
133#define MAX8907_REG_RTC_YEAR2 0x07
134#define MAX8907_REG_ALARM0_SEC 0x08
135#define MAX8907_REG_ALARM0_MIN 0x09
136#define MAX8907_REG_ALARM0_HOURS 0x0A
137#define MAX8907_REG_ALARM0_WEEKDAY 0x0B
138#define MAX8907_REG_ALARM0_DATE 0x0C
139#define MAX8907_REG_ALARM0_MONTH 0x0D
140#define MAX8907_REG_ALARM0_YEAR1 0x0E
141#define MAX8907_REG_ALARM0_YEAR2 0x0F
142#define MAX8907_REG_ALARM1_SEC 0x10
143#define MAX8907_REG_ALARM1_MIN 0x11
144#define MAX8907_REG_ALARM1_HOURS 0x12
145#define MAX8907_REG_ALARM1_WEEKDAY 0x13
146#define MAX8907_REG_ALARM1_DATE 0x14
147#define MAX8907_REG_ALARM1_MONTH 0x15
148#define MAX8907_REG_ALARM1_YEAR1 0x16
149#define MAX8907_REG_ALARM1_YEAR2 0x17
150#define MAX8907_REG_ALARM0_CNTL 0x18
151#define MAX8907_REG_ALARM1_CNTL 0x19
152#define MAX8907_REG_RTC_STATUS 0x1A
153#define MAX8907_REG_RTC_CNTL 0x1B
154#define MAX8907_REG_RTC_IRQ 0x1C
155#define MAX8907_REG_RTC_IRQ_MASK 0x1D
156#define MAX8907_REG_MPL_CNTL 0x1E
157
158/* ADC and Touch Screen Controller register map */
159#define MAX8907_CTL 0
160#define MAX8907_SEQCNT 1
161#define MAX8907_VOUT 2
162
163/* mask bit fields */
164#define MAX8907_MASK_LDO_SEQ 0x1C
165#define MAX8907_MASK_LDO_EN 0x01
166#define MAX8907_MASK_VBBATTCV 0x03
167#define MAX8907_MASK_OUT5V_VINEN 0x10
168#define MAX8907_MASK_OUT5V_ENSRC 0x0E
169#define MAX8907_MASK_OUT5V_EN 0x01
Stephen Warren9582fdc2012-09-18 16:51:19 -0600170#define MAX8907_MASK_POWER_OFF 0x40
Gyungoh Yooa91d2f82012-08-15 10:28:46 -0600171
172/* Regulator IDs */
173#define MAX8907_MBATT 0
174#define MAX8907_SD1 1
175#define MAX8907_SD2 2
176#define MAX8907_SD3 3
177#define MAX8907_LDO1 4
178#define MAX8907_LDO2 5
179#define MAX8907_LDO3 6
180#define MAX8907_LDO4 7
181#define MAX8907_LDO5 8
182#define MAX8907_LDO6 9
183#define MAX8907_LDO7 10
184#define MAX8907_LDO8 11
185#define MAX8907_LDO9 12
186#define MAX8907_LDO10 13
187#define MAX8907_LDO11 14
188#define MAX8907_LDO12 15
189#define MAX8907_LDO13 16
190#define MAX8907_LDO14 17
191#define MAX8907_LDO15 18
192#define MAX8907_LDO16 19
193#define MAX8907_LDO17 20
194#define MAX8907_LDO18 21
195#define MAX8907_LDO19 22
196#define MAX8907_LDO20 23
197#define MAX8907_OUT5V 24
198#define MAX8907_OUT33V 25
199#define MAX8907_BBAT 26
200#define MAX8907_SDBY 27
201#define MAX8907_VRTC 28
202#define MAX8907_NUM_REGULATORS (MAX8907_VRTC + 1)
203
204/* IRQ definitions */
205enum {
206 MAX8907_IRQ_VCHG_DC_OVP = 0,
207 MAX8907_IRQ_VCHG_DC_F,
208 MAX8907_IRQ_VCHG_DC_R,
209 MAX8907_IRQ_VCHG_THM_OK_R,
210 MAX8907_IRQ_VCHG_THM_OK_F,
211 MAX8907_IRQ_VCHG_MBATTLOW_F,
212 MAX8907_IRQ_VCHG_MBATTLOW_R,
213 MAX8907_IRQ_VCHG_RST,
214 MAX8907_IRQ_VCHG_DONE,
215 MAX8907_IRQ_VCHG_TOPOFF,
216 MAX8907_IRQ_VCHG_TMR_FAULT,
217
218 MAX8907_IRQ_GPM_RSTIN = 0,
219 MAX8907_IRQ_GPM_MPL,
220 MAX8907_IRQ_GPM_SW_3SEC,
221 MAX8907_IRQ_GPM_EXTON_F,
222 MAX8907_IRQ_GPM_EXTON_R,
223 MAX8907_IRQ_GPM_SW_1SEC,
224 MAX8907_IRQ_GPM_SW_F,
225 MAX8907_IRQ_GPM_SW_R,
226 MAX8907_IRQ_GPM_SYSCKEN_F,
227 MAX8907_IRQ_GPM_SYSCKEN_R,
228
229 MAX8907_IRQ_RTC_ALARM1 = 0,
230 MAX8907_IRQ_RTC_ALARM0,
231};
232
233struct max8907_platform_data {
234 struct regulator_init_data *init_data[MAX8907_NUM_REGULATORS];
Stephen Warren9582fdc2012-09-18 16:51:19 -0600235 bool pm_off;
Gyungoh Yooa91d2f82012-08-15 10:28:46 -0600236};
237
238struct regmap_irq_chips_data;
239
240struct max8907 {
241 struct device *dev;
242 struct mutex irq_lock;
243 struct i2c_client *i2c_gen;
244 struct i2c_client *i2c_rtc;
245 struct regmap *regmap_gen;
246 struct regmap *regmap_rtc;
247 struct regmap_irq_chip_data *irqc_chg;
248 struct regmap_irq_chip_data *irqc_on_off;
249 struct regmap_irq_chip_data *irqc_rtc;
250};
251
252#endif