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gerrit-public.fairphone.software / kernel / msm-4.9 / 30bc9b53878a9921b02e3b5bc4283ac1c6de102a / . / include / linux / platform_data / spi-s3c64xx.h
blob: 8447f634c7f5a142982b1c6fd0121b4219d91d72 [file] [log] [blame]
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]1/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S3C64XX_PLAT_SPI_H
12#define __S3C64XX_PLAT_SPI_H
13
Arnd Bergmann78843722013-04-11 22:42:03 +0200[diff] [blame]14#include <linux/dmaengine.h>
15
Mark Brown5b0b34e2011-12-29 18:01:08 +0900[diff] [blame]16struct platform_device;
17
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]18/**
19 * struct s3c64xx_spi_csinfo - ChipSelect description
20 * @fb_delay: Slave specific feedback delay.
21 * Refer to FB_CLK_SEL register definition in SPI chapter.
22 * @line: Custom 'identity' of the CS line.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]23 *
24 * This is per SPI-Slave Chipselect information.
25 * Allocate and initialize one in machine init code and make the
26 * spi_board_info.controller_data point to it.
27 */
28struct s3c64xx_spi_csinfo {
29 u8 fb_delay;
30 unsigned line;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]31};
32
33/**
34 * struct s3c64xx_spi_info - SPI Controller defining structure
35 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]36 * @num_cs: Number of CS this controller emulates.
37 * @cfg_gpio: Configure pins for this SPI controller.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]38 */
39struct s3c64xx_spi_info {
40 int src_clk_nr;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]41 int num_cs;
Thomas Abraham868dee92012-07-13 07:15:14 +0900[diff] [blame]42 int (*cfg_gpio)(void);
Arnd Bergmann78843722013-04-11 22:42:03 +0200[diff] [blame]43 dma_filter_fn filter;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]44};
45
46/**
Padmavathi Venna875a5932011-12-23 10:14:31 +0900[diff] [blame]47 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]48 * initialization code.
Thomas Abraham4d0efdd2012-07-13 07:15:14 +0900[diff] [blame]49 * @cfg_gpio: Pointer to gpio setup function.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]50 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
51 * @num_cs: Number of elements in the 'cs' array.
52 *
53 * Call this from machine init code for each SPI Controller that
54 * has some chips attached to it.
55 */
Thomas Abraham4d0efdd2012-07-13 07:15:14 +0900[diff] [blame]56extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
57 int num_cs);
58extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
59 int num_cs);
60extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
61 int num_cs);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]62
63/* defined by architecture to configure gpio */
Thomas Abraham868dee92012-07-13 07:15:14 +0900[diff] [blame]64extern int s3c64xx_spi0_cfg_gpio(void);
65extern int s3c64xx_spi1_cfg_gpio(void);
66extern int s3c64xx_spi2_cfg_gpio(void);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]67
68extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
69extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
Padmavathi Venna323d7712011-12-23 10:14:45 +0900[diff] [blame]70extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]71#endif /* __S3C64XX_PLAT_SPI_H */