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gerrit-public.fairphone.software / kernel / msm-4.9 / 30e840346c516ad4e36f710fa485933ccc7afa66 / . / drivers / net / wireless / rt2x00 / rt2800.h
blob: 74fb5253ee23f8426debe750f03e3f0921d5dcef [file] [log] [blame]
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800
23 Abstract: Data structures and registers for the rt2800 modules.
24 Supported chipsets: RT2800E, RT2800ED & RT2800U.
25 */
26
27#ifndef RT2800_H
28#define RT2800_H
29
30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * Chipset version.
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Default offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * USB registers.
87 */
88
89/*
90 * INT_SOURCE_CSR: Interrupt source register.
91 * Write one to clear corresponding bit.
92 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
93 */
94#define INT_SOURCE_CSR 0x0200
95#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
96#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
97#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
98#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
99#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
100#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
101#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
102#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
103#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
104#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
105#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
106#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
107#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
108#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
109#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
110#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
111#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
112#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
113
114/*
115 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
116 */
117#define INT_MASK_CSR 0x0204
118#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
119#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
120#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
121#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
122#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
123#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
124#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
125#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
126#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
127#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
128#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
129#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
130#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
131#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
132#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
133#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
134#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
135#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
136
137/*
138 * WPDMA_GLO_CFG
139 */
140#define WPDMA_GLO_CFG 0x0208
141#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
142#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
143#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
144#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
145#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
146#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
147#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
148#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
149#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
150
151/*
152 * WPDMA_RST_IDX
153 */
154#define WPDMA_RST_IDX 0x020c
155#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
156#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
157#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
158#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
159#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
160#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
161#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
162
163/*
164 * DELAY_INT_CFG
165 */
166#define DELAY_INT_CFG 0x0210
167#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
168#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
169#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
170#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
171#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
172#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
173
174/*
175 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
176 * AIFSN0: AC_BE
177 * AIFSN1: AC_BK
Bartlomiej Zolnierkiewicza4385212009-11-04 18:36:02 +0100[diff] [blame]178 * AIFSN2: AC_VI
179 * AIFSN3: AC_VO
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]180 */
181#define WMM_AIFSN_CFG 0x0214
182#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
183#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
184#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
185#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
186
187/*
188 * WMM_CWMIN_CSR: CWmin for each EDCA AC
189 * CWMIN0: AC_BE
190 * CWMIN1: AC_BK
Bartlomiej Zolnierkiewicza4385212009-11-04 18:36:02 +0100[diff] [blame]191 * CWMIN2: AC_VI
192 * CWMIN3: AC_VO
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]193 */
194#define WMM_CWMIN_CFG 0x0218
195#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
196#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
197#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
198#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
199
200/*
201 * WMM_CWMAX_CSR: CWmax for each EDCA AC
202 * CWMAX0: AC_BE
203 * CWMAX1: AC_BK
Bartlomiej Zolnierkiewicza4385212009-11-04 18:36:02 +0100[diff] [blame]204 * CWMAX2: AC_VI
205 * CWMAX3: AC_VO
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]206 */
207#define WMM_CWMAX_CFG 0x021c
208#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
209#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
210#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
211#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
212
213/*
214 * AC_TXOP0: AC_BK/AC_BE TXOP register
215 * AC0TXOP: AC_BK in unit of 32us
216 * AC1TXOP: AC_BE in unit of 32us
217 */
218#define WMM_TXOP0_CFG 0x0220
219#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
220#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
221
222/*
223 * AC_TXOP1: AC_VO/AC_VI TXOP register
224 * AC2TXOP: AC_VI in unit of 32us
225 * AC3TXOP: AC_VO in unit of 32us
226 */
227#define WMM_TXOP1_CFG 0x0224
228#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
229#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
230
231/*
232 * GPIO_CTRL_CFG:
233 */
234#define GPIO_CTRL_CFG 0x0228
235#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
236#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
237#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
238#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
239#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
240#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
241#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
242#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
243#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
244
245/*
246 * MCU_CMD_CFG
247 */
248#define MCU_CMD_CFG 0x022c
249
250/*
251 * AC_BK register offsets
252 */
253#define TX_BASE_PTR0 0x0230
254#define TX_MAX_CNT0 0x0234
255#define TX_CTX_IDX0 0x0238
256#define TX_DTX_IDX0 0x023c
257
258/*
259 * AC_BE register offsets
260 */
261#define TX_BASE_PTR1 0x0240
262#define TX_MAX_CNT1 0x0244
263#define TX_CTX_IDX1 0x0248
264#define TX_DTX_IDX1 0x024c
265
266/*
267 * AC_VI register offsets
268 */
269#define TX_BASE_PTR2 0x0250
270#define TX_MAX_CNT2 0x0254
271#define TX_CTX_IDX2 0x0258
272#define TX_DTX_IDX2 0x025c
273
274/*
275 * AC_VO register offsets
276 */
277#define TX_BASE_PTR3 0x0260
278#define TX_MAX_CNT3 0x0264
279#define TX_CTX_IDX3 0x0268
280#define TX_DTX_IDX3 0x026c
281
282/*
283 * HCCA register offsets
284 */
285#define TX_BASE_PTR4 0x0270
286#define TX_MAX_CNT4 0x0274
287#define TX_CTX_IDX4 0x0278
288#define TX_DTX_IDX4 0x027c
289
290/*
291 * MGMT register offsets
292 */
293#define TX_BASE_PTR5 0x0280
294#define TX_MAX_CNT5 0x0284
295#define TX_CTX_IDX5 0x0288
296#define TX_DTX_IDX5 0x028c
297
298/*
299 * RX register offsets
300 */
301#define RX_BASE_PTR 0x0290
302#define RX_MAX_CNT 0x0294
303#define RX_CRX_IDX 0x0298
304#define RX_DRX_IDX 0x029c
305
306/*
307 * PBF_SYS_CTRL
308 * HOST_RAM_WRITE: enable Host program ram write selection
309 */
310#define PBF_SYS_CTRL 0x0400
311#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
312#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
313
314/*
315 * HOST-MCU shared memory
316 */
317#define HOST_CMD_CSR 0x0404
318#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
319
320/*
321 * PBF registers
322 * Most are for debug. Driver doesn't touch PBF register.
323 */
324#define PBF_CFG 0x0408
325#define PBF_MAX_PCNT 0x040c
326#define PBF_CTRL 0x0410
327#define PBF_INT_STA 0x0414
328#define PBF_INT_ENA 0x0418
329
330/*
331 * BCN_OFFSET0:
332 */
333#define BCN_OFFSET0 0x042c
334#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
335#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
336#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
337#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
338
339/*
340 * BCN_OFFSET1:
341 */
342#define BCN_OFFSET1 0x0430
343#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
344#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
345#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
346#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
347
348/*
349 * PBF registers
350 * Most are for debug. Driver doesn't touch PBF register.
351 */
352#define TXRXQ_PCNT 0x0438
353#define PBF_DBG 0x043c
354
355/*
356 * RF registers
357 */
358#define RF_CSR_CFG 0x0500
359#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
360#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
361#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
362#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
363
364/*
Bartlomiej Zolnierkiewicz30e84032009-11-08 14:39:48 +0100[diff] [blame^]365 * EFUSE_CSR: RT30x0 EEPROM
366 */
367#define EFUSE_CTRL 0x0580
368#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
369#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
370#define EFUSE_CTRL_KICK FIELD32(0x40000000)
371#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
372
373/*
374 * EFUSE_DATA0
375 */
376#define EFUSE_DATA0 0x0590
377
378/*
379 * EFUSE_DATA1
380 */
381#define EFUSE_DATA1 0x0594
382
383/*
384 * EFUSE_DATA2
385 */
386#define EFUSE_DATA2 0x0598
387
388/*
389 * EFUSE_DATA3
390 */
391#define EFUSE_DATA3 0x059c
392
393/*
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]394 * MAC Control/Status Registers(CSR).
395 * Some values are set in TU, whereas 1 TU == 1024 us.
396 */
397
398/*
399 * MAC_CSR0: ASIC revision number.
400 * ASIC_REV: 0
401 * ASIC_VER: 2860 or 2870
402 */
403#define MAC_CSR0 0x1000
404#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
405#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
406
407/*
408 * MAC_SYS_CTRL:
409 */
410#define MAC_SYS_CTRL 0x1004
411#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
412#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
413#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
414#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
415#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
416#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
417#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
418#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
419
420/*
421 * MAC_ADDR_DW0: STA MAC register 0
422 */
423#define MAC_ADDR_DW0 0x1008
424#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
425#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
426#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
427#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
428
429/*
430 * MAC_ADDR_DW1: STA MAC register 1
431 * UNICAST_TO_ME_MASK:
432 * Used to mask off bits from byte 5 of the MAC address
433 * to determine the UNICAST_TO_ME bit for RX frames.
434 * The full mask is complemented by BSS_ID_MASK:
435 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
436 */
437#define MAC_ADDR_DW1 0x100c
438#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
439#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
440#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
441
442/*
443 * MAC_BSSID_DW0: BSSID register 0
444 */
445#define MAC_BSSID_DW0 0x1010
446#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
447#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
448#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
449#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
450
451/*
452 * MAC_BSSID_DW1: BSSID register 1
453 * BSS_ID_MASK:
454 * 0: 1-BSSID mode (BSS index = 0)
455 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
456 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
457 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
458 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
459 * BSSID. This will make sure that those bits will be ignored
460 * when determining the MY_BSS of RX frames.
461 */
462#define MAC_BSSID_DW1 0x1014
463#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
464#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
465#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
466#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
467
468/*
469 * MAX_LEN_CFG: Maximum frame length register.
470 * MAX_MPDU: rt2860b max 16k bytes
471 * MAX_PSDU: Maximum PSDU length
472 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
473 */
474#define MAX_LEN_CFG 0x1018
475#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
476#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
477#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
478#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
479
480/*
481 * BBP_CSR_CFG: BBP serial control register
482 * VALUE: Register value to program into BBP
483 * REG_NUM: Selected BBP register
484 * READ_CONTROL: 0 write BBP, 1 read BBP
485 * BUSY: ASIC is busy executing BBP commands
486 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
487 * BBP_RW_MODE: 0 serial, 1 paralell
488 */
489#define BBP_CSR_CFG 0x101c
490#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
491#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
492#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
493#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
494#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
495#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
496
497/*
498 * RF_CSR_CFG0: RF control register
499 * REGID_AND_VALUE: Register value to program into RF
500 * BITWIDTH: Selected RF register
501 * STANDBYMODE: 0 high when standby, 1 low when standby
502 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
503 * BUSY: ASIC is busy executing RF commands
504 */
505#define RF_CSR_CFG0 0x1020
506#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
507#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
508#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
509#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
510#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
511#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
512
513/*
514 * RF_CSR_CFG1: RF control register
515 * REGID_AND_VALUE: Register value to program into RF
516 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
517 * 0: 3 system clock cycle (37.5usec)
518 * 1: 5 system clock cycle (62.5usec)
519 */
520#define RF_CSR_CFG1 0x1024
521#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
522#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
523
524/*
525 * RF_CSR_CFG2: RF control register
526 * VALUE: Register value to program into RF
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]527 */
528#define RF_CSR_CFG2 0x1028
529#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
530
531/*
532 * LED_CFG: LED control
533 * color LED's:
534 * 0: off
535 * 1: blinking upon TX2
536 * 2: periodic slow blinking
537 * 3: always on
538 * LED polarity:
539 * 0: active low
540 * 1: active high
541 */
542#define LED_CFG 0x102c
543#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
544#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
545#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
546#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
547#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
548#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
549#define LED_CFG_LED_POLAR FIELD32(0x40000000)
550
551/*
552 * XIFS_TIME_CFG: MAC timing
553 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
554 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
555 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
556 * when MAC doesn't reference BBP signal BBRXEND
557 * EIFS: unit 1us
558 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
559 *
560 */
561#define XIFS_TIME_CFG 0x1100
562#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
563#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
564#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
565#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
566#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
567
568/*
569 * BKOFF_SLOT_CFG:
570 */
571#define BKOFF_SLOT_CFG 0x1104
572#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
573#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
574
575/*
576 * NAV_TIME_CFG:
577 */
578#define NAV_TIME_CFG 0x1108
579#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
580#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
581#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
582#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
583
584/*
585 * CH_TIME_CFG: count as channel busy
586 */
587#define CH_TIME_CFG 0x110c
588
589/*
590 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
591 */
592#define PBF_LIFE_TIMER 0x1110
593
594/*
595 * BCN_TIME_CFG:
596 * BEACON_INTERVAL: in unit of 1/16 TU
597 * TSF_TICKING: Enable TSF auto counting
598 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
599 * BEACON_GEN: Enable beacon generator
600 */
601#define BCN_TIME_CFG 0x1114
602#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
603#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
604#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
605#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
606#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
607#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
608
609/*
610 * TBTT_SYNC_CFG:
611 */
612#define TBTT_SYNC_CFG 0x1118
613
614/*
615 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
616 */
617#define TSF_TIMER_DW0 0x111c
618#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
619
620/*
621 * TSF_TIMER_DW1: Local msb TSF timer, read-only
622 */
623#define TSF_TIMER_DW1 0x1120
624#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
625
626/*
627 * TBTT_TIMER: TImer remains till next TBTT, read-only
628 */
629#define TBTT_TIMER 0x1124
630
631/*
632 * INT_TIMER_CFG:
633 */
634#define INT_TIMER_CFG 0x1128
635
636/*
637 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
638 */
639#define INT_TIMER_EN 0x112c
640
641/*
642 * CH_IDLE_STA: channel idle time
643 */
644#define CH_IDLE_STA 0x1130
645
646/*
647 * CH_BUSY_STA: channel busy time
648 */
649#define CH_BUSY_STA 0x1134
650
651/*
652 * MAC_STATUS_CFG:
653 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
654 * if 1 or higher one of the 2 registers is busy.
655 */
656#define MAC_STATUS_CFG 0x1200
657#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
658
659/*
660 * PWR_PIN_CFG:
661 */
662#define PWR_PIN_CFG 0x1204
663
664/*
665 * AUTOWAKEUP_CFG: Manual power control / status register
666 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
667 * AUTOWAKE: 0:sleep, 1:awake
668 */
669#define AUTOWAKEUP_CFG 0x1208
670#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
671#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
672#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
673
674/*
675 * EDCA_AC0_CFG:
676 */
677#define EDCA_AC0_CFG 0x1300
678#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
679#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
680#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
681#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
682
683/*
684 * EDCA_AC1_CFG:
685 */
686#define EDCA_AC1_CFG 0x1304
687#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
688#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
689#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
690#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
691
692/*
693 * EDCA_AC2_CFG:
694 */
695#define EDCA_AC2_CFG 0x1308
696#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
697#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
698#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
699#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
700
701/*
702 * EDCA_AC3_CFG:
703 */
704#define EDCA_AC3_CFG 0x130c
705#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
706#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
707#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
708#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
709
710/*
711 * EDCA_TID_AC_MAP:
712 */
713#define EDCA_TID_AC_MAP 0x1310
714
715/*
716 * TX_PWR_CFG_0:
717 */
718#define TX_PWR_CFG_0 0x1314
719#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
720#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
721#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
722#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
723#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
724#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
725#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
726#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
727
728/*
729 * TX_PWR_CFG_1:
730 */
731#define TX_PWR_CFG_1 0x1318
732#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
733#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
734#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
735#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
736#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
737#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
738#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
739#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
740
741/*
742 * TX_PWR_CFG_2:
743 */
744#define TX_PWR_CFG_2 0x131c
745#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
746#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
747#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
748#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
749#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
750#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
751#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
752#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
753
754/*
755 * TX_PWR_CFG_3:
756 */
757#define TX_PWR_CFG_3 0x1320
758#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
759#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
760#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
761#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
762#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
763#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
764#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
765#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
766
767/*
768 * TX_PWR_CFG_4:
769 */
770#define TX_PWR_CFG_4 0x1324
771#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
772#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
773#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
774#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
775
776/*
777 * TX_PIN_CFG:
778 */
779#define TX_PIN_CFG 0x1328
780#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
781#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
782#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
783#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
784#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
785#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
786#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
787#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
788#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
789#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
790#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
791#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
792#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
793#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
794#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
795#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
796#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
797#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
798#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
799#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
800
801/*
802 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
803 */
804#define TX_BAND_CFG 0x132c
805#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
806#define TX_BAND_CFG_A FIELD32(0x00000002)
807#define TX_BAND_CFG_BG FIELD32(0x00000004)
808
809/*
810 * TX_SW_CFG0:
811 */
812#define TX_SW_CFG0 0x1330
813
814/*
815 * TX_SW_CFG1:
816 */
817#define TX_SW_CFG1 0x1334
818
819/*
820 * TX_SW_CFG2:
821 */
822#define TX_SW_CFG2 0x1338
823
824/*
825 * TXOP_THRES_CFG:
826 */
827#define TXOP_THRES_CFG 0x133c
828
829/*
830 * TXOP_CTRL_CFG:
831 */
832#define TXOP_CTRL_CFG 0x1340
833
834/*
835 * TX_RTS_CFG:
836 * RTS_THRES: unit:byte
837 * RTS_FBK_EN: enable rts rate fallback
838 */
839#define TX_RTS_CFG 0x1344
840#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
841#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
842#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
843
844/*
845 * TX_TIMEOUT_CFG:
846 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
847 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
848 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
849 * it is recommended that:
850 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
851 */
852#define TX_TIMEOUT_CFG 0x1348
853#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
854#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
855#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
856
857/*
858 * TX_RTY_CFG:
859 * SHORT_RTY_LIMIT: short retry limit
860 * LONG_RTY_LIMIT: long retry limit
861 * LONG_RTY_THRE: Long retry threshoold
862 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
863 * 0:expired by retry limit, 1: expired by mpdu life timer
864 * AGG_RTY_MODE: Aggregate MPDU retry mode
865 * 0:expired by retry limit, 1: expired by mpdu life timer
866 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
867 */
868#define TX_RTY_CFG 0x134c
869#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
870#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
871#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
872#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
873#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
874#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
875
876/*
877 * TX_LINK_CFG:
878 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
879 * MFB_ENABLE: TX apply remote MFB 1:enable
880 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
881 * 0: not apply remote remote unsolicit (MFS=7)
882 * TX_MRQ_EN: MCS request TX enable
883 * TX_RDG_EN: RDG TX enable
884 * TX_CF_ACK_EN: Piggyback CF-ACK enable
885 * REMOTE_MFB: remote MCS feedback
886 * REMOTE_MFS: remote MCS feedback sequence number
887 */
888#define TX_LINK_CFG 0x1350
889#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
890#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
891#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
892#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
893#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
894#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
895#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
896#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
897
898/*
899 * HT_FBK_CFG0:
900 */
901#define HT_FBK_CFG0 0x1354
902#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
903#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
904#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
905#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
906#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
907#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
908#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
909#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
910
911/*
912 * HT_FBK_CFG1:
913 */
914#define HT_FBK_CFG1 0x1358
915#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
916#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
917#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
918#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
919#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
920#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
921#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
922#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
923
924/*
925 * LG_FBK_CFG0:
926 */
927#define LG_FBK_CFG0 0x135c
928#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
929#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
930#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
931#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
932#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
933#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
934#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
935#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
936
937/*
938 * LG_FBK_CFG1:
939 */
940#define LG_FBK_CFG1 0x1360
941#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
942#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
943#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
944#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
945
946/*
947 * CCK_PROT_CFG: CCK Protection
948 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
949 * PROTECT_CTRL: Protection control frame type for CCK TX
950 * 0:none, 1:RTS/CTS, 2:CTS-to-self
951 * PROTECT_NAV: TXOP protection type for CCK TX
952 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
953 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
954 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
955 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
956 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
957 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
958 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
959 * RTS_TH_EN: RTS threshold enable on CCK TX
960 */
961#define CCK_PROT_CFG 0x1364
962#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
963#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
964#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
965#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
966#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
967#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
968#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
969#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
970#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
971#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
972
973/*
974 * OFDM_PROT_CFG: OFDM Protection
975 */
976#define OFDM_PROT_CFG 0x1368
977#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
978#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
979#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
980#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
981#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
982#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
983#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
984#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
985#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
986#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
987
988/*
989 * MM20_PROT_CFG: MM20 Protection
990 */
991#define MM20_PROT_CFG 0x136c
992#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
993#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
994#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
995#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
996#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
997#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
998#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
999#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1000#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1001#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1002
1003/*
1004 * MM40_PROT_CFG: MM40 Protection
1005 */
1006#define MM40_PROT_CFG 0x1370
1007#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1008#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1009#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1010#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1011#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1012#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1013#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1014#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1015#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1016#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1017
1018/*
1019 * GF20_PROT_CFG: GF20 Protection
1020 */
1021#define GF20_PROT_CFG 0x1374
1022#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1023#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1024#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1025#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1026#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1027#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1028#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1029#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1030#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1031#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1032
1033/*
1034 * GF40_PROT_CFG: GF40 Protection
1035 */
1036#define GF40_PROT_CFG 0x1378
1037#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1038#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1039#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1040#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1041#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1042#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1043#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1044#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1045#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1046#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1047
1048/*
1049 * EXP_CTS_TIME:
1050 */
1051#define EXP_CTS_TIME 0x137c
1052
1053/*
1054 * EXP_ACK_TIME:
1055 */
1056#define EXP_ACK_TIME 0x1380
1057
1058/*
1059 * RX_FILTER_CFG: RX configuration register.
1060 */
1061#define RX_FILTER_CFG 0x1400
1062#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1063#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1064#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1065#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1066#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1067#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1068#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1069#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1070#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1071#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1072#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1073#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1074#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1075#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1076#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1077#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1078#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1079
1080/*
1081 * AUTO_RSP_CFG:
1082 * AUTORESPONDER: 0: disable, 1: enable
1083 * BAC_ACK_POLICY: 0:long, 1:short preamble
1084 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1085 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1086 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1087 * DUAL_CTS_EN: Power bit value in control frame
1088 * ACK_CTS_PSM_BIT:Power bit value in control frame
1089 */
1090#define AUTO_RSP_CFG 0x1404
1091#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1092#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1093#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1094#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1095#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1096#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1097#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1098
1099/*
1100 * LEGACY_BASIC_RATE:
1101 */
1102#define LEGACY_BASIC_RATE 0x1408
1103
1104/*
1105 * HT_BASIC_RATE:
1106 */
1107#define HT_BASIC_RATE 0x140c
1108
1109/*
1110 * HT_CTRL_CFG:
1111 */
1112#define HT_CTRL_CFG 0x1410
1113
1114/*
1115 * SIFS_COST_CFG:
1116 */
1117#define SIFS_COST_CFG 0x1414
1118
1119/*
1120 * RX_PARSER_CFG:
1121 * Set NAV for all received frames
1122 */
1123#define RX_PARSER_CFG 0x1418
1124
1125/*
1126 * TX_SEC_CNT0:
1127 */
1128#define TX_SEC_CNT0 0x1500
1129
1130/*
1131 * RX_SEC_CNT0:
1132 */
1133#define RX_SEC_CNT0 0x1504
1134
1135/*
1136 * CCMP_FC_MUTE:
1137 */
1138#define CCMP_FC_MUTE 0x1508
1139
1140/*
1141 * TXOP_HLDR_ADDR0:
1142 */
1143#define TXOP_HLDR_ADDR0 0x1600
1144
1145/*
1146 * TXOP_HLDR_ADDR1:
1147 */
1148#define TXOP_HLDR_ADDR1 0x1604
1149
1150/*
1151 * TXOP_HLDR_ET:
1152 */
1153#define TXOP_HLDR_ET 0x1608
1154
1155/*
1156 * QOS_CFPOLL_RA_DW0:
1157 */
1158#define QOS_CFPOLL_RA_DW0 0x160c
1159
1160/*
1161 * QOS_CFPOLL_RA_DW1:
1162 */
1163#define QOS_CFPOLL_RA_DW1 0x1610
1164
1165/*
1166 * QOS_CFPOLL_QC:
1167 */
1168#define QOS_CFPOLL_QC 0x1614
1169
1170/*
1171 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1172 */
1173#define RX_STA_CNT0 0x1700
1174#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1175#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1176
1177/*
1178 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1179 */
1180#define RX_STA_CNT1 0x1704
1181#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1182#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1183
1184/*
1185 * RX_STA_CNT2:
1186 */
1187#define RX_STA_CNT2 0x1708
1188#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1189#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1190
1191/*
1192 * TX_STA_CNT0: TX Beacon count
1193 */
1194#define TX_STA_CNT0 0x170c
1195#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1196#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1197
1198/*
1199 * TX_STA_CNT1: TX tx count
1200 */
1201#define TX_STA_CNT1 0x1710
1202#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1203#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1204
1205/*
1206 * TX_STA_CNT2: TX tx count
1207 */
1208#define TX_STA_CNT2 0x1714
1209#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1210#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1211
1212/*
1213 * TX_STA_FIFO: TX Result for specific PID status fifo register
1214 */
1215#define TX_STA_FIFO 0x1718
1216#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1217#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1218#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1219#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1220#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1221#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1222#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1223#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1224#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1225
1226/*
1227 * TX_AGG_CNT: Debug counter
1228 */
1229#define TX_AGG_CNT 0x171c
1230#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1231#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1232
1233/*
1234 * TX_AGG_CNT0:
1235 */
1236#define TX_AGG_CNT0 0x1720
1237#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1238#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1239
1240/*
1241 * TX_AGG_CNT1:
1242 */
1243#define TX_AGG_CNT1 0x1724
1244#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1245#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1246
1247/*
1248 * TX_AGG_CNT2:
1249 */
1250#define TX_AGG_CNT2 0x1728
1251#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1252#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1253
1254/*
1255 * TX_AGG_CNT3:
1256 */
1257#define TX_AGG_CNT3 0x172c
1258#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1259#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1260
1261/*
1262 * TX_AGG_CNT4:
1263 */
1264#define TX_AGG_CNT4 0x1730
1265#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1266#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1267
1268/*
1269 * TX_AGG_CNT5:
1270 */
1271#define TX_AGG_CNT5 0x1734
1272#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1273#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1274
1275/*
1276 * TX_AGG_CNT6:
1277 */
1278#define TX_AGG_CNT6 0x1738
1279#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1280#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1281
1282/*
1283 * TX_AGG_CNT7:
1284 */
1285#define TX_AGG_CNT7 0x173c
1286#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1287#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1288
1289/*
1290 * MPDU_DENSITY_CNT:
1291 * TX_ZERO_DEL: TX zero length delimiter count
1292 * RX_ZERO_DEL: RX zero length delimiter count
1293 */
1294#define MPDU_DENSITY_CNT 0x1740
1295#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1296#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1297
1298/*
1299 * Security key table memory.
1300 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1301 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1302 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1303 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
Bartlomiej Zolnierkiewicza4385212009-11-04 18:36:02 +0100[diff] [blame]1304 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1305 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]1306 */
1307#define MAC_WCID_BASE 0x1800
1308#define PAIRWISE_KEY_TABLE_BASE 0x4000
1309#define MAC_IVEIV_TABLE_BASE 0x6000
1310#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1311#define SHARED_KEY_TABLE_BASE 0x6c00
1312#define SHARED_KEY_MODE_BASE 0x7000
1313
1314#define MAC_WCID_ENTRY(__idx) \
1315 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1316#define PAIRWISE_KEY_ENTRY(__idx) \
1317 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1318#define MAC_IVEIV_ENTRY(__idx) \
1319 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1320#define MAC_WCID_ATTR_ENTRY(__idx) \
1321 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1322#define SHARED_KEY_ENTRY(__idx) \
1323 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1324#define SHARED_KEY_MODE_ENTRY(__idx) \
1325 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1326
1327struct mac_wcid_entry {
1328 u8 mac[6];
1329 u8 reserved[2];
1330} __attribute__ ((packed));
1331
1332struct hw_key_entry {
1333 u8 key[16];
1334 u8 tx_mic[8];
1335 u8 rx_mic[8];
1336} __attribute__ ((packed));
1337
1338struct mac_iveiv_entry {
1339 u8 iv[8];
1340} __attribute__ ((packed));
1341
1342/*
1343 * MAC_WCID_ATTRIBUTE:
1344 */
1345#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1346#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1347#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1348#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1349
1350/*
1351 * SHARED_KEY_MODE:
1352 */
1353#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1354#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1355#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1356#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1357#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1358#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1359#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1360#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1361
1362/*
1363 * HOST-MCU communication
1364 */
1365
1366/*
1367 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1368 */
1369#define H2M_MAILBOX_CSR 0x7010
1370#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1371#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1372#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1373#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1374
1375/*
1376 * H2M_MAILBOX_CID:
1377 */
1378#define H2M_MAILBOX_CID 0x7014
1379#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1380#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1381#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1382#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1383
1384/*
1385 * H2M_MAILBOX_STATUS:
1386 */
1387#define H2M_MAILBOX_STATUS 0x701c
1388
1389/*
1390 * H2M_INT_SRC:
1391 */
1392#define H2M_INT_SRC 0x7024
1393
1394/*
1395 * H2M_BBP_AGENT:
1396 */
1397#define H2M_BBP_AGENT 0x7028
1398
1399/*
1400 * MCU_LEDCS: LED control for MCU Mailbox.
1401 */
1402#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1403#define MCU_LEDCS_POLARITY FIELD8(0x01)
1404
1405/*
1406 * HW_CS_CTS_BASE:
1407 * Carrier-sense CTS frame base address.
1408 * It's where mac stores carrier-sense frame for carrier-sense function.
1409 */
1410#define HW_CS_CTS_BASE 0x7700
1411
1412/*
1413 * HW_DFS_CTS_BASE:
Bartlomiej Zolnierkiewicza4385212009-11-04 18:36:02 +0100[diff] [blame]1414 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
Bartlomiej Zolnierkiewiczb54f78a2009-11-04 18:35:54 +0100[diff] [blame]1415 */
1416#define HW_DFS_CTS_BASE 0x7780
1417
1418/*
1419 * TXRX control registers - base address 0x3000
1420 */
1421
1422/*
1423 * TXRX_CSR1:
1424 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1425 */
1426#define TXRX_CSR1 0x77d0
1427
1428/*
1429 * HW_DEBUG_SETTING_BASE:
1430 * since NULL frame won't be that long (256 byte)
1431 * We steal 16 tail bytes to save debugging settings
1432 */
1433#define HW_DEBUG_SETTING_BASE 0x77f0
1434#define HW_DEBUG_SETTING_BASE2 0x7770
1435
1436/*
1437 * HW_BEACON_BASE
1438 * In order to support maximum 8 MBSS and its maximum length
1439 * is 512 bytes for each beacon
1440 * Three section discontinue memory segments will be used.
1441 * 1. The original region for BCN 0~3
1442 * 2. Extract memory from FCE table for BCN 4~5
1443 * 3. Extract memory from Pair-wise key table for BCN 6~7
1444 * It occupied those memory of wcid 238~253 for BCN 6
1445 * and wcid 222~237 for BCN 7
1446 *
1447 * IMPORTANT NOTE: Not sure why legacy driver does this,
1448 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1449 */
1450#define HW_BEACON_BASE0 0x7800
1451#define HW_BEACON_BASE1 0x7a00
1452#define HW_BEACON_BASE2 0x7c00
1453#define HW_BEACON_BASE3 0x7e00
1454#define HW_BEACON_BASE4 0x7200
1455#define HW_BEACON_BASE5 0x7400
1456#define HW_BEACON_BASE6 0x5dc0
1457#define HW_BEACON_BASE7 0x5bc0
1458
1459#define HW_BEACON_OFFSET(__index) \
1460 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1461 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1462 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1463
1464/*
1465 * BBP registers.
1466 * The wordsize of the BBP is 8 bits.
1467 */
1468
1469/*
1470 * BBP 1: TX Antenna
1471 */
1472#define BBP1_TX_POWER FIELD8(0x07)
1473#define BBP1_TX_ANTENNA FIELD8(0x18)
1474
1475/*
1476 * BBP 3: RX Antenna
1477 */
1478#define BBP3_RX_ANTENNA FIELD8(0x18)
1479#define BBP3_HT40_PLUS FIELD8(0x20)
1480
1481/*
1482 * BBP 4: Bandwidth
1483 */
1484#define BBP4_TX_BF FIELD8(0x01)
1485#define BBP4_BANDWIDTH FIELD8(0x18)
1486
1487/*
1488 * RFCSR registers
1489 * The wordsize of the RFCSR is 8 bits.
1490 */
1491
1492/*
1493 * RFCSR 6:
1494 */
1495#define RFCSR6_R FIELD8(0x03)
1496
1497/*
1498 * RFCSR 7:
1499 */
1500#define RFCSR7_RF_TUNING FIELD8(0x01)
1501
1502/*
1503 * RFCSR 12:
1504 */
1505#define RFCSR12_TX_POWER FIELD8(0x1f)
1506
1507/*
1508 * RFCSR 22:
1509 */
1510#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1511
1512/*
1513 * RFCSR 23:
1514 */
1515#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1516
1517/*
1518 * RFCSR 30:
1519 */
1520#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1521
1522/*
1523 * RF registers
1524 */
1525
1526/*
1527 * RF 2
1528 */
1529#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1530#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1531#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1532
1533/*
1534 * RF 3
1535 */
1536#define RF3_TXPOWER_G FIELD32(0x00003e00)
1537#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1538#define RF3_TXPOWER_A FIELD32(0x00003c00)
1539
1540/*
1541 * RF 4
1542 */
1543#define RF4_TXPOWER_G FIELD32(0x000007c0)
1544#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1545#define RF4_TXPOWER_A FIELD32(0x00000780)
1546#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1547#define RF4_HT40 FIELD32(0x00200000)
1548
1549/*
1550 * EEPROM content.
1551 * The wordsize of the EEPROM is 16 bits.
1552 */
1553
1554/*
1555 * EEPROM Version
1556 */
1557#define EEPROM_VERSION 0x0001
1558#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1559#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1560
1561/*
1562 * HW MAC address.
1563 */
1564#define EEPROM_MAC_ADDR_0 0x0002
1565#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1566#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1567#define EEPROM_MAC_ADDR_1 0x0003
1568#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1569#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1570#define EEPROM_MAC_ADDR_2 0x0004
1571#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1572#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1573
1574/*
1575 * EEPROM ANTENNA config
1576 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1577 * TXPATH: 1: 1T, 2: 2T
1578 */
1579#define EEPROM_ANTENNA 0x001a
1580#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1581#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1582#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1583
1584/*
1585 * EEPROM NIC config
1586 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1587 */
1588#define EEPROM_NIC 0x001b
1589#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1590#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1591#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1592#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1593#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1594#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1595#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1596#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1597#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1598#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1599
1600/*
1601 * EEPROM frequency
1602 */
1603#define EEPROM_FREQ 0x001d
1604#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1605#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1606#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1607
1608/*
1609 * EEPROM LED
1610 * POLARITY_RDY_G: Polarity RDY_G setting.
1611 * POLARITY_RDY_A: Polarity RDY_A setting.
1612 * POLARITY_ACT: Polarity ACT setting.
1613 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1614 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1615 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1616 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1617 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1618 * LED_MODE: Led mode.
1619 */
1620#define EEPROM_LED1 0x001e
1621#define EEPROM_LED2 0x001f
1622#define EEPROM_LED3 0x0020
1623#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1624#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1625#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1626#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1627#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1628#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1629#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1630#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1631#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1632
1633/*
1634 * EEPROM LNA
1635 */
1636#define EEPROM_LNA 0x0022
1637#define EEPROM_LNA_BG FIELD16(0x00ff)
1638#define EEPROM_LNA_A0 FIELD16(0xff00)
1639
1640/*
1641 * EEPROM RSSI BG offset
1642 */
1643#define EEPROM_RSSI_BG 0x0023
1644#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1645#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1646
1647/*
1648 * EEPROM RSSI BG2 offset
1649 */
1650#define EEPROM_RSSI_BG2 0x0024
1651#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1652#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1653
1654/*
1655 * EEPROM RSSI A offset
1656 */
1657#define EEPROM_RSSI_A 0x0025
1658#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1659#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1660
1661/*
1662 * EEPROM RSSI A2 offset
1663 */
1664#define EEPROM_RSSI_A2 0x0026
1665#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1666#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1667
1668/*
1669 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1670 * This is delta in 40MHZ.
1671 * VALUE: Tx Power dalta value (MAX=4)
1672 * TYPE: 1: Plus the delta value, 0: minus the delta value
1673 * TXPOWER: Enable:
1674 */
1675#define EEPROM_TXPOWER_DELTA 0x0028
1676#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1677#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1678#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1679
1680/*
1681 * EEPROM TXPOWER 802.11BG
1682 */
1683#define EEPROM_TXPOWER_BG1 0x0029
1684#define EEPROM_TXPOWER_BG2 0x0030
1685#define EEPROM_TXPOWER_BG_SIZE 7
1686#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1687#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1688
1689/*
1690 * EEPROM TXPOWER 802.11A
1691 */
1692#define EEPROM_TXPOWER_A1 0x003c
1693#define EEPROM_TXPOWER_A2 0x0053
1694#define EEPROM_TXPOWER_A_SIZE 6
1695#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1696#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1697
1698/*
1699 * EEPROM TXpower byrate: 20MHZ power
1700 */
1701#define EEPROM_TXPOWER_BYRATE 0x006f
1702
1703/*
1704 * EEPROM BBP.
1705 */
1706#define EEPROM_BBP_START 0x0078
1707#define EEPROM_BBP_SIZE 16
1708#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1709#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1710
1711/*
1712 * MCU mailbox commands.
1713 */
1714#define MCU_SLEEP 0x30
1715#define MCU_WAKEUP 0x31
1716#define MCU_RADIO_OFF 0x35
1717#define MCU_CURRENT 0x36
1718#define MCU_LED 0x50
1719#define MCU_LED_STRENGTH 0x51
1720#define MCU_LED_1 0x52
1721#define MCU_LED_2 0x53
1722#define MCU_LED_3 0x54
1723#define MCU_RADAR 0x60
1724#define MCU_BOOT_SIGNAL 0x72
1725#define MCU_BBP_SIGNAL 0x80
1726#define MCU_POWER_SAVE 0x83
1727
1728/*
1729 * MCU mailbox tokens
1730 */
1731#define TOKEN_WAKUP 3
1732
1733/*
1734 * DMA descriptor defines.
1735 */
1736#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1737#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1738
1739/*
1740 * TX WI structure
1741 */
1742
1743/*
1744 * Word0
1745 * FRAG: 1 To inform TKIP engine this is a fragment.
1746 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1747 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1748 * BW: Channel bandwidth 20MHz or 40 MHz
1749 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1750 */
1751#define TXWI_W0_FRAG FIELD32(0x00000001)
1752#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1753#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1754#define TXWI_W0_TS FIELD32(0x00000008)
1755#define TXWI_W0_AMPDU FIELD32(0x00000010)
1756#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1757#define TXWI_W0_TX_OP FIELD32(0x00000300)
1758#define TXWI_W0_MCS FIELD32(0x007f0000)
1759#define TXWI_W0_BW FIELD32(0x00800000)
1760#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1761#define TXWI_W0_STBC FIELD32(0x06000000)
1762#define TXWI_W0_IFS FIELD32(0x08000000)
1763#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1764
1765/*
1766 * Word1
1767 */
1768#define TXWI_W1_ACK FIELD32(0x00000001)
1769#define TXWI_W1_NSEQ FIELD32(0x00000002)
1770#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1771#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1772#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1773#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1774
1775/*
1776 * Word2
1777 */
1778#define TXWI_W2_IV FIELD32(0xffffffff)
1779
1780/*
1781 * Word3
1782 */
1783#define TXWI_W3_EIV FIELD32(0xffffffff)
1784
1785/*
1786 * RX WI structure
1787 */
1788
1789/*
1790 * Word0
1791 */
1792#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1793#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1794#define RXWI_W0_BSSID FIELD32(0x00001c00)
1795#define RXWI_W0_UDF FIELD32(0x0000e000)
1796#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1797#define RXWI_W0_TID FIELD32(0xf0000000)
1798
1799/*
1800 * Word1
1801 */
1802#define RXWI_W1_FRAG FIELD32(0x0000000f)
1803#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1804#define RXWI_W1_MCS FIELD32(0x007f0000)
1805#define RXWI_W1_BW FIELD32(0x00800000)
1806#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1807#define RXWI_W1_STBC FIELD32(0x06000000)
1808#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1809
1810/*
1811 * Word2
1812 */
1813#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1814#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1815#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1816
1817/*
1818 * Word3
1819 */
1820#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1821#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1822
1823/*
1824 * Macros for converting txpower from EEPROM to mac80211 value
1825 * and from mac80211 value to register value.
1826 */
1827#define MIN_G_TXPOWER 0
1828#define MIN_A_TXPOWER -7
1829#define MAX_G_TXPOWER 31
1830#define MAX_A_TXPOWER 15
1831#define DEFAULT_TXPOWER 5
1832
1833#define TXPOWER_G_FROM_DEV(__txpower) \
1834 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1835
1836#define TXPOWER_G_TO_DEV(__txpower) \
1837 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1838
1839#define TXPOWER_A_FROM_DEV(__txpower) \
1840 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1841
1842#define TXPOWER_A_TO_DEV(__txpower) \
1843 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1844
1845#endif /* RT2800_H */