Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * CCI cache coherent interconnect driver |
| 3 | * |
| 4 | * Copyright (C) 2013 ARM Ltd. |
| 5 | * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 12 | * kind, whether express or implied; without even the implied warranty |
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/arm-cci.h> |
| 18 | #include <linux/io.h> |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/of_address.h> |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 22 | #include <linux/of_irq.h> |
| 23 | #include <linux/of_platform.h> |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 24 | #include <linux/perf_event.h> |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 25 | #include <linux/platform_device.h> |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 26 | #include <linux/slab.h> |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 27 | #include <linux/spinlock.h> |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 28 | |
| 29 | #include <asm/cacheflush.h> |
| 30 | #include <asm/smp_plat.h> |
| 31 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 32 | static void __iomem *cci_ctrl_base; |
| 33 | static unsigned long cci_ctrl_phys; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 34 | |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 35 | #ifdef CONFIG_ARM_CCI400_PORT_CTRL |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 36 | struct cci_nb_ports { |
| 37 | unsigned int nb_ace; |
| 38 | unsigned int nb_ace_lite; |
| 39 | }; |
| 40 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 41 | static const struct cci_nb_ports cci400_ports = { |
| 42 | .nb_ace = 2, |
| 43 | .nb_ace_lite = 3 |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 44 | }; |
| 45 | |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 46 | #define CCI400_PORTS_DATA (&cci400_ports) |
| 47 | #else |
| 48 | #define CCI400_PORTS_DATA (NULL) |
| 49 | #endif |
| 50 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 51 | static const struct of_device_id arm_cci_matches[] = { |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 52 | #ifdef CONFIG_ARM_CCI400_COMMON |
| 53 | {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA }, |
| 54 | #endif |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 55 | {}, |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 56 | }; |
| 57 | |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 58 | #ifdef CONFIG_ARM_CCI400_PMU |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 59 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 60 | #define DRIVER_NAME "CCI-400" |
| 61 | #define DRIVER_NAME_PMU DRIVER_NAME " PMU" |
| 62 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 63 | #define CCI_PMCR 0x0100 |
| 64 | #define CCI_PID2 0x0fe8 |
| 65 | |
| 66 | #define CCI_PMCR_CEN 0x00000001 |
| 67 | #define CCI_PMCR_NCNT_MASK 0x0000f800 |
| 68 | #define CCI_PMCR_NCNT_SHIFT 11 |
| 69 | |
| 70 | #define CCI_PID2_REV_MASK 0xf0 |
| 71 | #define CCI_PID2_REV_SHIFT 4 |
| 72 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 73 | #define CCI_PMU_EVT_SEL 0x000 |
| 74 | #define CCI_PMU_CNTR 0x004 |
| 75 | #define CCI_PMU_CNTR_CTRL 0x008 |
| 76 | #define CCI_PMU_OVRFLW 0x00c |
| 77 | |
| 78 | #define CCI_PMU_OVRFLW_FLAG 1 |
| 79 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 80 | #define CCI_PMU_CNTR_SIZE(model) ((model)->cntr_size) |
| 81 | #define CCI_PMU_CNTR_BASE(model, idx) ((idx) * CCI_PMU_CNTR_SIZE(model)) |
| 82 | #define CCI_PMU_CNTR_MASK ((1ULL << 32) -1) |
| 83 | #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1) |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 84 | |
Suzuki K. Poulose | 874c571 | 2015-03-18 12:24:42 +0000 | [diff] [blame] | 85 | #define CCI_PMU_EVENT_MASK 0xffUL |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 86 | #define CCI_PMU_EVENT_SOURCE(event) ((event >> 5) & 0x7) |
| 87 | #define CCI_PMU_EVENT_CODE(event) (event & 0x1f) |
| 88 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 89 | #define CCI_PMU_MAX_HW_CNTRS(model) \ |
| 90 | ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs) |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 91 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 92 | /* Types of interfaces that can generate events */ |
| 93 | enum { |
| 94 | CCI_IF_SLAVE, |
| 95 | CCI_IF_MASTER, |
| 96 | CCI_IF_MAX, |
| 97 | }; |
| 98 | |
| 99 | struct event_range { |
| 100 | u32 min; |
| 101 | u32 max; |
| 102 | }; |
| 103 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 104 | struct cci_pmu_hw_events { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 105 | struct perf_event **events; |
| 106 | unsigned long *used_mask; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 107 | raw_spinlock_t pmu_lock; |
| 108 | }; |
| 109 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 110 | struct cci_pmu; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 111 | /* |
| 112 | * struct cci_pmu_model: |
| 113 | * @fixed_hw_cntrs - Number of fixed event counters |
| 114 | * @num_hw_cntrs - Maximum number of programmable event counters |
| 115 | * @cntr_size - Size of an event counter mapping |
| 116 | */ |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 117 | struct cci_pmu_model { |
| 118 | char *name; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 119 | u32 fixed_hw_cntrs; |
| 120 | u32 num_hw_cntrs; |
| 121 | u32 cntr_size; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 122 | struct event_range event_ranges[CCI_IF_MAX]; |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 123 | int (*validate_hw_event)(struct cci_pmu *, unsigned long); |
| 124 | int (*get_event_idx)(struct cci_pmu *, struct cci_pmu_hw_events *, unsigned long); |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 125 | }; |
| 126 | |
| 127 | static struct cci_pmu_model cci_pmu_models[]; |
| 128 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 129 | struct cci_pmu { |
| 130 | void __iomem *base; |
| 131 | struct pmu pmu; |
| 132 | int nr_irqs; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 133 | int *irqs; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 134 | unsigned long active_irqs; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 135 | const struct cci_pmu_model *model; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 136 | struct cci_pmu_hw_events hw_events; |
| 137 | struct platform_device *plat_device; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 138 | int num_cntrs; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 139 | atomic_t active_events; |
| 140 | struct mutex reserve_mutex; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 141 | struct notifier_block cpu_nb; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 142 | cpumask_t cpus; |
| 143 | }; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 144 | |
| 145 | #define to_cci_pmu(c) (container_of(c, struct cci_pmu, pmu)) |
| 146 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 147 | /* Port ids */ |
| 148 | #define CCI_PORT_S0 0 |
| 149 | #define CCI_PORT_S1 1 |
| 150 | #define CCI_PORT_S2 2 |
| 151 | #define CCI_PORT_S3 3 |
| 152 | #define CCI_PORT_S4 4 |
| 153 | #define CCI_PORT_M0 5 |
| 154 | #define CCI_PORT_M1 6 |
| 155 | #define CCI_PORT_M2 7 |
| 156 | |
| 157 | #define CCI_REV_R0 0 |
| 158 | #define CCI_REV_R1 1 |
Punit Agrawal | 6fb0c4a | 2014-02-19 12:17:02 +0000 | [diff] [blame] | 159 | #define CCI_REV_R1_PX 5 |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 160 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 161 | /* |
| 162 | * Instead of an event id to monitor CCI cycles, a dedicated counter is |
| 163 | * provided. Use 0xff to represent CCI cycles and hope that no future revisions |
| 164 | * make use of this event in hardware. |
| 165 | */ |
| 166 | enum cci400_perf_events { |
| 167 | CCI_PMU_CYCLES = 0xff |
| 168 | }; |
| 169 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 170 | #define CCI_PMU_CYCLE_CNTR_IDX 0 |
| 171 | #define CCI_PMU_CNTR0_IDX 1 |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 172 | |
| 173 | /* |
| 174 | * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8 |
| 175 | * ports and bits 4:0 are event codes. There are different event codes |
| 176 | * associated with each port type. |
| 177 | * |
| 178 | * Additionally, the range of events associated with the port types changed |
| 179 | * between Rev0 and Rev1. |
| 180 | * |
| 181 | * The constants below define the range of valid codes for each port type for |
| 182 | * the different revisions and are used to validate the event to be monitored. |
| 183 | */ |
| 184 | |
| 185 | #define CCI_REV_R0_SLAVE_PORT_MIN_EV 0x00 |
| 186 | #define CCI_REV_R0_SLAVE_PORT_MAX_EV 0x13 |
| 187 | #define CCI_REV_R0_MASTER_PORT_MIN_EV 0x14 |
| 188 | #define CCI_REV_R0_MASTER_PORT_MAX_EV 0x1a |
| 189 | |
| 190 | #define CCI_REV_R1_SLAVE_PORT_MIN_EV 0x00 |
| 191 | #define CCI_REV_R1_SLAVE_PORT_MAX_EV 0x14 |
| 192 | #define CCI_REV_R1_MASTER_PORT_MIN_EV 0x00 |
| 193 | #define CCI_REV_R1_MASTER_PORT_MAX_EV 0x11 |
| 194 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 195 | static int cci400_get_event_idx(struct cci_pmu *cci_pmu, |
| 196 | struct cci_pmu_hw_events *hw, |
| 197 | unsigned long cci_event) |
| 198 | { |
| 199 | int idx; |
| 200 | |
| 201 | /* cycles event idx is fixed */ |
| 202 | if (cci_event == CCI_PMU_CYCLES) { |
| 203 | if (test_and_set_bit(CCI_PMU_CYCLE_CNTR_IDX, hw->used_mask)) |
| 204 | return -EAGAIN; |
| 205 | |
| 206 | return CCI_PMU_CYCLE_CNTR_IDX; |
| 207 | } |
| 208 | |
| 209 | for (idx = CCI_PMU_CNTR0_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); ++idx) |
| 210 | if (!test_and_set_bit(idx, hw->used_mask)) |
| 211 | return idx; |
| 212 | |
| 213 | /* No counters available */ |
| 214 | return -EAGAIN; |
| 215 | } |
| 216 | |
| 217 | static int cci400_validate_hw_event(struct cci_pmu *cci_pmu, unsigned long hw_event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 218 | { |
| 219 | u8 ev_source = CCI_PMU_EVENT_SOURCE(hw_event); |
| 220 | u8 ev_code = CCI_PMU_EVENT_CODE(hw_event); |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 221 | int if_type; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 222 | |
Suzuki K. Poulose | 874c571 | 2015-03-18 12:24:42 +0000 | [diff] [blame] | 223 | if (hw_event & ~CCI_PMU_EVENT_MASK) |
| 224 | return -ENOENT; |
| 225 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 226 | if (hw_event == CCI_PMU_CYCLES) |
| 227 | return hw_event; |
| 228 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 229 | switch (ev_source) { |
| 230 | case CCI_PORT_S0: |
| 231 | case CCI_PORT_S1: |
| 232 | case CCI_PORT_S2: |
| 233 | case CCI_PORT_S3: |
| 234 | case CCI_PORT_S4: |
| 235 | /* Slave Interface */ |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 236 | if_type = CCI_IF_SLAVE; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 237 | break; |
| 238 | case CCI_PORT_M0: |
| 239 | case CCI_PORT_M1: |
| 240 | case CCI_PORT_M2: |
| 241 | /* Master Interface */ |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 242 | if_type = CCI_IF_MASTER; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 243 | break; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 244 | default: |
| 245 | return -ENOENT; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 246 | } |
| 247 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 248 | if (ev_code >= cci_pmu->model->event_ranges[if_type].min && |
| 249 | ev_code <= cci_pmu->model->event_ranges[if_type].max) |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 250 | return hw_event; |
| 251 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 252 | return -ENOENT; |
| 253 | } |
| 254 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 255 | static int probe_cci_revision(void) |
| 256 | { |
| 257 | int rev; |
| 258 | rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK; |
| 259 | rev >>= CCI_PID2_REV_SHIFT; |
| 260 | |
| 261 | if (rev < CCI_REV_R1_PX) |
| 262 | return CCI_REV_R0; |
| 263 | else |
| 264 | return CCI_REV_R1; |
| 265 | } |
| 266 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 267 | static const struct cci_pmu_model *probe_cci_model(struct platform_device *pdev) |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 268 | { |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 269 | if (platform_has_secure_cci_access()) |
| 270 | return &cci_pmu_models[probe_cci_revision()]; |
| 271 | return NULL; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 272 | } |
| 273 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 274 | static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 275 | { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 276 | return 0 <= idx && idx <= CCI_PMU_CNTR_LAST(cci_pmu); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 277 | } |
| 278 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 279 | static u32 pmu_read_register(struct cci_pmu *cci_pmu, int idx, unsigned int offset) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 280 | { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 281 | return readl_relaxed(cci_pmu->base + |
| 282 | CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 283 | } |
| 284 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 285 | static void pmu_write_register(struct cci_pmu *cci_pmu, u32 value, |
| 286 | int idx, unsigned int offset) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 287 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 288 | return writel_relaxed(value, cci_pmu->base + |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 289 | CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 290 | } |
| 291 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 292 | static void pmu_disable_counter(struct cci_pmu *cci_pmu, int idx) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 293 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 294 | pmu_write_register(cci_pmu, 0, idx, CCI_PMU_CNTR_CTRL); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 295 | } |
| 296 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 297 | static void pmu_enable_counter(struct cci_pmu *cci_pmu, int idx) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 298 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 299 | pmu_write_register(cci_pmu, 1, idx, CCI_PMU_CNTR_CTRL); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 300 | } |
| 301 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 302 | static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 303 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 304 | pmu_write_register(cci_pmu, event, idx, CCI_PMU_EVT_SEL); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 305 | } |
| 306 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 307 | /* |
| 308 | * Returns the number of programmable counters actually implemented |
| 309 | * by the cci |
| 310 | */ |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 311 | static u32 pmu_get_max_counters(void) |
| 312 | { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 313 | return (readl_relaxed(cci_ctrl_base + CCI_PMCR) & |
| 314 | CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 315 | } |
| 316 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 317 | static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 318 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 319 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 320 | unsigned long cci_event = event->hw.config_base; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 321 | int idx; |
| 322 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 323 | if (cci_pmu->model->get_event_idx) |
| 324 | return cci_pmu->model->get_event_idx(cci_pmu, hw, cci_event); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 325 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 326 | /* Generic code to find an unused idx from the mask */ |
| 327 | for(idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 328 | if (!test_and_set_bit(idx, hw->used_mask)) |
| 329 | return idx; |
| 330 | |
| 331 | /* No counters available */ |
| 332 | return -EAGAIN; |
| 333 | } |
| 334 | |
| 335 | static int pmu_map_event(struct perf_event *event) |
| 336 | { |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 337 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 338 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 339 | if (event->attr.type < PERF_TYPE_MAX || |
| 340 | !cci_pmu->model->validate_hw_event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 341 | return -ENOENT; |
| 342 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 343 | return cci_pmu->model->validate_hw_event(cci_pmu, event->attr.config); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 344 | } |
| 345 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 346 | static int pmu_request_irq(struct cci_pmu *cci_pmu, irq_handler_t handler) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 347 | { |
| 348 | int i; |
| 349 | struct platform_device *pmu_device = cci_pmu->plat_device; |
| 350 | |
| 351 | if (unlikely(!pmu_device)) |
| 352 | return -ENODEV; |
| 353 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 354 | if (cci_pmu->nr_irqs < 1) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 355 | dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); |
| 356 | return -ENODEV; |
| 357 | } |
| 358 | |
| 359 | /* |
| 360 | * Register all available CCI PMU interrupts. In the interrupt handler |
| 361 | * we iterate over the counters checking for interrupt source (the |
| 362 | * overflowing counter) and clear it. |
| 363 | * |
| 364 | * This should allow handling of non-unique interrupt for the counters. |
| 365 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 366 | for (i = 0; i < cci_pmu->nr_irqs; i++) { |
| 367 | int err = request_irq(cci_pmu->irqs[i], handler, IRQF_SHARED, |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 368 | "arm-cci-pmu", cci_pmu); |
| 369 | if (err) { |
| 370 | dev_err(&pmu_device->dev, "unable to request IRQ%d for ARM CCI PMU counters\n", |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 371 | cci_pmu->irqs[i]); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 372 | return err; |
| 373 | } |
| 374 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 375 | set_bit(i, &cci_pmu->active_irqs); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 376 | } |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 381 | static void pmu_free_irq(struct cci_pmu *cci_pmu) |
| 382 | { |
| 383 | int i; |
| 384 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 385 | for (i = 0; i < cci_pmu->nr_irqs; i++) { |
| 386 | if (!test_and_clear_bit(i, &cci_pmu->active_irqs)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 387 | continue; |
| 388 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 389 | free_irq(cci_pmu->irqs[i], cci_pmu); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 390 | } |
| 391 | } |
| 392 | |
| 393 | static u32 pmu_read_counter(struct perf_event *event) |
| 394 | { |
| 395 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 396 | struct hw_perf_event *hw_counter = &event->hw; |
| 397 | int idx = hw_counter->idx; |
| 398 | u32 value; |
| 399 | |
| 400 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) { |
| 401 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
| 402 | return 0; |
| 403 | } |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 404 | value = pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 405 | |
| 406 | return value; |
| 407 | } |
| 408 | |
| 409 | static void pmu_write_counter(struct perf_event *event, u32 value) |
| 410 | { |
| 411 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 412 | struct hw_perf_event *hw_counter = &event->hw; |
| 413 | int idx = hw_counter->idx; |
| 414 | |
| 415 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) |
| 416 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
| 417 | else |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 418 | pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 419 | } |
| 420 | |
| 421 | static u64 pmu_event_update(struct perf_event *event) |
| 422 | { |
| 423 | struct hw_perf_event *hwc = &event->hw; |
| 424 | u64 delta, prev_raw_count, new_raw_count; |
| 425 | |
| 426 | do { |
| 427 | prev_raw_count = local64_read(&hwc->prev_count); |
| 428 | new_raw_count = pmu_read_counter(event); |
| 429 | } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 430 | new_raw_count) != prev_raw_count); |
| 431 | |
| 432 | delta = (new_raw_count - prev_raw_count) & CCI_PMU_CNTR_MASK; |
| 433 | |
| 434 | local64_add(delta, &event->count); |
| 435 | |
| 436 | return new_raw_count; |
| 437 | } |
| 438 | |
| 439 | static void pmu_read(struct perf_event *event) |
| 440 | { |
| 441 | pmu_event_update(event); |
| 442 | } |
| 443 | |
| 444 | void pmu_event_set_period(struct perf_event *event) |
| 445 | { |
| 446 | struct hw_perf_event *hwc = &event->hw; |
| 447 | /* |
| 448 | * The CCI PMU counters have a period of 2^32. To account for the |
| 449 | * possiblity of extreme interrupt latency we program for a period of |
| 450 | * half that. Hopefully we can handle the interrupt before another 2^31 |
| 451 | * events occur and the counter overtakes its previous value. |
| 452 | */ |
| 453 | u64 val = 1ULL << 31; |
| 454 | local64_set(&hwc->prev_count, val); |
| 455 | pmu_write_counter(event, val); |
| 456 | } |
| 457 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 458 | static irqreturn_t pmu_handle_irq(int irq_num, void *dev) |
| 459 | { |
| 460 | unsigned long flags; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 461 | struct cci_pmu *cci_pmu = dev; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 462 | struct cci_pmu_hw_events *events = &cci_pmu->hw_events; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 463 | int idx, handled = IRQ_NONE; |
| 464 | |
| 465 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 466 | /* |
| 467 | * Iterate over counters and update the corresponding perf events. |
| 468 | * This should work regardless of whether we have per-counter overflow |
| 469 | * interrupt or a combined overflow interrupt. |
| 470 | */ |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 471 | for (idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 472 | struct perf_event *event = events->events[idx]; |
| 473 | struct hw_perf_event *hw_counter; |
| 474 | |
| 475 | if (!event) |
| 476 | continue; |
| 477 | |
| 478 | hw_counter = &event->hw; |
| 479 | |
| 480 | /* Did this counter overflow? */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 481 | if (!(pmu_read_register(cci_pmu, idx, CCI_PMU_OVRFLW) & |
Himangi Saraogi | fc5130d | 2014-07-30 11:37:35 +0100 | [diff] [blame] | 482 | CCI_PMU_OVRFLW_FLAG)) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 483 | continue; |
| 484 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 485 | pmu_write_register(cci_pmu, CCI_PMU_OVRFLW_FLAG, idx, |
| 486 | CCI_PMU_OVRFLW); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 487 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 488 | pmu_event_update(event); |
| 489 | pmu_event_set_period(event); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 490 | handled = IRQ_HANDLED; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 491 | } |
| 492 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 493 | |
| 494 | return IRQ_RETVAL(handled); |
| 495 | } |
| 496 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 497 | static int cci_pmu_get_hw(struct cci_pmu *cci_pmu) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 498 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 499 | int ret = pmu_request_irq(cci_pmu, pmu_handle_irq); |
| 500 | if (ret) { |
| 501 | pmu_free_irq(cci_pmu); |
| 502 | return ret; |
| 503 | } |
| 504 | return 0; |
| 505 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 506 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 507 | static void cci_pmu_put_hw(struct cci_pmu *cci_pmu) |
| 508 | { |
| 509 | pmu_free_irq(cci_pmu); |
| 510 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 511 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 512 | static void hw_perf_event_destroy(struct perf_event *event) |
| 513 | { |
| 514 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 515 | atomic_t *active_events = &cci_pmu->active_events; |
| 516 | struct mutex *reserve_mutex = &cci_pmu->reserve_mutex; |
| 517 | |
| 518 | if (atomic_dec_and_mutex_lock(active_events, reserve_mutex)) { |
| 519 | cci_pmu_put_hw(cci_pmu); |
| 520 | mutex_unlock(reserve_mutex); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 521 | } |
| 522 | } |
| 523 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 524 | static void cci_pmu_enable(struct pmu *pmu) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 525 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 526 | struct cci_pmu *cci_pmu = to_cci_pmu(pmu); |
| 527 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 528 | int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 529 | unsigned long flags; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 530 | u32 val; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 531 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 532 | if (!enabled) |
| 533 | return; |
| 534 | |
| 535 | raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 536 | |
| 537 | /* Enable all the PMU counters. */ |
| 538 | val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; |
| 539 | writel(val, cci_ctrl_base + CCI_PMCR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 540 | raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 541 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 542 | } |
| 543 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 544 | static void cci_pmu_disable(struct pmu *pmu) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 545 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 546 | struct cci_pmu *cci_pmu = to_cci_pmu(pmu); |
| 547 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 548 | unsigned long flags; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 549 | u32 val; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 550 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 551 | raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 552 | |
| 553 | /* Disable all the PMU counters. */ |
| 554 | val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; |
| 555 | writel(val, cci_ctrl_base + CCI_PMCR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 556 | raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 557 | } |
| 558 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 559 | /* |
| 560 | * Check if the idx represents a non-programmable counter. |
| 561 | * All the fixed event counters are mapped before the programmable |
| 562 | * counters. |
| 563 | */ |
| 564 | static bool pmu_fixed_hw_idx(struct cci_pmu *cci_pmu, int idx) |
| 565 | { |
| 566 | return (idx >= 0) && (idx < cci_pmu->model->fixed_hw_cntrs); |
| 567 | } |
| 568 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 569 | static void cci_pmu_start(struct perf_event *event, int pmu_flags) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 570 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 571 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 572 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
| 573 | struct hw_perf_event *hwc = &event->hw; |
| 574 | int idx = hwc->idx; |
| 575 | unsigned long flags; |
| 576 | |
| 577 | /* |
| 578 | * To handle interrupt latency, we always reprogram the period |
| 579 | * regardlesss of PERF_EF_RELOAD. |
| 580 | */ |
| 581 | if (pmu_flags & PERF_EF_RELOAD) |
| 582 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
| 583 | |
| 584 | hwc->state = 0; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 585 | |
| 586 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) { |
| 587 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 588 | return; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 589 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 590 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 591 | raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); |
| 592 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 593 | /* Configure the counter unless you are counting a fixed event */ |
| 594 | if (!pmu_fixed_hw_idx(cci_pmu, idx)) |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 595 | pmu_set_event(cci_pmu, idx, hwc->config_base); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 596 | |
| 597 | pmu_event_set_period(event); |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 598 | pmu_enable_counter(cci_pmu, idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 599 | |
| 600 | raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 601 | } |
| 602 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 603 | static void cci_pmu_stop(struct perf_event *event, int pmu_flags) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 604 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 605 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 606 | struct hw_perf_event *hwc = &event->hw; |
| 607 | int idx = hwc->idx; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 608 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 609 | if (hwc->state & PERF_HES_STOPPED) |
| 610 | return; |
| 611 | |
| 612 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 613 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 614 | return; |
| 615 | } |
| 616 | |
| 617 | /* |
| 618 | * We always reprogram the counter, so ignore PERF_EF_UPDATE. See |
| 619 | * cci_pmu_start() |
| 620 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 621 | pmu_disable_counter(cci_pmu, idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 622 | pmu_event_update(event); |
| 623 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 624 | } |
| 625 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 626 | static int cci_pmu_add(struct perf_event *event, int flags) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 627 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 628 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 629 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
| 630 | struct hw_perf_event *hwc = &event->hw; |
| 631 | int idx; |
| 632 | int err = 0; |
| 633 | |
| 634 | perf_pmu_disable(event->pmu); |
| 635 | |
| 636 | /* If we don't have a space for the counter then finish early. */ |
| 637 | idx = pmu_get_event_idx(hw_events, event); |
| 638 | if (idx < 0) { |
| 639 | err = idx; |
| 640 | goto out; |
| 641 | } |
| 642 | |
| 643 | event->hw.idx = idx; |
| 644 | hw_events->events[idx] = event; |
| 645 | |
| 646 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 647 | if (flags & PERF_EF_START) |
| 648 | cci_pmu_start(event, PERF_EF_RELOAD); |
| 649 | |
| 650 | /* Propagate our changes to the userspace mapping. */ |
| 651 | perf_event_update_userpage(event); |
| 652 | |
| 653 | out: |
| 654 | perf_pmu_enable(event->pmu); |
| 655 | return err; |
| 656 | } |
| 657 | |
| 658 | static void cci_pmu_del(struct perf_event *event, int flags) |
| 659 | { |
| 660 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 661 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
| 662 | struct hw_perf_event *hwc = &event->hw; |
| 663 | int idx = hwc->idx; |
| 664 | |
| 665 | cci_pmu_stop(event, PERF_EF_UPDATE); |
| 666 | hw_events->events[idx] = NULL; |
| 667 | clear_bit(idx, hw_events->used_mask); |
| 668 | |
| 669 | perf_event_update_userpage(event); |
| 670 | } |
| 671 | |
| 672 | static int |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 673 | validate_event(struct pmu *cci_pmu, |
| 674 | struct cci_pmu_hw_events *hw_events, |
| 675 | struct perf_event *event) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 676 | { |
| 677 | if (is_software_event(event)) |
| 678 | return 1; |
| 679 | |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 680 | /* |
| 681 | * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The |
| 682 | * core perf code won't check that the pmu->ctx == leader->ctx |
| 683 | * until after pmu->event_init(event). |
| 684 | */ |
| 685 | if (event->pmu != cci_pmu) |
| 686 | return 0; |
| 687 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 688 | if (event->state < PERF_EVENT_STATE_OFF) |
| 689 | return 1; |
| 690 | |
| 691 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) |
| 692 | return 1; |
| 693 | |
| 694 | return pmu_get_event_idx(hw_events, event) >= 0; |
| 695 | } |
| 696 | |
| 697 | static int |
| 698 | validate_group(struct perf_event *event) |
| 699 | { |
| 700 | struct perf_event *sibling, *leader = event->group_leader; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 701 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 702 | unsigned long mask[BITS_TO_LONGS(cci_pmu->num_cntrs)]; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 703 | struct cci_pmu_hw_events fake_pmu = { |
| 704 | /* |
| 705 | * Initialise the fake PMU. We only need to populate the |
| 706 | * used_mask for the purposes of validation. |
| 707 | */ |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 708 | .used_mask = mask, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 709 | }; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 710 | memset(mask, 0, BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long)); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 711 | |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 712 | if (!validate_event(event->pmu, &fake_pmu, leader)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 713 | return -EINVAL; |
| 714 | |
| 715 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 716 | if (!validate_event(event->pmu, &fake_pmu, sibling)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 717 | return -EINVAL; |
| 718 | } |
| 719 | |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 720 | if (!validate_event(event->pmu, &fake_pmu, event)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 721 | return -EINVAL; |
| 722 | |
| 723 | return 0; |
| 724 | } |
| 725 | |
| 726 | static int |
| 727 | __hw_perf_event_init(struct perf_event *event) |
| 728 | { |
| 729 | struct hw_perf_event *hwc = &event->hw; |
| 730 | int mapping; |
| 731 | |
| 732 | mapping = pmu_map_event(event); |
| 733 | |
| 734 | if (mapping < 0) { |
| 735 | pr_debug("event %x:%llx not supported\n", event->attr.type, |
| 736 | event->attr.config); |
| 737 | return mapping; |
| 738 | } |
| 739 | |
| 740 | /* |
| 741 | * We don't assign an index until we actually place the event onto |
| 742 | * hardware. Use -1 to signify that we haven't decided where to put it |
| 743 | * yet. |
| 744 | */ |
| 745 | hwc->idx = -1; |
| 746 | hwc->config_base = 0; |
| 747 | hwc->config = 0; |
| 748 | hwc->event_base = 0; |
| 749 | |
| 750 | /* |
| 751 | * Store the event encoding into the config_base field. |
| 752 | */ |
| 753 | hwc->config_base |= (unsigned long)mapping; |
| 754 | |
| 755 | /* |
| 756 | * Limit the sample_period to half of the counter width. That way, the |
| 757 | * new counter value is far less likely to overtake the previous one |
| 758 | * unless you have some serious IRQ latency issues. |
| 759 | */ |
| 760 | hwc->sample_period = CCI_PMU_CNTR_MASK >> 1; |
| 761 | hwc->last_period = hwc->sample_period; |
| 762 | local64_set(&hwc->period_left, hwc->sample_period); |
| 763 | |
| 764 | if (event->group_leader != event) { |
| 765 | if (validate_group(event) != 0) |
| 766 | return -EINVAL; |
| 767 | } |
| 768 | |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | static int cci_pmu_event_init(struct perf_event *event) |
| 773 | { |
| 774 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 775 | atomic_t *active_events = &cci_pmu->active_events; |
| 776 | int err = 0; |
| 777 | int cpu; |
| 778 | |
| 779 | if (event->attr.type != event->pmu->type) |
| 780 | return -ENOENT; |
| 781 | |
| 782 | /* Shared by all CPUs, no meaningful state to sample */ |
| 783 | if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) |
| 784 | return -EOPNOTSUPP; |
| 785 | |
| 786 | /* We have no filtering of any kind */ |
| 787 | if (event->attr.exclude_user || |
| 788 | event->attr.exclude_kernel || |
| 789 | event->attr.exclude_hv || |
| 790 | event->attr.exclude_idle || |
| 791 | event->attr.exclude_host || |
| 792 | event->attr.exclude_guest) |
| 793 | return -EINVAL; |
| 794 | |
| 795 | /* |
| 796 | * Following the example set by other "uncore" PMUs, we accept any CPU |
| 797 | * and rewrite its affinity dynamically rather than having perf core |
| 798 | * handle cpu == -1 and pid == -1 for this case. |
| 799 | * |
| 800 | * The perf core will pin online CPUs for the duration of this call and |
| 801 | * the event being installed into its context, so the PMU's CPU can't |
| 802 | * change under our feet. |
| 803 | */ |
| 804 | cpu = cpumask_first(&cci_pmu->cpus); |
| 805 | if (event->cpu < 0 || cpu < 0) |
| 806 | return -EINVAL; |
| 807 | event->cpu = cpu; |
| 808 | |
| 809 | event->destroy = hw_perf_event_destroy; |
| 810 | if (!atomic_inc_not_zero(active_events)) { |
| 811 | mutex_lock(&cci_pmu->reserve_mutex); |
| 812 | if (atomic_read(active_events) == 0) |
| 813 | err = cci_pmu_get_hw(cci_pmu); |
| 814 | if (!err) |
| 815 | atomic_inc(active_events); |
| 816 | mutex_unlock(&cci_pmu->reserve_mutex); |
| 817 | } |
| 818 | if (err) |
| 819 | return err; |
| 820 | |
| 821 | err = __hw_perf_event_init(event); |
| 822 | if (err) |
| 823 | hw_perf_event_destroy(event); |
| 824 | |
| 825 | return err; |
| 826 | } |
| 827 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 828 | static ssize_t pmu_cpumask_attr_show(struct device *dev, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 829 | struct device_attribute *attr, char *buf) |
| 830 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 831 | struct dev_ext_attribute *eattr = container_of(attr, |
| 832 | struct dev_ext_attribute, attr); |
| 833 | struct cci_pmu *cci_pmu = eattr->var; |
| 834 | |
Tejun Heo | 660e5ec | 2015-02-13 14:37:20 -0800 | [diff] [blame] | 835 | int n = scnprintf(buf, PAGE_SIZE - 1, "%*pbl", |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 836 | cpumask_pr_args(&cci_pmu->cpus)); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 837 | buf[n++] = '\n'; |
| 838 | buf[n] = '\0'; |
| 839 | return n; |
| 840 | } |
| 841 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 842 | static struct dev_ext_attribute pmu_cpumask_attr = { |
| 843 | __ATTR(cpumask, S_IRUGO, pmu_cpumask_attr_show, NULL), |
| 844 | NULL, /* Populated in cci_pmu_init */ |
| 845 | }; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 846 | |
| 847 | static struct attribute *pmu_attrs[] = { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 848 | &pmu_cpumask_attr.attr.attr, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 849 | NULL, |
| 850 | }; |
| 851 | |
| 852 | static struct attribute_group pmu_attr_group = { |
| 853 | .attrs = pmu_attrs, |
| 854 | }; |
| 855 | |
| 856 | static const struct attribute_group *pmu_attr_groups[] = { |
| 857 | &pmu_attr_group, |
| 858 | NULL |
| 859 | }; |
| 860 | |
| 861 | static int cci_pmu_init(struct cci_pmu *cci_pmu, struct platform_device *pdev) |
| 862 | { |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 863 | char *name = cci_pmu->model->name; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 864 | u32 num_cntrs; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 865 | |
| 866 | pmu_cpumask_attr.var = cci_pmu; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 867 | cci_pmu->pmu = (struct pmu) { |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 868 | .name = cci_pmu->model->name, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 869 | .task_ctx_nr = perf_invalid_context, |
| 870 | .pmu_enable = cci_pmu_enable, |
| 871 | .pmu_disable = cci_pmu_disable, |
| 872 | .event_init = cci_pmu_event_init, |
| 873 | .add = cci_pmu_add, |
| 874 | .del = cci_pmu_del, |
| 875 | .start = cci_pmu_start, |
| 876 | .stop = cci_pmu_stop, |
| 877 | .read = pmu_read, |
| 878 | .attr_groups = pmu_attr_groups, |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 879 | }; |
| 880 | |
| 881 | cci_pmu->plat_device = pdev; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 882 | num_cntrs = pmu_get_max_counters(); |
| 883 | if (num_cntrs > cci_pmu->model->num_hw_cntrs) { |
| 884 | dev_warn(&pdev->dev, |
| 885 | "PMU implements more counters(%d) than supported by" |
| 886 | " the model(%d), truncated.", |
| 887 | num_cntrs, cci_pmu->model->num_hw_cntrs); |
| 888 | num_cntrs = cci_pmu->model->num_hw_cntrs; |
| 889 | } |
| 890 | cci_pmu->num_cntrs = num_cntrs + cci_pmu->model->fixed_hw_cntrs; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 891 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 892 | return perf_pmu_register(&cci_pmu->pmu, name, -1); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 893 | } |
| 894 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 895 | static int cci_pmu_cpu_notifier(struct notifier_block *self, |
| 896 | unsigned long action, void *hcpu) |
| 897 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 898 | struct cci_pmu *cci_pmu = container_of(self, |
| 899 | struct cci_pmu, cpu_nb); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 900 | unsigned int cpu = (long)hcpu; |
| 901 | unsigned int target; |
| 902 | |
| 903 | switch (action & ~CPU_TASKS_FROZEN) { |
| 904 | case CPU_DOWN_PREPARE: |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 905 | if (!cpumask_test_and_clear_cpu(cpu, &cci_pmu->cpus)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 906 | break; |
| 907 | target = cpumask_any_but(cpu_online_mask, cpu); |
| 908 | if (target < 0) // UP, last CPU |
| 909 | break; |
| 910 | /* |
| 911 | * TODO: migrate context once core races on event->ctx have |
| 912 | * been fixed. |
| 913 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 914 | cpumask_set_cpu(target, &cci_pmu->cpus); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 915 | default: |
| 916 | break; |
| 917 | } |
| 918 | |
| 919 | return NOTIFY_OK; |
| 920 | } |
| 921 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 922 | static struct cci_pmu_model cci_pmu_models[] = { |
| 923 | [CCI_REV_R0] = { |
| 924 | .name = "CCI_400", |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 925 | .fixed_hw_cntrs = 1, /* Cycle counter */ |
| 926 | .num_hw_cntrs = 4, |
| 927 | .cntr_size = SZ_4K, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 928 | .event_ranges = { |
| 929 | [CCI_IF_SLAVE] = { |
| 930 | CCI_REV_R0_SLAVE_PORT_MIN_EV, |
| 931 | CCI_REV_R0_SLAVE_PORT_MAX_EV, |
| 932 | }, |
| 933 | [CCI_IF_MASTER] = { |
| 934 | CCI_REV_R0_MASTER_PORT_MIN_EV, |
| 935 | CCI_REV_R0_MASTER_PORT_MAX_EV, |
| 936 | }, |
| 937 | }, |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 938 | .validate_hw_event = cci400_validate_hw_event, |
| 939 | .get_event_idx = cci400_get_event_idx, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 940 | }, |
| 941 | [CCI_REV_R1] = { |
| 942 | .name = "CCI_400_r1", |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 943 | .fixed_hw_cntrs = 1, /* Cycle counter */ |
| 944 | .num_hw_cntrs = 4, |
| 945 | .cntr_size = SZ_4K, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 946 | .event_ranges = { |
| 947 | [CCI_IF_SLAVE] = { |
| 948 | CCI_REV_R1_SLAVE_PORT_MIN_EV, |
| 949 | CCI_REV_R1_SLAVE_PORT_MAX_EV, |
| 950 | }, |
| 951 | [CCI_IF_MASTER] = { |
| 952 | CCI_REV_R1_MASTER_PORT_MIN_EV, |
| 953 | CCI_REV_R1_MASTER_PORT_MAX_EV, |
| 954 | }, |
| 955 | }, |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame^] | 956 | .validate_hw_event = cci400_validate_hw_event, |
| 957 | .get_event_idx = cci400_get_event_idx, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 958 | }, |
| 959 | }; |
| 960 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 961 | static const struct of_device_id arm_cci_pmu_matches[] = { |
| 962 | { |
| 963 | .compatible = "arm,cci-400-pmu", |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 964 | .data = NULL, |
| 965 | }, |
| 966 | { |
| 967 | .compatible = "arm,cci-400-pmu,r0", |
| 968 | .data = &cci_pmu_models[CCI_REV_R0], |
| 969 | }, |
| 970 | { |
| 971 | .compatible = "arm,cci-400-pmu,r1", |
| 972 | .data = &cci_pmu_models[CCI_REV_R1], |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 973 | }, |
| 974 | {}, |
| 975 | }; |
| 976 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 977 | static inline const struct cci_pmu_model *get_cci_model(struct platform_device *pdev) |
| 978 | { |
| 979 | const struct of_device_id *match = of_match_node(arm_cci_pmu_matches, |
| 980 | pdev->dev.of_node); |
| 981 | if (!match) |
| 982 | return NULL; |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 983 | if (match->data) |
| 984 | return match->data; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 985 | |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 986 | dev_warn(&pdev->dev, "DEPRECATED compatible property," |
| 987 | "requires secure access to CCI registers"); |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 988 | return probe_cci_model(pdev); |
| 989 | } |
| 990 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 991 | static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs) |
| 992 | { |
| 993 | int i; |
| 994 | |
| 995 | for (i = 0; i < nr_irqs; i++) |
| 996 | if (irq == irqs[i]) |
| 997 | return true; |
| 998 | |
| 999 | return false; |
| 1000 | } |
| 1001 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1002 | static struct cci_pmu *cci_pmu_alloc(struct platform_device *pdev) |
| 1003 | { |
| 1004 | struct cci_pmu *cci_pmu; |
| 1005 | const struct cci_pmu_model *model; |
| 1006 | |
| 1007 | /* |
| 1008 | * All allocations are devm_* hence we don't have to free |
| 1009 | * them explicitly on an error, as it would end up in driver |
| 1010 | * detach. |
| 1011 | */ |
| 1012 | model = get_cci_model(pdev); |
| 1013 | if (!model) { |
| 1014 | dev_warn(&pdev->dev, "CCI PMU version not supported\n"); |
| 1015 | return ERR_PTR(-ENODEV); |
| 1016 | } |
| 1017 | |
| 1018 | cci_pmu = devm_kzalloc(&pdev->dev, sizeof(*cci_pmu), GFP_KERNEL); |
| 1019 | if (!cci_pmu) |
| 1020 | return ERR_PTR(-ENOMEM); |
| 1021 | |
| 1022 | cci_pmu->model = model; |
| 1023 | cci_pmu->irqs = devm_kcalloc(&pdev->dev, CCI_PMU_MAX_HW_CNTRS(model), |
| 1024 | sizeof(*cci_pmu->irqs), GFP_KERNEL); |
| 1025 | if (!cci_pmu->irqs) |
| 1026 | return ERR_PTR(-ENOMEM); |
| 1027 | cci_pmu->hw_events.events = devm_kcalloc(&pdev->dev, |
| 1028 | CCI_PMU_MAX_HW_CNTRS(model), |
| 1029 | sizeof(*cci_pmu->hw_events.events), |
| 1030 | GFP_KERNEL); |
| 1031 | if (!cci_pmu->hw_events.events) |
| 1032 | return ERR_PTR(-ENOMEM); |
| 1033 | cci_pmu->hw_events.used_mask = devm_kcalloc(&pdev->dev, |
| 1034 | BITS_TO_LONGS(CCI_PMU_MAX_HW_CNTRS(model)), |
| 1035 | sizeof(*cci_pmu->hw_events.used_mask), |
| 1036 | GFP_KERNEL); |
| 1037 | if (!cci_pmu->hw_events.used_mask) |
| 1038 | return ERR_PTR(-ENOMEM); |
| 1039 | |
| 1040 | return cci_pmu; |
| 1041 | } |
| 1042 | |
| 1043 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1044 | static int cci_pmu_probe(struct platform_device *pdev) |
| 1045 | { |
| 1046 | struct resource *res; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1047 | struct cci_pmu *cci_pmu; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1048 | int i, ret, irq; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1049 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1050 | cci_pmu = cci_pmu_alloc(pdev); |
| 1051 | if (IS_ERR(cci_pmu)) |
| 1052 | return PTR_ERR(cci_pmu); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1053 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1054 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1055 | cci_pmu->base = devm_ioremap_resource(&pdev->dev, res); |
| 1056 | if (IS_ERR(cci_pmu->base)) |
Wei Yongjun | fee4f2c | 2013-09-22 06:04:23 +0100 | [diff] [blame] | 1057 | return -ENOMEM; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1058 | |
| 1059 | /* |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1060 | * CCI PMU has one overflow interrupt per counter; but some may be tied |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1061 | * together to a common interrupt. |
| 1062 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1063 | cci_pmu->nr_irqs = 0; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1064 | for (i = 0; i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model); i++) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1065 | irq = platform_get_irq(pdev, i); |
| 1066 | if (irq < 0) |
| 1067 | break; |
| 1068 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1069 | if (is_duplicate_irq(irq, cci_pmu->irqs, cci_pmu->nr_irqs)) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1070 | continue; |
| 1071 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1072 | cci_pmu->irqs[cci_pmu->nr_irqs++] = irq; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1073 | } |
| 1074 | |
| 1075 | /* |
| 1076 | * Ensure that the device tree has as many interrupts as the number |
| 1077 | * of counters. |
| 1078 | */ |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1079 | if (i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1080 | dev_warn(&pdev->dev, "In-correct number of interrupts: %d, should be %d\n", |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1081 | i, CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)); |
Wei Yongjun | fee4f2c | 2013-09-22 06:04:23 +0100 | [diff] [blame] | 1082 | return -EINVAL; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1083 | } |
| 1084 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1085 | raw_spin_lock_init(&cci_pmu->hw_events.pmu_lock); |
| 1086 | mutex_init(&cci_pmu->reserve_mutex); |
| 1087 | atomic_set(&cci_pmu->active_events, 0); |
| 1088 | cpumask_set_cpu(smp_processor_id(), &cci_pmu->cpus); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1089 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1090 | cci_pmu->cpu_nb = (struct notifier_block) { |
| 1091 | .notifier_call = cci_pmu_cpu_notifier, |
| 1092 | /* |
| 1093 | * to migrate uncore events, our notifier should be executed |
| 1094 | * before perf core's notifier. |
| 1095 | */ |
| 1096 | .priority = CPU_PRI_PERF + 1, |
| 1097 | }; |
| 1098 | |
| 1099 | ret = register_cpu_notifier(&cci_pmu->cpu_nb); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1100 | if (ret) |
| 1101 | return ret; |
| 1102 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1103 | ret = cci_pmu_init(cci_pmu, pdev); |
| 1104 | if (ret) { |
| 1105 | unregister_cpu_notifier(&cci_pmu->cpu_nb); |
Wei Yongjun | fee4f2c | 2013-09-22 06:04:23 +0100 | [diff] [blame] | 1106 | return ret; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1107 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1108 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1109 | pr_info("ARM %s PMU driver probed", cci_pmu->model->name); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1110 | return 0; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1111 | } |
| 1112 | |
| 1113 | static int cci_platform_probe(struct platform_device *pdev) |
| 1114 | { |
| 1115 | if (!cci_probed()) |
| 1116 | return -ENODEV; |
| 1117 | |
| 1118 | return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); |
| 1119 | } |
| 1120 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1121 | static struct platform_driver cci_pmu_driver = { |
| 1122 | .driver = { |
| 1123 | .name = DRIVER_NAME_PMU, |
| 1124 | .of_match_table = arm_cci_pmu_matches, |
| 1125 | }, |
| 1126 | .probe = cci_pmu_probe, |
| 1127 | }; |
| 1128 | |
| 1129 | static struct platform_driver cci_platform_driver = { |
| 1130 | .driver = { |
| 1131 | .name = DRIVER_NAME, |
| 1132 | .of_match_table = arm_cci_matches, |
| 1133 | }, |
| 1134 | .probe = cci_platform_probe, |
| 1135 | }; |
| 1136 | |
| 1137 | static int __init cci_platform_init(void) |
| 1138 | { |
| 1139 | int ret; |
| 1140 | |
| 1141 | ret = platform_driver_register(&cci_pmu_driver); |
| 1142 | if (ret) |
| 1143 | return ret; |
| 1144 | |
| 1145 | return platform_driver_register(&cci_platform_driver); |
| 1146 | } |
| 1147 | |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 1148 | #else /* !CONFIG_ARM_CCI400_PMU */ |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1149 | |
| 1150 | static int __init cci_platform_init(void) |
| 1151 | { |
| 1152 | return 0; |
| 1153 | } |
| 1154 | |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 1155 | #endif /* CONFIG_ARM_CCI400_PMU */ |
| 1156 | |
| 1157 | #ifdef CONFIG_ARM_CCI400_PORT_CTRL |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1158 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1159 | #define CCI_PORT_CTRL 0x0 |
| 1160 | #define CCI_CTRL_STATUS 0xc |
| 1161 | |
| 1162 | #define CCI_ENABLE_SNOOP_REQ 0x1 |
| 1163 | #define CCI_ENABLE_DVM_REQ 0x2 |
| 1164 | #define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ) |
| 1165 | |
| 1166 | enum cci_ace_port_type { |
| 1167 | ACE_INVALID_PORT = 0x0, |
| 1168 | ACE_PORT, |
| 1169 | ACE_LITE_PORT, |
| 1170 | }; |
| 1171 | |
| 1172 | struct cci_ace_port { |
| 1173 | void __iomem *base; |
| 1174 | unsigned long phys; |
| 1175 | enum cci_ace_port_type type; |
| 1176 | struct device_node *dn; |
| 1177 | }; |
| 1178 | |
| 1179 | static struct cci_ace_port *ports; |
| 1180 | static unsigned int nb_cci_ports; |
| 1181 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1182 | struct cpu_port { |
| 1183 | u64 mpidr; |
| 1184 | u32 port; |
| 1185 | }; |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1186 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1187 | /* |
| 1188 | * Use the port MSB as valid flag, shift can be made dynamic |
| 1189 | * by computing number of bits required for port indexes. |
| 1190 | * Code disabling CCI cpu ports runs with D-cache invalidated |
| 1191 | * and SCTLR bit clear so data accesses must be kept to a minimum |
| 1192 | * to improve performance; for now shift is left static to |
| 1193 | * avoid one more data access while disabling the CCI port. |
| 1194 | */ |
| 1195 | #define PORT_VALID_SHIFT 31 |
| 1196 | #define PORT_VALID (0x1 << PORT_VALID_SHIFT) |
| 1197 | |
| 1198 | static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr) |
| 1199 | { |
| 1200 | port->port = PORT_VALID | index; |
| 1201 | port->mpidr = mpidr; |
| 1202 | } |
| 1203 | |
| 1204 | static inline bool cpu_port_is_valid(struct cpu_port *port) |
| 1205 | { |
| 1206 | return !!(port->port & PORT_VALID); |
| 1207 | } |
| 1208 | |
| 1209 | static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr) |
| 1210 | { |
| 1211 | return port->mpidr == (mpidr & MPIDR_HWID_BITMASK); |
| 1212 | } |
| 1213 | |
| 1214 | static struct cpu_port cpu_port[NR_CPUS]; |
| 1215 | |
| 1216 | /** |
| 1217 | * __cci_ace_get_port - Function to retrieve the port index connected to |
| 1218 | * a cpu or device. |
| 1219 | * |
| 1220 | * @dn: device node of the device to look-up |
| 1221 | * @type: port type |
| 1222 | * |
| 1223 | * Return value: |
| 1224 | * - CCI port index if success |
| 1225 | * - -ENODEV if failure |
| 1226 | */ |
| 1227 | static int __cci_ace_get_port(struct device_node *dn, int type) |
| 1228 | { |
| 1229 | int i; |
| 1230 | bool ace_match; |
| 1231 | struct device_node *cci_portn; |
| 1232 | |
| 1233 | cci_portn = of_parse_phandle(dn, "cci-control-port", 0); |
| 1234 | for (i = 0; i < nb_cci_ports; i++) { |
| 1235 | ace_match = ports[i].type == type; |
| 1236 | if (ace_match && cci_portn == ports[i].dn) |
| 1237 | return i; |
| 1238 | } |
| 1239 | return -ENODEV; |
| 1240 | } |
| 1241 | |
| 1242 | int cci_ace_get_port(struct device_node *dn) |
| 1243 | { |
| 1244 | return __cci_ace_get_port(dn, ACE_LITE_PORT); |
| 1245 | } |
| 1246 | EXPORT_SYMBOL_GPL(cci_ace_get_port); |
| 1247 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1248 | static void cci_ace_init_ports(void) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1249 | { |
Sudeep KarkadaNagesha | 78b4d6e | 2013-06-17 14:51:48 +0100 | [diff] [blame] | 1250 | int port, cpu; |
| 1251 | struct device_node *cpun; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1252 | |
| 1253 | /* |
| 1254 | * Port index look-up speeds up the function disabling ports by CPU, |
| 1255 | * since the logical to port index mapping is done once and does |
| 1256 | * not change after system boot. |
| 1257 | * The stashed index array is initialized for all possible CPUs |
| 1258 | * at probe time. |
| 1259 | */ |
Sudeep KarkadaNagesha | 78b4d6e | 2013-06-17 14:51:48 +0100 | [diff] [blame] | 1260 | for_each_possible_cpu(cpu) { |
| 1261 | /* too early to use cpu->of_node */ |
| 1262 | cpun = of_get_cpu_node(cpu, NULL); |
| 1263 | |
| 1264 | if (WARN(!cpun, "Missing cpu device node\n")) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1265 | continue; |
| 1266 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1267 | port = __cci_ace_get_port(cpun, ACE_PORT); |
| 1268 | if (port < 0) |
| 1269 | continue; |
| 1270 | |
| 1271 | init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu)); |
| 1272 | } |
| 1273 | |
| 1274 | for_each_possible_cpu(cpu) { |
| 1275 | WARN(!cpu_port_is_valid(&cpu_port[cpu]), |
| 1276 | "CPU %u does not have an associated CCI port\n", |
| 1277 | cpu); |
| 1278 | } |
| 1279 | } |
| 1280 | /* |
| 1281 | * Functions to enable/disable a CCI interconnect slave port |
| 1282 | * |
| 1283 | * They are called by low-level power management code to disable slave |
| 1284 | * interfaces snoops and DVM broadcast. |
| 1285 | * Since they may execute with cache data allocation disabled and |
| 1286 | * after the caches have been cleaned and invalidated the functions provide |
| 1287 | * no explicit locking since they may run with D-cache disabled, so normal |
| 1288 | * cacheable kernel locks based on ldrex/strex may not work. |
| 1289 | * Locking has to be provided by BSP implementations to ensure proper |
| 1290 | * operations. |
| 1291 | */ |
| 1292 | |
| 1293 | /** |
| 1294 | * cci_port_control() - function to control a CCI port |
| 1295 | * |
| 1296 | * @port: index of the port to setup |
| 1297 | * @enable: if true enables the port, if false disables it |
| 1298 | */ |
| 1299 | static void notrace cci_port_control(unsigned int port, bool enable) |
| 1300 | { |
| 1301 | void __iomem *base = ports[port].base; |
| 1302 | |
| 1303 | writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL); |
| 1304 | /* |
| 1305 | * This function is called from power down procedures |
| 1306 | * and must not execute any instruction that might |
| 1307 | * cause the processor to be put in a quiescent state |
| 1308 | * (eg wfi). Hence, cpu_relax() can not be added to this |
| 1309 | * read loop to optimize power, since it might hide possibly |
| 1310 | * disruptive operations. |
| 1311 | */ |
| 1312 | while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1) |
| 1313 | ; |
| 1314 | } |
| 1315 | |
| 1316 | /** |
| 1317 | * cci_disable_port_by_cpu() - function to disable a CCI port by CPU |
| 1318 | * reference |
| 1319 | * |
| 1320 | * @mpidr: mpidr of the CPU whose CCI port should be disabled |
| 1321 | * |
| 1322 | * Disabling a CCI port for a CPU implies disabling the CCI port |
| 1323 | * controlling that CPU cluster. Code disabling CPU CCI ports |
| 1324 | * must make sure that the CPU running the code is the last active CPU |
| 1325 | * in the cluster ie all other CPUs are quiescent in a low power state. |
| 1326 | * |
| 1327 | * Return: |
| 1328 | * 0 on success |
| 1329 | * -ENODEV on port look-up failure |
| 1330 | */ |
| 1331 | int notrace cci_disable_port_by_cpu(u64 mpidr) |
| 1332 | { |
| 1333 | int cpu; |
| 1334 | bool is_valid; |
| 1335 | for (cpu = 0; cpu < nr_cpu_ids; cpu++) { |
| 1336 | is_valid = cpu_port_is_valid(&cpu_port[cpu]); |
| 1337 | if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) { |
| 1338 | cci_port_control(cpu_port[cpu].port, false); |
| 1339 | return 0; |
| 1340 | } |
| 1341 | } |
| 1342 | return -ENODEV; |
| 1343 | } |
| 1344 | EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu); |
| 1345 | |
| 1346 | /** |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1347 | * cci_enable_port_for_self() - enable a CCI port for calling CPU |
| 1348 | * |
| 1349 | * Enabling a CCI port for the calling CPU implies enabling the CCI |
| 1350 | * port controlling that CPU's cluster. Caller must make sure that the |
| 1351 | * CPU running the code is the first active CPU in the cluster and all |
| 1352 | * other CPUs are quiescent in a low power state or waiting for this CPU |
| 1353 | * to complete the CCI initialization. |
| 1354 | * |
| 1355 | * Because this is called when the MMU is still off and with no stack, |
| 1356 | * the code must be position independent and ideally rely on callee |
| 1357 | * clobbered registers only. To achieve this we must code this function |
| 1358 | * entirely in assembler. |
| 1359 | * |
| 1360 | * On success this returns with the proper CCI port enabled. In case of |
| 1361 | * any failure this never returns as the inability to enable the CCI is |
| 1362 | * fatal and there is no possible recovery at this stage. |
| 1363 | */ |
| 1364 | asmlinkage void __naked cci_enable_port_for_self(void) |
| 1365 | { |
| 1366 | asm volatile ("\n" |
Arnd Bergmann | f490249 | 2013-06-03 15:15:36 +0200 | [diff] [blame] | 1367 | " .arch armv7-a\n" |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1368 | " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n" |
| 1369 | " and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n" |
| 1370 | " adr r1, 5f \n" |
| 1371 | " ldr r2, [r1] \n" |
| 1372 | " add r1, r1, r2 @ &cpu_port \n" |
| 1373 | " add ip, r1, %[sizeof_cpu_port] \n" |
| 1374 | |
| 1375 | /* Loop over the cpu_port array looking for a matching MPIDR */ |
| 1376 | "1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n" |
| 1377 | " cmp r2, r0 @ compare MPIDR \n" |
| 1378 | " bne 2f \n" |
| 1379 | |
| 1380 | /* Found a match, now test port validity */ |
| 1381 | " ldr r3, [r1, %[offsetof_cpu_port_port]] \n" |
| 1382 | " tst r3, #"__stringify(PORT_VALID)" \n" |
| 1383 | " bne 3f \n" |
| 1384 | |
| 1385 | /* no match, loop with the next cpu_port entry */ |
| 1386 | "2: add r1, r1, %[sizeof_struct_cpu_port] \n" |
| 1387 | " cmp r1, ip @ done? \n" |
| 1388 | " blo 1b \n" |
| 1389 | |
| 1390 | /* CCI port not found -- cheaply try to stall this CPU */ |
| 1391 | "cci_port_not_found: \n" |
| 1392 | " wfi \n" |
| 1393 | " wfe \n" |
| 1394 | " b cci_port_not_found \n" |
| 1395 | |
| 1396 | /* Use matched port index to look up the corresponding ports entry */ |
| 1397 | "3: bic r3, r3, #"__stringify(PORT_VALID)" \n" |
| 1398 | " adr r0, 6f \n" |
| 1399 | " ldmia r0, {r1, r2} \n" |
| 1400 | " sub r1, r1, r0 @ virt - phys \n" |
| 1401 | " ldr r0, [r0, r2] @ *(&ports) \n" |
| 1402 | " mov r2, %[sizeof_struct_ace_port] \n" |
| 1403 | " mla r0, r2, r3, r0 @ &ports[index] \n" |
| 1404 | " sub r0, r0, r1 @ virt_to_phys() \n" |
| 1405 | |
| 1406 | /* Enable the CCI port */ |
| 1407 | " ldr r0, [r0, %[offsetof_port_phys]] \n" |
Victor Kamensky | fdb07ae | 2013-10-15 21:50:34 -0700 | [diff] [blame] | 1408 | " mov r3, %[cci_enable_req]\n" |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1409 | " str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n" |
| 1410 | |
| 1411 | /* poll the status reg for completion */ |
| 1412 | " adr r1, 7f \n" |
| 1413 | " ldr r0, [r1] \n" |
| 1414 | " ldr r0, [r0, r1] @ cci_ctrl_base \n" |
| 1415 | "4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n" |
Victor Kamensky | fdb07ae | 2013-10-15 21:50:34 -0700 | [diff] [blame] | 1416 | " tst r1, %[cci_control_status_bits] \n" |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1417 | " bne 4b \n" |
| 1418 | |
| 1419 | " mov r0, #0 \n" |
| 1420 | " bx lr \n" |
| 1421 | |
| 1422 | " .align 2 \n" |
| 1423 | "5: .word cpu_port - . \n" |
| 1424 | "6: .word . \n" |
| 1425 | " .word ports - 6b \n" |
| 1426 | "7: .word cci_ctrl_phys - . \n" |
| 1427 | : : |
| 1428 | [sizeof_cpu_port] "i" (sizeof(cpu_port)), |
Victor Kamensky | fdb07ae | 2013-10-15 21:50:34 -0700 | [diff] [blame] | 1429 | [cci_enable_req] "i" cpu_to_le32(CCI_ENABLE_REQ), |
| 1430 | [cci_control_status_bits] "i" cpu_to_le32(1), |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1431 | #ifndef __ARMEB__ |
| 1432 | [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)), |
| 1433 | #else |
| 1434 | [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4), |
| 1435 | #endif |
| 1436 | [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)), |
| 1437 | [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)), |
| 1438 | [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)), |
| 1439 | [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) ); |
| 1440 | |
| 1441 | unreachable(); |
| 1442 | } |
| 1443 | |
| 1444 | /** |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1445 | * __cci_control_port_by_device() - function to control a CCI port by device |
| 1446 | * reference |
| 1447 | * |
| 1448 | * @dn: device node pointer of the device whose CCI port should be |
| 1449 | * controlled |
| 1450 | * @enable: if true enables the port, if false disables it |
| 1451 | * |
| 1452 | * Return: |
| 1453 | * 0 on success |
| 1454 | * -ENODEV on port look-up failure |
| 1455 | */ |
| 1456 | int notrace __cci_control_port_by_device(struct device_node *dn, bool enable) |
| 1457 | { |
| 1458 | int port; |
| 1459 | |
| 1460 | if (!dn) |
| 1461 | return -ENODEV; |
| 1462 | |
| 1463 | port = __cci_ace_get_port(dn, ACE_LITE_PORT); |
| 1464 | if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n", |
| 1465 | dn->full_name)) |
| 1466 | return -ENODEV; |
| 1467 | cci_port_control(port, enable); |
| 1468 | return 0; |
| 1469 | } |
| 1470 | EXPORT_SYMBOL_GPL(__cci_control_port_by_device); |
| 1471 | |
| 1472 | /** |
| 1473 | * __cci_control_port_by_index() - function to control a CCI port by port index |
| 1474 | * |
| 1475 | * @port: port index previously retrieved with cci_ace_get_port() |
| 1476 | * @enable: if true enables the port, if false disables it |
| 1477 | * |
| 1478 | * Return: |
| 1479 | * 0 on success |
| 1480 | * -ENODEV on port index out of range |
| 1481 | * -EPERM if operation carried out on an ACE PORT |
| 1482 | */ |
| 1483 | int notrace __cci_control_port_by_index(u32 port, bool enable) |
| 1484 | { |
| 1485 | if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT) |
| 1486 | return -ENODEV; |
| 1487 | /* |
| 1488 | * CCI control for ports connected to CPUS is extremely fragile |
| 1489 | * and must be made to go through a specific and controlled |
| 1490 | * interface (ie cci_disable_port_by_cpu(); control by general purpose |
| 1491 | * indexing is therefore disabled for ACE ports. |
| 1492 | */ |
| 1493 | if (ports[port].type == ACE_PORT) |
| 1494 | return -EPERM; |
| 1495 | |
| 1496 | cci_port_control(port, enable); |
| 1497 | return 0; |
| 1498 | } |
| 1499 | EXPORT_SYMBOL_GPL(__cci_control_port_by_index); |
| 1500 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1501 | static const struct of_device_id arm_cci_ctrl_if_matches[] = { |
| 1502 | {.compatible = "arm,cci-400-ctrl-if", }, |
| 1503 | {}, |
| 1504 | }; |
| 1505 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1506 | static int cci_probe_ports(struct device_node *np) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1507 | { |
| 1508 | struct cci_nb_ports const *cci_config; |
| 1509 | int ret, i, nb_ace = 0, nb_ace_lite = 0; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1510 | struct device_node *cp; |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1511 | struct resource res; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1512 | const char *match_str; |
| 1513 | bool is_ace; |
| 1514 | |
Abhilash Kesavan | 896ddd6 | 2015-01-10 08:41:35 +0530 | [diff] [blame] | 1515 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1516 | cci_config = of_match_node(arm_cci_matches, np)->data; |
| 1517 | if (!cci_config) |
| 1518 | return -ENODEV; |
| 1519 | |
| 1520 | nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite; |
| 1521 | |
Lorenzo Pieralisi | 7c76203 | 2014-01-27 10:50:37 +0000 | [diff] [blame] | 1522 | ports = kcalloc(nb_cci_ports, sizeof(*ports), GFP_KERNEL); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1523 | if (!ports) |
| 1524 | return -ENOMEM; |
| 1525 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1526 | for_each_child_of_node(np, cp) { |
| 1527 | if (!of_match_node(arm_cci_ctrl_if_matches, cp)) |
| 1528 | continue; |
| 1529 | |
| 1530 | i = nb_ace + nb_ace_lite; |
| 1531 | |
| 1532 | if (i >= nb_cci_ports) |
| 1533 | break; |
| 1534 | |
| 1535 | if (of_property_read_string(cp, "interface-type", |
| 1536 | &match_str)) { |
| 1537 | WARN(1, "node %s missing interface-type property\n", |
| 1538 | cp->full_name); |
| 1539 | continue; |
| 1540 | } |
| 1541 | is_ace = strcmp(match_str, "ace") == 0; |
| 1542 | if (!is_ace && strcmp(match_str, "ace-lite")) { |
| 1543 | WARN(1, "node %s containing invalid interface-type property, skipping it\n", |
| 1544 | cp->full_name); |
| 1545 | continue; |
| 1546 | } |
| 1547 | |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1548 | ret = of_address_to_resource(cp, 0, &res); |
| 1549 | if (!ret) { |
| 1550 | ports[i].base = ioremap(res.start, resource_size(&res)); |
| 1551 | ports[i].phys = res.start; |
| 1552 | } |
| 1553 | if (ret || !ports[i].base) { |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1554 | WARN(1, "unable to ioremap CCI port %d\n", i); |
| 1555 | continue; |
| 1556 | } |
| 1557 | |
| 1558 | if (is_ace) { |
| 1559 | if (WARN_ON(nb_ace >= cci_config->nb_ace)) |
| 1560 | continue; |
| 1561 | ports[i].type = ACE_PORT; |
| 1562 | ++nb_ace; |
| 1563 | } else { |
| 1564 | if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite)) |
| 1565 | continue; |
| 1566 | ports[i].type = ACE_LITE_PORT; |
| 1567 | ++nb_ace_lite; |
| 1568 | } |
| 1569 | ports[i].dn = cp; |
| 1570 | } |
| 1571 | |
| 1572 | /* initialize a stashed array of ACE ports to speed-up look-up */ |
| 1573 | cci_ace_init_ports(); |
| 1574 | |
| 1575 | /* |
| 1576 | * Multi-cluster systems may need this data when non-coherent, during |
| 1577 | * cluster power-up/power-down. Make sure it reaches main memory. |
| 1578 | */ |
| 1579 | sync_cache_w(&cci_ctrl_base); |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1580 | sync_cache_w(&cci_ctrl_phys); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1581 | sync_cache_w(&ports); |
| 1582 | sync_cache_w(&cpu_port); |
| 1583 | __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports); |
| 1584 | pr_info("ARM CCI driver probed\n"); |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1585 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1586 | return 0; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1587 | } |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 1588 | #else /* !CONFIG_ARM_CCI400_PORT_CTRL */ |
| 1589 | static inline int cci_probe_ports(struct device_node *np) |
| 1590 | { |
| 1591 | return 0; |
| 1592 | } |
| 1593 | #endif /* CONFIG_ARM_CCI400_PORT_CTRL */ |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1594 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1595 | static int cci_probe(void) |
| 1596 | { |
| 1597 | int ret; |
| 1598 | struct device_node *np; |
| 1599 | struct resource res; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1600 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1601 | np = of_find_matching_node(NULL, arm_cci_matches); |
| 1602 | if(!np || !of_device_is_available(np)) |
| 1603 | return -ENODEV; |
| 1604 | |
| 1605 | ret = of_address_to_resource(np, 0, &res); |
| 1606 | if (!ret) { |
| 1607 | cci_ctrl_base = ioremap(res.start, resource_size(&res)); |
| 1608 | cci_ctrl_phys = res.start; |
| 1609 | } |
| 1610 | if (ret || !cci_ctrl_base) { |
| 1611 | WARN(1, "unable to ioremap CCI ctrl\n"); |
| 1612 | return -ENXIO; |
| 1613 | } |
| 1614 | |
| 1615 | return cci_probe_ports(np); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1616 | } |
| 1617 | |
| 1618 | static int cci_init_status = -EAGAIN; |
| 1619 | static DEFINE_MUTEX(cci_probing); |
| 1620 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1621 | static int cci_init(void) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1622 | { |
| 1623 | if (cci_init_status != -EAGAIN) |
| 1624 | return cci_init_status; |
| 1625 | |
| 1626 | mutex_lock(&cci_probing); |
| 1627 | if (cci_init_status == -EAGAIN) |
| 1628 | cci_init_status = cci_probe(); |
| 1629 | mutex_unlock(&cci_probing); |
| 1630 | return cci_init_status; |
| 1631 | } |
| 1632 | |
| 1633 | /* |
| 1634 | * To sort out early init calls ordering a helper function is provided to |
| 1635 | * check if the CCI driver has beed initialized. Function check if the driver |
| 1636 | * has been initialized, if not it calls the init function that probes |
| 1637 | * the driver and updates the return value. |
| 1638 | */ |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1639 | bool cci_probed(void) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1640 | { |
| 1641 | return cci_init() == 0; |
| 1642 | } |
| 1643 | EXPORT_SYMBOL_GPL(cci_probed); |
| 1644 | |
| 1645 | early_initcall(cci_init); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1646 | core_initcall(cci_platform_init); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1647 | MODULE_LICENSE("GPL"); |
| 1648 | MODULE_DESCRIPTION("ARM CCI support"); |