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Alan Cox806c35f2006-01-18 17:44:08 -08001/*
2 * Intel e7xxx Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e7xxx_chips" below for supported chipsets
8 *
9 * Written by Thayne Harbaugh
10 * Based on work by Dan Hollis <goemon at anime dot net> and others.
11 * http://www.anime.net/~goemon/linux-ecc/
12 *
Mauro Carvalho Chehab30ac4402012-04-16 15:07:09 -030013 * Datasheet:
14 * http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html
15 *
Alan Cox806c35f2006-01-18 17:44:08 -080016 * Contributors:
Dave Petersone7ecd892006-03-26 01:38:52 -080017 * Eric Biederman (Linux Networx)
18 * Tom Zimmerman (Linux Networx)
19 * Jim Garlick (Lawrence Livermore National Labs)
Alan Cox806c35f2006-01-18 17:44:08 -080020 * Dave Peterson (Lawrence Livermore National Labs)
21 * That One Guy (Some other place)
22 * Wang Zhenyu (intel.com)
23 *
24 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
25 *
26 */
27
Alan Cox806c35f2006-01-18 17:44:08 -080028#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/pci_ids.h>
Dave Jiangc0d12172007-07-19 01:49:46 -070032#include <linux/edac.h>
Douglas Thompson20bcb7a2007-07-19 01:49:47 -070033#include "edac_core.h"
Alan Cox806c35f2006-01-18 17:44:08 -080034
Michal Marek152ba392011-04-01 12:41:20 +020035#define E7XXX_REVISION " Ver: 2.0.2"
Doug Thompson929a40e2006-07-01 04:35:45 -070036#define EDAC_MOD_STR "e7xxx_edac"
Doug Thompson37f04582006-06-30 01:56:07 -070037
Dave Peterson537fba22006-03-26 01:38:40 -080038#define e7xxx_printk(level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080039 edac_printk(level, "e7xxx", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080040
41#define e7xxx_mc_printk(mci, level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080042 edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080043
Alan Cox806c35f2006-01-18 17:44:08 -080044#ifndef PCI_DEVICE_ID_INTEL_7205_0
45#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
46#endif /* PCI_DEVICE_ID_INTEL_7205_0 */
47
48#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
49#define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
50#endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
51
52#ifndef PCI_DEVICE_ID_INTEL_7500_0
53#define PCI_DEVICE_ID_INTEL_7500_0 0x2540
54#endif /* PCI_DEVICE_ID_INTEL_7500_0 */
55
56#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
57#define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
58#endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
59
60#ifndef PCI_DEVICE_ID_INTEL_7501_0
61#define PCI_DEVICE_ID_INTEL_7501_0 0x254c
62#endif /* PCI_DEVICE_ID_INTEL_7501_0 */
63
64#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
65#define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
66#endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
67
68#ifndef PCI_DEVICE_ID_INTEL_7505_0
69#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
70#endif /* PCI_DEVICE_ID_INTEL_7505_0 */
71
72#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
73#define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
74#endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
75
Alan Cox806c35f2006-01-18 17:44:08 -080076#define E7XXX_NR_CSROWS 8 /* number of csrows */
Mauro Carvalho Chehab30ac4402012-04-16 15:07:09 -030077#define E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */
Alan Cox806c35f2006-01-18 17:44:08 -080078
Alan Cox806c35f2006-01-18 17:44:08 -080079/* E7XXX register addresses - device 0 function 0 */
80#define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
81#define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
82 /*
83 * 31 Device width row 7 0=x8 1=x4
84 * 27 Device width row 6
85 * 23 Device width row 5
86 * 19 Device width row 4
87 * 15 Device width row 3
88 * 11 Device width row 2
89 * 7 Device width row 1
90 * 3 Device width row 0
91 */
92#define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
93 /*
94 * 22 Number channels 0=1,1=2
95 * 19:18 DRB Granularity 32/64MB
96 */
97#define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
98#define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
99#define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
100
101/* E7XXX register addresses - device 0 function 1 */
102#define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
103#define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
104#define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
105 /* error address register (32b) */
106 /*
107 * 31:28 Reserved
108 * 27:6 CE address (4k block 33:12)
109 * 5:0 Reserved
110 */
111#define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
112 /* error address register (32b) */
113 /*
114 * 31:28 Reserved
115 * 27:6 CE address (4k block 33:12)
116 * 5:0 Reserved
117 */
118#define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
119 /* error syndrome register (16b) */
120
121enum e7xxx_chips {
122 E7500 = 0,
123 E7501,
124 E7505,
125 E7205,
126};
127
Alan Cox806c35f2006-01-18 17:44:08 -0800128struct e7xxx_pvt {
129 struct pci_dev *bridge_ck;
130 u32 tolm;
131 u32 remapbase;
132 u32 remaplimit;
133 const struct e7xxx_dev_info *dev_info;
134};
135
Alan Cox806c35f2006-01-18 17:44:08 -0800136struct e7xxx_dev_info {
137 u16 err_dev;
138 const char *ctl_name;
139};
140
Alan Cox806c35f2006-01-18 17:44:08 -0800141struct e7xxx_error_info {
142 u8 dram_ferr;
143 u8 dram_nerr;
144 u32 dram_celog_add;
145 u16 dram_celog_syndrome;
146 u32 dram_uelog_add;
147};
148
Dave Jiang456a2f92007-07-19 01:50:10 -0700149static struct edac_pci_ctl_info *e7xxx_pci;
150
Alan Cox806c35f2006-01-18 17:44:08 -0800151static const struct e7xxx_dev_info e7xxx_devs[] = {
152 [E7500] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700153 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
154 .ctl_name = "E7500"},
Alan Cox806c35f2006-01-18 17:44:08 -0800155 [E7501] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700156 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
157 .ctl_name = "E7501"},
Alan Cox806c35f2006-01-18 17:44:08 -0800158 [E7505] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700159 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
160 .ctl_name = "E7505"},
Alan Cox806c35f2006-01-18 17:44:08 -0800161 [E7205] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700162 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
163 .ctl_name = "E7205"},
Alan Cox806c35f2006-01-18 17:44:08 -0800164};
165
Alan Cox806c35f2006-01-18 17:44:08 -0800166/* FIXME - is this valid for both SECDED and S4ECD4ED? */
167static inline int e7xxx_find_channel(u16 syndrome)
168{
Joe Perches956b9ba2012-04-29 17:08:39 -0300169 edac_dbg(3, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800170
171 if ((syndrome & 0xff00) == 0)
172 return 0;
Dave Petersone7ecd892006-03-26 01:38:52 -0800173
Alan Cox806c35f2006-01-18 17:44:08 -0800174 if ((syndrome & 0x00ff) == 0)
175 return 1;
Dave Petersone7ecd892006-03-26 01:38:52 -0800176
Alan Cox806c35f2006-01-18 17:44:08 -0800177 if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
178 return 0;
Dave Petersone7ecd892006-03-26 01:38:52 -0800179
Alan Cox806c35f2006-01-18 17:44:08 -0800180 return 1;
181}
182
Dave Petersone7ecd892006-03-26 01:38:52 -0800183static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700184 unsigned long page)
Alan Cox806c35f2006-01-18 17:44:08 -0800185{
186 u32 remap;
Dave Jiang849a4c32007-07-19 01:50:03 -0700187 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
Alan Cox806c35f2006-01-18 17:44:08 -0800188
Joe Perches956b9ba2012-04-29 17:08:39 -0300189 edac_dbg(3, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800190
191 if ((page < pvt->tolm) ||
Douglas Thompson052dfb42007-07-19 01:50:13 -0700192 ((page >= 0x100000) && (page < pvt->remapbase)))
Alan Cox806c35f2006-01-18 17:44:08 -0800193 return page;
Dave Petersone7ecd892006-03-26 01:38:52 -0800194
Alan Cox806c35f2006-01-18 17:44:08 -0800195 remap = (page - pvt->tolm) + pvt->remapbase;
Dave Petersone7ecd892006-03-26 01:38:52 -0800196
Alan Cox806c35f2006-01-18 17:44:08 -0800197 if (remap < pvt->remaplimit)
198 return remap;
Dave Petersone7ecd892006-03-26 01:38:52 -0800199
Dave Peterson537fba22006-03-26 01:38:40 -0800200 e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
Alan Cox806c35f2006-01-18 17:44:08 -0800201 return pvt->tolm - 1;
202}
203
Dave Jiang849a4c32007-07-19 01:50:03 -0700204static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800205{
206 u32 error_1b, page;
207 u16 syndrome;
208 int row;
209 int channel;
210
Joe Perches956b9ba2012-04-29 17:08:39 -0300211 edac_dbg(3, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800212 /* read the error address */
213 error_1b = info->dram_celog_add;
214 /* FIXME - should use PAGE_SHIFT */
Dave Jiang849a4c32007-07-19 01:50:03 -0700215 page = error_1b >> 6; /* convert the address to 4k page */
Alan Cox806c35f2006-01-18 17:44:08 -0800216 /* read the syndrome */
217 syndrome = info->dram_celog_syndrome;
218 /* FIXME - check for -1 */
219 row = edac_mc_find_csrow_by_page(mci, page);
220 /* convert syndrome to channel */
221 channel = e7xxx_find_channel(syndrome);
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300222 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300223 row, channel, -1, "e7xxx CE", "");
Alan Cox806c35f2006-01-18 17:44:08 -0800224}
225
Alan Cox806c35f2006-01-18 17:44:08 -0800226static void process_ce_no_info(struct mem_ctl_info *mci)
227{
Joe Perches956b9ba2012-04-29 17:08:39 -0300228 edac_dbg(3, "\n");
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300229 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300230 "e7xxx CE log register overflow", "");
Alan Cox806c35f2006-01-18 17:44:08 -0800231}
232
Dave Jiang849a4c32007-07-19 01:50:03 -0700233static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800234{
235 u32 error_2b, block_page;
236 int row;
237
Joe Perches956b9ba2012-04-29 17:08:39 -0300238 edac_dbg(3, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800239 /* read the error address */
240 error_2b = info->dram_uelog_add;
241 /* FIXME - should use PAGE_SHIFT */
Dave Jiang849a4c32007-07-19 01:50:03 -0700242 block_page = error_2b >> 6; /* convert to 4k address */
Alan Cox806c35f2006-01-18 17:44:08 -0800243 row = edac_mc_find_csrow_by_page(mci, block_page);
Mauro Carvalho Chehab30ac4402012-04-16 15:07:09 -0300244
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300245 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300246 row, -1, -1, "e7xxx UE", "");
Alan Cox806c35f2006-01-18 17:44:08 -0800247}
248
Alan Cox806c35f2006-01-18 17:44:08 -0800249static void process_ue_no_info(struct mem_ctl_info *mci)
250{
Joe Perches956b9ba2012-04-29 17:08:39 -0300251 edac_dbg(3, "\n");
Mauro Carvalho Chehab30ac4402012-04-16 15:07:09 -0300252
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300253 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300254 "e7xxx UE log register overflow", "");
Alan Cox806c35f2006-01-18 17:44:08 -0800255}
256
Dave Jiang849a4c32007-07-19 01:50:03 -0700257static void e7xxx_get_error_info(struct mem_ctl_info *mci,
258 struct e7xxx_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800259{
260 struct e7xxx_pvt *pvt;
261
Dave Jiang849a4c32007-07-19 01:50:03 -0700262 pvt = (struct e7xxx_pvt *)mci->pvt_info;
263 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
264 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
Alan Cox806c35f2006-01-18 17:44:08 -0800265
266 if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
267 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700268 &info->dram_celog_add);
Alan Cox806c35f2006-01-18 17:44:08 -0800269 pci_read_config_word(pvt->bridge_ck,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700270 E7XXX_DRAM_CELOG_SYNDROME,
271 &info->dram_celog_syndrome);
Alan Cox806c35f2006-01-18 17:44:08 -0800272 }
273
274 if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
275 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700276 &info->dram_uelog_add);
Alan Cox806c35f2006-01-18 17:44:08 -0800277
278 if (info->dram_ferr & 3)
Dave Petersone7ecd892006-03-26 01:38:52 -0800279 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
Alan Cox806c35f2006-01-18 17:44:08 -0800280
281 if (info->dram_nerr & 3)
Dave Petersone7ecd892006-03-26 01:38:52 -0800282 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
Alan Cox806c35f2006-01-18 17:44:08 -0800283}
284
Dave Jiang849a4c32007-07-19 01:50:03 -0700285static int e7xxx_process_error_info(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700286 struct e7xxx_error_info *info,
287 int handle_errors)
Alan Cox806c35f2006-01-18 17:44:08 -0800288{
289 int error_found;
290
291 error_found = 0;
292
293 /* decode and report errors */
294 if (info->dram_ferr & 1) { /* check first error correctable */
295 error_found = 1;
296
297 if (handle_errors)
298 process_ce(mci, info);
299 }
300
301 if (info->dram_ferr & 2) { /* check first error uncorrectable */
302 error_found = 1;
303
304 if (handle_errors)
305 process_ue(mci, info);
306 }
307
308 if (info->dram_nerr & 1) { /* check next error correctable */
309 error_found = 1;
310
311 if (handle_errors) {
312 if (info->dram_ferr & 1)
313 process_ce_no_info(mci);
314 else
315 process_ce(mci, info);
316 }
317 }
318
319 if (info->dram_nerr & 2) { /* check next error uncorrectable */
320 error_found = 1;
321
322 if (handle_errors) {
323 if (info->dram_ferr & 2)
324 process_ue_no_info(mci);
325 else
326 process_ue(mci, info);
327 }
328 }
329
330 return error_found;
331}
332
Alan Cox806c35f2006-01-18 17:44:08 -0800333static void e7xxx_check(struct mem_ctl_info *mci)
334{
335 struct e7xxx_error_info info;
336
Joe Perches956b9ba2012-04-29 17:08:39 -0300337 edac_dbg(3, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800338 e7xxx_get_error_info(mci, &info);
339 e7xxx_process_error_info(mci, &info, 1);
340}
341
Doug Thompson13189522006-06-30 01:56:08 -0700342/* Return 1 if dual channel mode is active. Else return 0. */
343static inline int dual_channel_active(u32 drc, int dev_idx)
Alan Cox806c35f2006-01-18 17:44:08 -0800344{
Doug Thompson13189522006-06-30 01:56:08 -0700345 return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
346}
Alan Cox806c35f2006-01-18 17:44:08 -0800347
Doug Thompson13189522006-06-30 01:56:08 -0700348/* Return DRB granularity (0=32mb, 1=64mb). */
349static inline int drb_granularity(u32 drc, int dev_idx)
350{
Alan Cox806c35f2006-01-18 17:44:08 -0800351 /* only e7501 can be single channel */
Doug Thompson13189522006-06-30 01:56:08 -0700352 return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
353}
Alan Cox806c35f2006-01-18 17:44:08 -0800354
Doug Thompson13189522006-06-30 01:56:08 -0700355static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700356 int dev_idx, u32 drc)
Doug Thompson13189522006-06-30 01:56:08 -0700357{
358 unsigned long last_cumul_size;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300359 int index, j;
Doug Thompson13189522006-06-30 01:56:08 -0700360 u8 value;
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300361 u32 dra, cumul_size, nr_pages;
Doug Thompson13189522006-06-30 01:56:08 -0700362 int drc_chan, drc_drbg, drc_ddim, mem_dev;
363 struct csrow_info *csrow;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300364 struct dimm_info *dimm;
Mauro Carvalho Chehabfd633122012-03-28 19:37:59 -0300365 enum edac_type edac_mode;
Alan Cox806c35f2006-01-18 17:44:08 -0800366
Alan Cox806c35f2006-01-18 17:44:08 -0800367 pci_read_config_dword(pdev, E7XXX_DRA, &dra);
Doug Thompson13189522006-06-30 01:56:08 -0700368 drc_chan = dual_channel_active(drc, dev_idx);
369 drc_drbg = drb_granularity(drc, dev_idx);
370 drc_ddim = (drc >> 20) & 0x3;
371 last_cumul_size = 0;
Alan Cox806c35f2006-01-18 17:44:08 -0800372
Doug Thompson13189522006-06-30 01:56:08 -0700373 /* The dram row boundary (DRB) reg values are boundary address
Alan Cox806c35f2006-01-18 17:44:08 -0800374 * for each DRAM row with a granularity of 32 or 64MB (single/dual
375 * channel operation). DRB regs are cumulative; therefore DRB7 will
376 * contain the total memory contained in all eight rows.
377 */
Doug Thompson13189522006-06-30 01:56:08 -0700378 for (index = 0; index < mci->nr_csrows; index++) {
Alan Cox806c35f2006-01-18 17:44:08 -0800379 /* mem_dev 0=x8, 1=x4 */
Doug Thompson13189522006-06-30 01:56:08 -0700380 mem_dev = (dra >> (index * 4 + 3)) & 0x1;
Mauro Carvalho Chehabde3910eb2012-04-24 15:05:43 -0300381 csrow = mci->csrows[index];
Alan Cox806c35f2006-01-18 17:44:08 -0800382
Doug Thompson37f04582006-06-30 01:56:07 -0700383 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
Alan Cox806c35f2006-01-18 17:44:08 -0800384 /* convert a 64 or 32 MiB DRB to a page size. */
385 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
Joe Perches956b9ba2012-04-29 17:08:39 -0300386 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
Alan Cox806c35f2006-01-18 17:44:08 -0800387 if (cumul_size == last_cumul_size)
Doug Thompson13189522006-06-30 01:56:08 -0700388 continue; /* not populated */
Alan Cox806c35f2006-01-18 17:44:08 -0800389
390 csrow->first_page = last_cumul_size;
391 csrow->last_page = cumul_size - 1;
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300392 nr_pages = cumul_size - last_cumul_size;
Alan Cox806c35f2006-01-18 17:44:08 -0800393 last_cumul_size = cumul_size;
Alan Cox806c35f2006-01-18 17:44:08 -0800394
Mauro Carvalho Chehabfd633122012-03-28 19:37:59 -0300395 /*
396 * if single channel or x8 devices then SECDED
397 * if dual channel and x4 then S4ECD4ED
398 */
399 if (drc_ddim) {
400 if (drc_chan && mem_dev) {
401 edac_mode = EDAC_S4ECD4ED;
402 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
403 } else {
404 edac_mode = EDAC_SECDED;
405 mci->edac_cap |= EDAC_FLAG_SECDED;
406 }
407 } else
408 edac_mode = EDAC_NONE;
409
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300410 for (j = 0; j < drc_chan + 1; j++) {
Mauro Carvalho Chehabde3910eb2012-04-24 15:05:43 -0300411 dimm = csrow->channels[j]->dimm;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300412
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300413 dimm->nr_pages = nr_pages / (drc_chan + 1);
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300414 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
415 dimm->mtype = MEM_RDDR; /* only one type supported */
416 dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
Mauro Carvalho Chehabfd633122012-03-28 19:37:59 -0300417 dimm->edac_mode = edac_mode;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300418 }
Alan Cox806c35f2006-01-18 17:44:08 -0800419 }
Doug Thompson13189522006-06-30 01:56:08 -0700420}
Alan Cox806c35f2006-01-18 17:44:08 -0800421
Doug Thompson13189522006-06-30 01:56:08 -0700422static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
423{
424 u16 pci_data;
425 struct mem_ctl_info *mci = NULL;
Mauro Carvalho Chehab30ac4402012-04-16 15:07:09 -0300426 struct edac_mc_layer layers[2];
Doug Thompson13189522006-06-30 01:56:08 -0700427 struct e7xxx_pvt *pvt = NULL;
428 u32 drc;
429 int drc_chan;
430 struct e7xxx_error_info discard;
431
Joe Perches956b9ba2012-04-29 17:08:39 -0300432 edac_dbg(0, "mci\n");
Dave Jiangc0d12172007-07-19 01:49:46 -0700433
Doug Thompson13189522006-06-30 01:56:08 -0700434 pci_read_config_dword(pdev, E7XXX_DRC, &drc);
435
436 drc_chan = dual_channel_active(drc, dev_idx);
Mauro Carvalho Chehab30ac4402012-04-16 15:07:09 -0300437 /*
438 * According with the datasheet, this device has a maximum of
439 * 4 DIMMS per channel, either single-rank or dual-rank. So, the
440 * total amount of dimms is 8 (E7XXX_NR_DIMMS).
441 * That means that the DIMM is mapped as CSROWs, and the channel
442 * will map the rank. So, an error to either channel should be
443 * attributed to the same dimm.
444 */
445 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
446 layers[0].size = E7XXX_NR_CSROWS;
447 layers[0].is_virt_csrow = true;
448 layers[1].type = EDAC_MC_LAYER_CHANNEL;
449 layers[1].size = drc_chan + 1;
450 layers[1].is_virt_csrow = false;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -0300451 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
Doug Thompson13189522006-06-30 01:56:08 -0700452 if (mci == NULL)
453 return -ENOMEM;
454
Joe Perches956b9ba2012-04-29 17:08:39 -0300455 edac_dbg(3, "init mci\n");
Doug Thompson13189522006-06-30 01:56:08 -0700456 mci->mtype_cap = MEM_FLAG_RDDR;
457 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
Douglas Thompson052dfb42007-07-19 01:50:13 -0700458 EDAC_FLAG_S4ECD4ED;
Doug Thompson13189522006-06-30 01:56:08 -0700459 /* FIXME - what if different memory types are in different csrows? */
460 mci->mod_name = EDAC_MOD_STR;
461 mci->mod_ver = E7XXX_REVISION;
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -0300462 mci->pdev = &pdev->dev;
Joe Perches956b9ba2012-04-29 17:08:39 -0300463 edac_dbg(3, "init pvt\n");
Dave Jiang849a4c32007-07-19 01:50:03 -0700464 pvt = (struct e7xxx_pvt *)mci->pvt_info;
Doug Thompson13189522006-06-30 01:56:08 -0700465 pvt->dev_info = &e7xxx_devs[dev_idx];
466 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
Dave Jiang849a4c32007-07-19 01:50:03 -0700467 pvt->dev_info->err_dev, pvt->bridge_ck);
Doug Thompson13189522006-06-30 01:56:08 -0700468
469 if (!pvt->bridge_ck) {
470 e7xxx_printk(KERN_ERR, "error reporting device not found:"
Douglas Thompson052dfb42007-07-19 01:50:13 -0700471 "vendor %x device 0x%x (broken BIOS?)\n",
472 PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
Doug Thompson13189522006-06-30 01:56:08 -0700473 goto fail0;
474 }
475
Joe Perches956b9ba2012-04-29 17:08:39 -0300476 edac_dbg(3, "more mci init\n");
Doug Thompson13189522006-06-30 01:56:08 -0700477 mci->ctl_name = pvt->dev_info->ctl_name;
Dave Jiangc4192702007-07-19 01:49:47 -0700478 mci->dev_name = pci_name(pdev);
Doug Thompson13189522006-06-30 01:56:08 -0700479 mci->edac_check = e7xxx_check;
480 mci->ctl_page_to_phys = ctl_page_to_phys;
481 e7xxx_init_csrows(mci, pdev, dev_idx, drc);
Alan Cox806c35f2006-01-18 17:44:08 -0800482 mci->edac_cap |= EDAC_FLAG_NONE;
Joe Perches956b9ba2012-04-29 17:08:39 -0300483 edac_dbg(3, "tolm, remapbase, remaplimit\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800484 /* load the top of low memory, remap base, and remap limit vars */
Doug Thompson37f04582006-06-30 01:56:07 -0700485 pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800486 pvt->tolm = ((u32) pci_data) << 4;
Doug Thompson37f04582006-06-30 01:56:07 -0700487 pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800488 pvt->remapbase = ((u32) pci_data) << 14;
Doug Thompson37f04582006-06-30 01:56:07 -0700489 pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800490 pvt->remaplimit = ((u32) pci_data) << 14;
Dave Peterson537fba22006-03-26 01:38:40 -0800491 e7xxx_printk(KERN_INFO,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700492 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
493 pvt->remapbase, pvt->remaplimit);
Alan Cox806c35f2006-01-18 17:44:08 -0800494
495 /* clear any pending errors, or initial state bits */
Dave Peterson749ede52006-03-26 01:38:45 -0800496 e7xxx_get_error_info(mci, &discard);
Alan Cox806c35f2006-01-18 17:44:08 -0800497
Doug Thompson2d7bbb92006-06-30 01:56:08 -0700498 /* Here we assume that we will never see multiple instances of this
499 * type of memory controller. The ID is therefore hardcoded to 0.
500 */
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700501 if (edac_mc_add_mc(mci)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300502 edac_dbg(3, "failed edac_mc_add_mc()\n");
Doug Thompson13189522006-06-30 01:56:08 -0700503 goto fail1;
Alan Cox806c35f2006-01-18 17:44:08 -0800504 }
505
Dave Jiang456a2f92007-07-19 01:50:10 -0700506 /* allocating generic PCI control info */
507 e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
508 if (!e7xxx_pci) {
509 printk(KERN_WARNING
510 "%s(): Unable to create PCI control\n",
511 __func__);
512 printk(KERN_WARNING
513 "%s(): PCI error report via EDAC not setup\n",
514 __func__);
515 }
516
Alan Cox806c35f2006-01-18 17:44:08 -0800517 /* get this far and it's successful */
Joe Perches956b9ba2012-04-29 17:08:39 -0300518 edac_dbg(3, "success\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800519 return 0;
520
Douglas Thompson052dfb42007-07-19 01:50:13 -0700521fail1:
Doug Thompson13189522006-06-30 01:56:08 -0700522 pci_dev_put(pvt->bridge_ck);
Alan Cox806c35f2006-01-18 17:44:08 -0800523
Douglas Thompson052dfb42007-07-19 01:50:13 -0700524fail0:
Doug Thompson13189522006-06-30 01:56:08 -0700525 edac_mc_free(mci);
526
527 return -ENODEV;
Alan Cox806c35f2006-01-18 17:44:08 -0800528}
529
530/* returns count (>= 0), or negative on error */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800531static int e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Alan Cox806c35f2006-01-18 17:44:08 -0800532{
Joe Perches956b9ba2012-04-29 17:08:39 -0300533 edac_dbg(0, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800534
535 /* wake up and enable device */
536 return pci_enable_device(pdev) ?
Douglas Thompson052dfb42007-07-19 01:50:13 -0700537 -EIO : e7xxx_probe1(pdev, ent->driver_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800538}
539
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800540static void e7xxx_remove_one(struct pci_dev *pdev)
Alan Cox806c35f2006-01-18 17:44:08 -0800541{
542 struct mem_ctl_info *mci;
543 struct e7xxx_pvt *pvt;
544
Joe Perches956b9ba2012-04-29 17:08:39 -0300545 edac_dbg(0, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800546
Dave Jiang456a2f92007-07-19 01:50:10 -0700547 if (e7xxx_pci)
548 edac_pci_release_generic_ctl(e7xxx_pci);
549
Doug Thompson37f04582006-06-30 01:56:07 -0700550 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
Dave Peterson18dbc332006-03-26 01:38:50 -0800551 return;
552
Dave Jiang849a4c32007-07-19 01:50:03 -0700553 pvt = (struct e7xxx_pvt *)mci->pvt_info;
Dave Peterson18dbc332006-03-26 01:38:50 -0800554 pci_dev_put(pvt->bridge_ck);
555 edac_mc_free(mci);
Alan Cox806c35f2006-01-18 17:44:08 -0800556}
557
Lionel Debroux36c46f32012-02-27 07:41:47 +0100558static DEFINE_PCI_DEVICE_TABLE(e7xxx_pci_tbl) = {
Dave Petersone7ecd892006-03-26 01:38:52 -0800559 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700560 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
561 E7205},
Dave Petersone7ecd892006-03-26 01:38:52 -0800562 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700563 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
564 E7500},
Dave Petersone7ecd892006-03-26 01:38:52 -0800565 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700566 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
567 E7501},
Dave Petersone7ecd892006-03-26 01:38:52 -0800568 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700569 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
570 E7505},
Dave Petersone7ecd892006-03-26 01:38:52 -0800571 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700572 0,
573 } /* 0 terminated list. */
Alan Cox806c35f2006-01-18 17:44:08 -0800574};
575
576MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
577
Alan Cox806c35f2006-01-18 17:44:08 -0800578static struct pci_driver e7xxx_driver = {
Dave Peterson680cbbb2006-03-26 01:38:41 -0800579 .name = EDAC_MOD_STR,
Alan Cox806c35f2006-01-18 17:44:08 -0800580 .probe = e7xxx_init_one,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800581 .remove = e7xxx_remove_one,
Alan Cox806c35f2006-01-18 17:44:08 -0800582 .id_table = e7xxx_pci_tbl,
583};
584
Alan Coxda9bb1d2006-01-18 17:44:13 -0800585static int __init e7xxx_init(void)
Alan Cox806c35f2006-01-18 17:44:08 -0800586{
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700587 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
588 opstate_init();
589
Alan Cox806c35f2006-01-18 17:44:08 -0800590 return pci_register_driver(&e7xxx_driver);
591}
592
Alan Cox806c35f2006-01-18 17:44:08 -0800593static void __exit e7xxx_exit(void)
594{
595 pci_unregister_driver(&e7xxx_driver);
596}
597
598module_init(e7xxx_init);
599module_exit(e7xxx_exit);
600
Alan Cox806c35f2006-01-18 17:44:08 -0800601MODULE_LICENSE("GPL");
602MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
Douglas Thompson052dfb42007-07-19 01:50:13 -0700603 "Based on.work by Dan Hollis et al");
Alan Cox806c35f2006-01-18 17:44:08 -0800604MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
Dave Jiangc0d12172007-07-19 01:49:46 -0700605module_param(edac_op_state, int, 0444);
606MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");