Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-imx/dma.c |
| 3 | * |
| 4 | * imx DMA registration and IRQ dispatching |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 10 | * 2004-03-03 Sascha Hauer <sascha@saschahauer.de> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | * initial version heavily inspired by |
| 12 | * linux/arch/arm/mach-pxa/dma.c |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 13 | * |
| 14 | * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz> |
| 15 | * Changed to support scatter gather DMA |
| 16 | * by taking Russell's code from RiscPC |
| 17 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | */ |
| 19 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 20 | #undef DEBUG |
| 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <linux/module.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/errno.h> |
| 27 | |
| 28 | #include <asm/system.h> |
| 29 | #include <asm/irq.h> |
| 30 | #include <asm/hardware.h> |
| 31 | #include <asm/dma.h> |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 32 | #include <asm/arch/imx-dma.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 34 | struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 36 | /* |
| 37 | * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation |
| 38 | * @dma_ch: i.MX DMA channel number |
| 39 | * @lastcount: number of bytes transferred during last transfer |
| 40 | * |
| 41 | * Functions prepares DMA controller for next sg data chunk transfer. |
| 42 | * The @lastcount argument informs function about number of bytes transferred |
| 43 | * during last block. Zero value can be used for @lastcount to setup DMA |
| 44 | * for the first chunk. |
| 45 | */ |
| 46 | static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | { |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 48 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 49 | unsigned int nextcount; |
| 50 | unsigned int nextaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 52 | if (!imxdma->name) { |
| 53 | printk(KERN_CRIT "%s: called for not allocated channel %d\n", |
| 54 | __FUNCTION__, dma_ch); |
| 55 | return 0; |
| 56 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 58 | imxdma->resbytes -= lastcount; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 60 | if (!imxdma->sg) { |
| 61 | pr_debug("imxdma%d: no sg data\n", dma_ch); |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | imxdma->sgbc += lastcount; |
| 66 | if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) { |
| 67 | if ((imxdma->sgcount <= 1) || !imxdma->resbytes) { |
| 68 | pr_debug("imxdma%d: sg transfer limit reached\n", |
| 69 | dma_ch); |
| 70 | imxdma->sgcount=0; |
| 71 | imxdma->sg = NULL; |
| 72 | return 0; |
| 73 | } else { |
| 74 | imxdma->sgcount--; |
| 75 | imxdma->sg++; |
| 76 | imxdma->sgbc = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | } |
| 78 | } |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 79 | nextcount = imxdma->sg->length - imxdma->sgbc; |
| 80 | nextaddr = imxdma->sg->dma_address + imxdma->sgbc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 82 | if(imxdma->resbytes < nextcount) |
| 83 | nextcount = imxdma->resbytes; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 85 | if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) |
| 86 | DAR(dma_ch) = nextaddr; |
| 87 | else |
| 88 | SAR(dma_ch) = nextaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 90 | CNTR(dma_ch) = nextcount; |
| 91 | pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n", |
| 92 | dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch)); |
| 93 | |
| 94 | return nextcount; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | } |
| 96 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 97 | /* |
| 98 | * imx_dma_setup_sg_base - scatter-gather DMA emulation |
| 99 | * @dma_ch: i.MX DMA channel number |
| 100 | * @sg: pointer to the scatter-gather list/vector |
| 101 | * @sgcount: scatter-gather list hungs count |
| 102 | * |
| 103 | * Functions sets up i.MX DMA state for emulated scatter-gather transfer |
| 104 | * and sets up channel registers to be ready for the first chunk |
| 105 | */ |
| 106 | static int |
| 107 | imx_dma_setup_sg_base(imx_dmach_t dma_ch, |
| 108 | struct scatterlist *sg, unsigned int sgcount) |
| 109 | { |
| 110 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 111 | |
| 112 | imxdma->sg = sg; |
| 113 | imxdma->sgcount = sgcount; |
| 114 | imxdma->sgbc = 0; |
| 115 | return imx_dma_sg_next(dma_ch, 0); |
| 116 | } |
| 117 | |
| 118 | /** |
| 119 | * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer |
| 120 | * @dma_ch: i.MX DMA channel number |
| 121 | * @dma_address: the DMA/physical memory address of the linear data block |
| 122 | * to transfer |
| 123 | * @dma_length: length of the data block in bytes |
| 124 | * @dev_addr: physical device port address |
| 125 | * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory |
| 126 | * or %DMA_MODE_WRITE from memory to the device |
| 127 | * |
| 128 | * The function setups DMA channel source and destination addresses for transfer |
| 129 | * specified by provided parameters. The scatter-gather emulation is disabled, |
| 130 | * because linear data block |
| 131 | * form the physical address range is transfered. |
| 132 | * Return value: if incorrect parameters are provided -%EINVAL. |
| 133 | * Zero indicates success. |
| 134 | */ |
| 135 | int |
| 136 | imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, |
| 137 | unsigned int dma_length, unsigned int dev_addr, |
| 138 | dmamode_t dmamode) |
| 139 | { |
| 140 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 141 | |
| 142 | imxdma->sg = NULL; |
| 143 | imxdma->sgcount = 0; |
| 144 | imxdma->dma_mode = dmamode; |
| 145 | imxdma->resbytes = dma_length; |
| 146 | |
| 147 | if (!dma_address) { |
| 148 | printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n", |
| 149 | dma_ch); |
| 150 | return -EINVAL; |
| 151 | } |
| 152 | |
| 153 | if (!dma_length) { |
| 154 | printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n", |
| 155 | dma_ch); |
| 156 | return -EINVAL; |
| 157 | } |
| 158 | |
| 159 | if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { |
| 160 | pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n", |
| 161 | dma_ch, (unsigned int)dma_address, dma_length, |
| 162 | dev_addr); |
| 163 | SAR(dma_ch) = dev_addr; |
| 164 | DAR(dma_ch) = (unsigned int)dma_address; |
| 165 | } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { |
| 166 | pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n", |
| 167 | dma_ch, (unsigned int)dma_address, dma_length, |
| 168 | dev_addr); |
| 169 | SAR(dma_ch) = (unsigned int)dma_address; |
| 170 | DAR(dma_ch) = dev_addr; |
| 171 | } else { |
| 172 | printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", |
| 173 | dma_ch); |
| 174 | return -EINVAL; |
| 175 | } |
| 176 | |
| 177 | CNTR(dma_ch) = dma_length; |
| 178 | |
| 179 | return 0; |
| 180 | } |
| 181 | |
| 182 | /** |
| 183 | * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer |
| 184 | * @dma_ch: i.MX DMA channel number |
| 185 | * @sg: pointer to the scatter-gather list/vector |
| 186 | * @sgcount: scatter-gather list hungs count |
| 187 | * @dma_length: total length of the transfer request in bytes |
| 188 | * @dev_addr: physical device port address |
| 189 | * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory |
| 190 | * or %DMA_MODE_WRITE from memory to the device |
| 191 | * |
| 192 | * The function setups DMA channel state and registers to be ready for transfer |
| 193 | * specified by provided parameters. The scatter-gather emulation is set up |
| 194 | * according to the parameters. |
| 195 | * |
| 196 | * The full preparation of the transfer requires setup of more register |
| 197 | * by the caller before imx_dma_enable() can be called. |
| 198 | * |
| 199 | * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes |
| 200 | * |
| 201 | * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx |
| 202 | * |
| 203 | * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical |
| 204 | * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified |
| 205 | * |
| 206 | * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x |
| 207 | * |
| 208 | * The typical setup for %DMA_MODE_WRITE is specified by next options combination |
| 209 | * |
| 210 | * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x |
| 211 | * |
| 212 | * Be carefull there and do not mistakenly mix source and target device |
| 213 | * port sizes constants, they are really different: |
| 214 | * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, |
| 215 | * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 |
| 216 | * |
| 217 | * Return value: if incorrect parameters are provided -%EINVAL. |
| 218 | * Zero indicates success. |
| 219 | */ |
| 220 | int |
| 221 | imx_dma_setup_sg(imx_dmach_t dma_ch, |
| 222 | struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, |
| 223 | unsigned int dev_addr, dmamode_t dmamode) |
| 224 | { |
| 225 | int res; |
| 226 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 227 | |
| 228 | imxdma->sg = NULL; |
| 229 | imxdma->sgcount = 0; |
| 230 | imxdma->dma_mode = dmamode; |
| 231 | imxdma->resbytes = dma_length; |
| 232 | |
| 233 | if (!sg || !sgcount) { |
| 234 | printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n", |
| 235 | dma_ch); |
| 236 | return -EINVAL; |
| 237 | } |
| 238 | |
| 239 | if (!sg->length) { |
| 240 | printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n", |
| 241 | dma_ch); |
| 242 | return -EINVAL; |
| 243 | } |
| 244 | |
| 245 | if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { |
| 246 | pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n", |
| 247 | dma_ch, sg, sgcount, dma_length, dev_addr); |
| 248 | SAR(dma_ch) = dev_addr; |
| 249 | } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { |
| 250 | pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n", |
| 251 | dma_ch, sg, sgcount, dma_length, dev_addr); |
| 252 | DAR(dma_ch) = dev_addr; |
| 253 | } else { |
| 254 | printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", |
| 255 | dma_ch); |
| 256 | return -EINVAL; |
| 257 | } |
| 258 | |
| 259 | res = imx_dma_setup_sg_base(dma_ch, sg, sgcount); |
| 260 | if (res <= 0) { |
| 261 | printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch); |
| 262 | return -EINVAL; |
| 263 | } |
| 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | /** |
| 269 | * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers |
| 270 | * @dma_ch: i.MX DMA channel number |
| 271 | * @irq_handler: the pointer to the function called if the transfer |
| 272 | * ends successfully |
| 273 | * @err_handler: the pointer to the function called if the premature |
| 274 | * end caused by error occurs |
| 275 | * @data: user specified value to be passed to the handlers |
| 276 | */ |
| 277 | int |
| 278 | imx_dma_setup_handlers(imx_dmach_t dma_ch, |
| 279 | void (*irq_handler) (int, void *, struct pt_regs *), |
| 280 | void (*err_handler) (int, void *, struct pt_regs *), |
| 281 | void *data) |
| 282 | { |
| 283 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 284 | unsigned long flags; |
| 285 | |
| 286 | if (!imxdma->name) { |
| 287 | printk(KERN_CRIT "%s: called for not allocated channel %d\n", |
| 288 | __FUNCTION__, dma_ch); |
| 289 | return -ENODEV; |
| 290 | } |
| 291 | |
| 292 | local_irq_save(flags); |
| 293 | DISR = (1 << dma_ch); |
| 294 | imxdma->irq_handler = irq_handler; |
| 295 | imxdma->err_handler = err_handler; |
| 296 | imxdma->data = data; |
| 297 | local_irq_restore(flags); |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | /** |
| 302 | * imx_dma_enable - function to start i.MX DMA channel operation |
| 303 | * @dma_ch: i.MX DMA channel number |
| 304 | * |
| 305 | * The channel has to be allocated by driver through imx_dma_request() |
| 306 | * or imx_dma_request_by_prio() function. |
| 307 | * The transfer parameters has to be set to the channel registers through |
| 308 | * call of the imx_dma_setup_single() or imx_dma_setup_sg() function |
| 309 | * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to |
| 310 | * be set prior this function call by the channel user. |
| 311 | */ |
| 312 | void imx_dma_enable(imx_dmach_t dma_ch) |
| 313 | { |
| 314 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 315 | unsigned long flags; |
| 316 | |
| 317 | pr_debug("imxdma%d: imx_dma_enable\n", dma_ch); |
| 318 | |
| 319 | if (!imxdma->name) { |
| 320 | printk(KERN_CRIT "%s: called for not allocated channel %d\n", |
| 321 | __FUNCTION__, dma_ch); |
| 322 | return; |
| 323 | } |
| 324 | |
| 325 | local_irq_save(flags); |
| 326 | DISR = (1 << dma_ch); |
| 327 | DIMR &= ~(1 << dma_ch); |
| 328 | CCR(dma_ch) |= CCR_CEN; |
| 329 | local_irq_restore(flags); |
| 330 | } |
| 331 | |
| 332 | /** |
| 333 | * imx_dma_disable - stop, finish i.MX DMA channel operatin |
| 334 | * @dma_ch: i.MX DMA channel number |
| 335 | */ |
| 336 | void imx_dma_disable(imx_dmach_t dma_ch) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | { |
| 338 | unsigned long flags; |
| 339 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 340 | pr_debug("imxdma%d: imx_dma_disable\n", dma_ch); |
| 341 | |
| 342 | local_irq_save(flags); |
| 343 | DIMR |= (1 << dma_ch); |
| 344 | CCR(dma_ch) &= ~CCR_CEN; |
| 345 | DISR = (1 << dma_ch); |
| 346 | local_irq_restore(flags); |
| 347 | } |
| 348 | |
| 349 | /** |
| 350 | * imx_dma_request - request/allocate specified channel number |
| 351 | * @dma_ch: i.MX DMA channel number |
| 352 | * @name: the driver/caller own non-%NULL identification |
| 353 | */ |
| 354 | int imx_dma_request(imx_dmach_t dma_ch, const char *name) |
| 355 | { |
| 356 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 357 | unsigned long flags; |
| 358 | |
| 359 | /* basic sanity checks */ |
| 360 | if (!name) |
| 361 | return -EINVAL; |
| 362 | |
| 363 | if (dma_ch >= IMX_DMA_CHANNELS) { |
| 364 | printk(KERN_CRIT "%s: called for non-existed channel %d\n", |
| 365 | __FUNCTION__, dma_ch); |
| 366 | return -EINVAL; |
| 367 | } |
| 368 | |
| 369 | local_irq_save(flags); |
| 370 | if (imxdma->name) { |
| 371 | local_irq_restore(flags); |
| 372 | return -ENODEV; |
| 373 | } |
| 374 | |
| 375 | imxdma->name = name; |
| 376 | imxdma->irq_handler = NULL; |
| 377 | imxdma->err_handler = NULL; |
| 378 | imxdma->data = NULL; |
| 379 | imxdma->sg = NULL; |
| 380 | local_irq_restore(flags); |
| 381 | return 0; |
| 382 | } |
| 383 | |
| 384 | /** |
| 385 | * imx_dma_free - release previously acquired channel |
| 386 | * @dma_ch: i.MX DMA channel number |
| 387 | */ |
| 388 | void imx_dma_free(imx_dmach_t dma_ch) |
| 389 | { |
| 390 | unsigned long flags; |
| 391 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; |
| 392 | |
| 393 | if (!imxdma->name) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | printk(KERN_CRIT |
| 395 | "%s: trying to free channel %d which is already freed\n", |
| 396 | __FUNCTION__, dma_ch); |
| 397 | return; |
| 398 | } |
| 399 | |
| 400 | local_irq_save(flags); |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 401 | /* Disable interrupts */ |
| 402 | DIMR |= (1 << dma_ch); |
| 403 | CCR(dma_ch) &= ~CCR_CEN; |
| 404 | imxdma->name = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | local_irq_restore(flags); |
| 406 | } |
| 407 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 408 | /** |
| 409 | * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority |
| 410 | * @dma_ch: i.MX DMA channel number |
| 411 | * @name: the driver/caller own non-%NULL identification |
| 412 | * @prio: one of the hardware distinguished priority level: |
| 413 | * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW |
| 414 | * |
| 415 | * This function tries to find free channel in the specified priority group |
| 416 | * if the priority cannot be achieved it tries to look for free channel |
| 417 | * in the higher and then even lower priority groups. |
| 418 | * |
| 419 | * Return value: If there is no free channel to allocate, -%ENODEV is returned. |
| 420 | * Zero value indicates successful channel allocation. |
| 421 | */ |
| 422 | int |
| 423 | imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name, |
| 424 | imx_dma_prio prio) |
| 425 | { |
| 426 | int i; |
| 427 | int best; |
| 428 | |
| 429 | switch (prio) { |
| 430 | case (DMA_PRIO_HIGH): |
| 431 | best = 8; |
| 432 | break; |
| 433 | case (DMA_PRIO_MEDIUM): |
| 434 | best = 4; |
| 435 | break; |
| 436 | case (DMA_PRIO_LOW): |
| 437 | default: |
| 438 | best = 0; |
| 439 | break; |
| 440 | } |
| 441 | |
| 442 | for (i = best; i < IMX_DMA_CHANNELS; i++) { |
| 443 | if (!imx_dma_request(i, name)) { |
| 444 | *pdma_ch = i; |
| 445 | return 0; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | for (i = best - 1; i >= 0; i--) { |
| 450 | if (!imx_dma_request(i, name)) { |
| 451 | *pdma_ch = i; |
| 452 | return 0; |
| 453 | } |
| 454 | } |
| 455 | |
| 456 | printk(KERN_ERR "%s: no free DMA channel found\n", __FUNCTION__); |
| 457 | |
| 458 | return -ENODEV; |
| 459 | } |
| 460 | |
| 461 | static irqreturn_t dma_err_handler(int irq, void *dev_id, struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | { |
| 463 | int i, disr = DISR; |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 464 | struct imx_dma_channel *channel; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 465 | unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR; |
| 466 | |
| 467 | DISR = disr; |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 468 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
| 469 | channel = &imx_dma_channels[i]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 470 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 471 | if ((err_mask & 1 << i) && channel->name |
| 472 | && channel->err_handler) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | channel->err_handler(i, channel->data, regs); |
| 474 | continue; |
| 475 | } |
| 476 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 477 | imx_dma_channels[i].sg = NULL; |
| 478 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | if (DBTOSR & (1 << i)) { |
| 480 | printk(KERN_WARNING |
| 481 | "Burst timeout on channel %d (%s)\n", |
| 482 | i, channel->name); |
| 483 | DBTOSR |= (1 << i); |
| 484 | } |
| 485 | if (DRTOSR & (1 << i)) { |
| 486 | printk(KERN_WARNING |
| 487 | "Request timeout on channel %d (%s)\n", |
| 488 | i, channel->name); |
| 489 | DRTOSR |= (1 << i); |
| 490 | } |
| 491 | if (DSESR & (1 << i)) { |
| 492 | printk(KERN_WARNING |
| 493 | "Transfer timeout on channel %d (%s)\n", |
| 494 | i, channel->name); |
| 495 | DSESR |= (1 << i); |
| 496 | } |
| 497 | if (DBOSR & (1 << i)) { |
| 498 | printk(KERN_WARNING |
| 499 | "Buffer overflow timeout on channel %d (%s)\n", |
| 500 | i, channel->name); |
| 501 | DBOSR |= (1 << i); |
| 502 | } |
| 503 | } |
| 504 | return IRQ_HANDLED; |
| 505 | } |
| 506 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 507 | static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | { |
| 509 | int i, disr = DISR; |
| 510 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 511 | pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", |
| 512 | disr); |
| 513 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | DISR = disr; |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 515 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | if (disr & (1 << i)) { |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 517 | struct imx_dma_channel *channel = &imx_dma_channels[i]; |
| 518 | if (channel->name) { |
| 519 | if (imx_dma_sg_next(i, CNTR(i))) { |
| 520 | CCR(i) &= ~CCR_CEN; |
| 521 | mb(); |
| 522 | CCR(i) |= CCR_CEN; |
| 523 | } else { |
| 524 | if (channel->irq_handler) |
| 525 | channel->irq_handler(i, |
| 526 | channel->data, regs); |
| 527 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 528 | } else { |
| 529 | /* |
| 530 | * IRQ for an unregistered DMA channel: |
| 531 | * let's clear the interrupts and disable it. |
| 532 | */ |
| 533 | printk(KERN_WARNING |
| 534 | "spurious IRQ for DMA channel %d\n", i); |
| 535 | } |
| 536 | } |
| 537 | } |
| 538 | return IRQ_HANDLED; |
| 539 | } |
| 540 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 541 | static int __init imx_dma_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 542 | { |
| 543 | int ret; |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 544 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | |
| 546 | /* reset DMA module */ |
| 547 | DCR = DCR_DRST; |
| 548 | |
| 549 | ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); |
| 550 | if (ret) { |
| 551 | printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); |
| 552 | return ret; |
| 553 | } |
| 554 | |
| 555 | ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); |
| 556 | if (ret) { |
| 557 | printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); |
| 558 | free_irq(DMA_INT, NULL); |
| 559 | } |
| 560 | |
| 561 | /* enable DMA module */ |
| 562 | DCR = DCR_DEN; |
| 563 | |
| 564 | /* clear all interrupts */ |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 565 | DISR = (1 << IMX_DMA_CHANNELS) - 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 566 | |
| 567 | /* enable interrupts */ |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 568 | DIMR = (1 << IMX_DMA_CHANNELS) - 1; |
| 569 | |
| 570 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
| 571 | imx_dma_channels[i].sg = NULL; |
| 572 | imx_dma_channels[i].dma_num = i; |
| 573 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 574 | |
| 575 | return ret; |
| 576 | } |
| 577 | |
| 578 | arch_initcall(imx_dma_init); |
| 579 | |
Pavel Pisa | 999331a | 2006-04-02 16:58:37 +0100 | [diff] [blame] | 580 | EXPORT_SYMBOL(imx_dma_setup_single); |
| 581 | EXPORT_SYMBOL(imx_dma_setup_sg); |
| 582 | EXPORT_SYMBOL(imx_dma_setup_handlers); |
| 583 | EXPORT_SYMBOL(imx_dma_enable); |
| 584 | EXPORT_SYMBOL(imx_dma_disable); |
| 585 | EXPORT_SYMBOL(imx_dma_request); |
| 586 | EXPORT_SYMBOL(imx_dma_free); |
| 587 | EXPORT_SYMBOL(imx_dma_request_by_prio); |
| 588 | EXPORT_SYMBOL(imx_dma_channels); |